/*
 * $Id: xgxs16g.h,v 1.10.2.2 Broadcom SDK $
 * $Copyright: Copyright 2011 Broadcom Corporation.
 * This program is the proprietary software of Broadcom Corporation
 * and/or its licensors, and may only be used, duplicated, modified
 * or distributed pursuant to the terms and conditions of a separate,
 * written license agreement executed between you and Broadcom
 * (an "Authorized License").  Except as set forth in an Authorized
 * License, Broadcom grants no license (express or implied), right
 * to use, or waiver of any kind with respect to the Software, and
 * Broadcom expressly reserves all rights in and to the Software
 * and all intellectual property rights therein.  IF YOU HAVE
 * NO AUTHORIZED LICENSE, THEN YOU HAVE NO RIGHT TO USE THIS SOFTWARE
 * IN ANY WAY, AND SHOULD IMMEDIATELY NOTIFY BROADCOM AND DISCONTINUE
 * ALL USE OF THE SOFTWARE.  
 *  
 * Except as expressly set forth in the Authorized License,
 *  
 * 1.     This program, including its structure, sequence and organization,
 * constitutes the valuable trade secrets of Broadcom, and you shall use
 * all reasonable efforts to protect the confidentiality thereof,
 * and to use this information only in connection with your use of
 * Broadcom integrated circuit products.
 *  
 * 2.     TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS
 * PROVIDED "AS IS" AND WITH ALL FAULTS AND BROADCOM MAKES NO PROMISES,
 * REPRESENTATIONS OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY,
 * OR OTHERWISE, WITH RESPECT TO THE SOFTWARE.  BROADCOM SPECIFICALLY
 * DISCLAIMS ANY AND ALL IMPLIED WARRANTIES OF TITLE, MERCHANTABILITY,
 * NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF VIRUSES,
 * ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
 * CORRESPONDENCE TO DESCRIPTION. YOU ASSUME THE ENTIRE RISK ARISING
 * OUT OF USE OR PERFORMANCE OF THE SOFTWARE.
 * 
 * 3.     TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT SHALL
 * BROADCOM OR ITS LICENSORS BE LIABLE FOR (i) CONSEQUENTIAL,
 * INCIDENTAL, SPECIAL, INDIRECT, OR EXEMPLARY DAMAGES WHATSOEVER
 * ARISING OUT OF OR IN ANY WAY RELATING TO YOUR USE OF OR INABILITY
 * TO USE THE SOFTWARE EVEN IF BROADCOM HAS BEEN ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGES; OR (ii) ANY AMOUNT IN EXCESS OF
 * THE AMOUNT ACTUALLY PAID FOR THE SOFTWARE ITSELF OR USD 1.00,
 * WHICHEVER IS GREATER. THESE LIMITATIONS SHALL APPLY NOTWITHSTANDING
 * ANY FAILURE OF ESSENTIAL PURPOSE OF ANY LIMITED REMEDY.$
 *
 * File:        xgxs16g.h
 * Purpose:     16G 802.3ae Ethernet PHY
 */

#ifndef   _PHY_XGXS16G_H_
#define   _PHY_XGXS16G_H_

/* typedefs */ 
#define XGXS16G_LANE_NAME_LEN 30
typedef struct {
    uint16 serdes_id0;
    uint16 serdes_id2;
    char   name[XGXS16G_LANE_NAME_LEN];
} XGXS16G_DEV_DESC;

/* macros */

/* Macros ONLY used after initialization */
#define XGXS16G_16G_ID(_pc) \
     ((((XGXS16G_DEV_DESC *)((_pc) + 1))->serdes_id2) & SERDESID_SERDESID2_DR_16G_4L_MASK)
#define XGXS16G_13G_ID(_pc) \
     ((((((XGXS16G_DEV_DESC *)((_pc) + 1))->serdes_id2) >> 8) & 0xf) == 0x3)
#define XGXS16G_2p5G_ID(_pc) \
     (((((XGXS16G_DEV_DESC *)((_pc) + 1))->serdes_id2) & 0xff) == 0xf)

#define FEATURE_SPEED_100FX(_pc) (XGXS16G_13G_ID(_pc))
#define FEATURE_NEW_LANESWAP(_pc) (XGXS16G_13G_ID(_pc))

#define SERDES_ID0_TECH_PROC_40NM (1 << 7)


/****************************************************************************/
/*****  Starting below is auto-generated register macros from RDB files *****/
/****************************************************************************/

/**
 * m = memory, c = core, r = register, f = field, d = data.
 */
#if !defined(GET_FIELD) && !defined(SET_FIELD)
#define BRCM_ALIGN(c,r,f)   c##_##r##_##f##_ALIGN
#define BRCM_BITS(c,r,f)    c##_##r##_##f##_BITS
#define BRCM_MASK(c,r,f)    c##_##r##_##f##_MASK
#define BRCM_SHIFT(c,r,f)   c##_##r##_##f##_SHIFT

#define GET_FIELD(m,c,r,f) \
	((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)) << BRCM_ALIGN(c,r,f))

#define SET_FIELD(m,c,r,f,d) \
	((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d) >> BRCM_ALIGN(c,r,f)) << \
	 BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))) \
	)

#define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d)
#define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d)
#define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d)

#endif /* GET & SET */

/****************************************************************************
 * Core Enums.
 ***************************************************************************/
/****************************************************************************
 * Enums: combo_operationModes
 ***************************************************************************/
#define combo_operationModes_XGXS                          0
#define combo_operationModes_XGXG_nCC                      1
#define combo_operationModes_Indlanes                      6
#define combo_operationModes_PCI                           7
#define combo_operationModes_XGXS_nLQ                      8
#define combo_operationModes_XGXS_nLQnCC                   9
#define combo_operationModes_PBypass                       10
#define combo_operationModes_PBypass_nDSK                  11
#define combo_operationModes_ComboCoreMode                 12
#define combo_operationModes_Clocks_off                    15

/****************************************************************************
 * Enums: combo_actualSpeeds4
 ***************************************************************************/
#define combo_actualSpeeds4_dr_10M                         0
#define combo_actualSpeeds4_dr_100M                        1
#define combo_actualSpeeds4_dr_1G                          2
#define combo_actualSpeeds4_dr_2p5G                        3
#define combo_actualSpeeds4_dr_5G                          4
#define combo_actualSpeeds4_dr_6G                          5
#define combo_actualSpeeds4_dr_10G_HiG                     6
#define combo_actualSpeeds4_dr_10G_CX4                     7
#define combo_actualSpeeds4_dr_12G_HiG                     8
#define combo_actualSpeeds4_dr_12p5G                       9
#define combo_actualSpeeds4_dr_13G                         10
#define combo_actualSpeeds4_dr_15G                         11
#define combo_actualSpeeds4_dr_16G                         12

/****************************************************************************
 * Enums: combo_actualSpeeds5
 ***************************************************************************/
#define combo_actualSpeeds5_dr_10M                         0
#define combo_actualSpeeds5_dr_100M                        1
#define combo_actualSpeeds5_dr_1G                          2
#define combo_actualSpeeds5_dr_2p5G                        3
#define combo_actualSpeeds5_dr_5GX4                        4
#define combo_actualSpeeds5_dr_6GX4                        5
#define combo_actualSpeeds5_dr_10G_HiG                     6
#define combo_actualSpeeds5_dr_10G_CX4                     7
#define combo_actualSpeeds5_dr_12G_HiG                     8
#define combo_actualSpeeds5_dr_12p5GX4                     9
#define combo_actualSpeeds5_dr_13GX4                       10
#define combo_actualSpeeds5_dr_15GX4                       11
#define combo_actualSpeeds5_dr_16GX4                       12
#define combo_actualSpeeds5_dr_5G                          16
#define combo_actualSpeeds5_dr_6p4G                        17
#define combo_actualSpeeds5_dr_20GX4                       18
#define combo_actualSpeeds5_dr_25GX4                       19

/****************************************************************************
 * Enums: xgxs_operationModes
 ***************************************************************************/
#define xgxs_operationModes_XGXS                           0
#define xgxs_operationModes_XGXG_nCC                       1
#define xgxs_operationModes_Indlanes                       6
#define xgxs_operationModes_PCI                            7
#define xgxs_operationModes_XGXS_nLQ                       8
#define xgxs_operationModes_XGXS_nLQnCC                    9
#define xgxs_operationModes_PBypass                        10
#define xgxs_operationModes_PBypass_nDSK                   11
#define xgxs_operationModes_ComboCoreMode                  12
#define xgxs_operationModes_Clocks_off                     15

/****************************************************************************
 * Enums: xgxs_actualSpeeds4
 ***************************************************************************/
#define xgxs_actualSpeeds4_dr_10M                          0
#define xgxs_actualSpeeds4_dr_100M                         1
#define xgxs_actualSpeeds4_dr_1G                           2
#define xgxs_actualSpeeds4_dr_2p5G                         3
#define xgxs_actualSpeeds4_dr_5G                           4
#define xgxs_actualSpeeds4_dr_6G                           5
#define xgxs_actualSpeeds4_dr_10G_HiG                      6
#define xgxs_actualSpeeds4_dr_10G_CX4                      7
#define xgxs_actualSpeeds4_dr_12G_HiG                      8
#define xgxs_actualSpeeds4_dr_12p5G                        9
#define xgxs_actualSpeeds4_dr_13G                          10
#define xgxs_actualSpeeds4_dr_15G                          11
#define xgxs_actualSpeeds4_dr_16G                          12

/****************************************************************************
 * Enums: xgxs_actualSpeeds5
 ***************************************************************************/
#define xgxs_actualSpeeds5_dr_10M                          0
#define xgxs_actualSpeeds5_dr_100M                         1
#define xgxs_actualSpeeds5_dr_1G                           2
#define xgxs_actualSpeeds5_dr_2p5G                         3
#define xgxs_actualSpeeds5_dr_5GX4                         4
#define xgxs_actualSpeeds5_dr_6GX4                         5
#define xgxs_actualSpeeds5_dr_10G_HiG                      6
#define xgxs_actualSpeeds5_dr_10G_CX4                      7
#define xgxs_actualSpeeds5_dr_12G_HiG                      8
#define xgxs_actualSpeeds5_dr_12p5GX4                      9
#define xgxs_actualSpeeds5_dr_13GX4                        10
#define xgxs_actualSpeeds5_dr_15GX4                        11
#define xgxs_actualSpeeds5_dr_16GX4                        12
#define xgxs_actualSpeeds5_dr_5G                           16
#define xgxs_actualSpeeds5_dr_6p4G                         17
#define xgxs_actualSpeeds5_dr_20GX4                        18
#define xgxs_actualSpeeds5_dr_25GX4                        19

/* defines for Clause73 device */
#define CL73_AN_ADVERT0_REG   0x10
#define CL73_AN_ADVERT1_REG   0x11
#define CL73_AN_LP_ABILITY0_REG  0x13
#define CL73_AN_LP_ABILITY1_REG  0x14

#define CL73_AN_ADV_TECH_10G_KX4      (1 << 6) 
#define CL73_AN_ADV_TECH_1G_KX        (1 << 5)
#define CL73_AN_ADV_TECH_SPEEDS_MASK  (0x7 << 5)
#define CL73_AN_ADV_PAUSE             (1 << 10)
#define CL73_AN_ADV_ASYM_PAUSE        (1 << 11)


#define AER_MMD_CL73_AN  (0x3800 << 16)
#define READ_XGXS16G_AN_CL73_REG(_unit, _pc, _reg,_val) \
       XGXS16G_REG_READ((_unit), (_pc), 0x00, AER_MMD_CL73_AN | (_reg), (_val))
#define WRITE_XGXS16G_AN_CL73_REG(_unit, _pc,_reg, _val) \
       XGXS16G_REG_WRITE((_unit), (_pc), 0x00, AER_MMD_CL73_AN | (_reg), (_val))
#define MODIFY_XGXS16G_AN_CL73_REG(_unit, _pc, _reg, _val, _mask) \
       XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, AER_MMD_CL73_AN | (_reg), \
		(_val), (_mask))

/****************************************************************************
 * HXGS16G_IEEE_ieee0Blk
 ***************************************************************************/

/* IEEE MII control register */
#define READ_XGXS16G_IEEE0BLK_IEEECONTROL0r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00000000, (_val))
#define WRITE_XGXS16G_IEEE0BLK_IEEECONTROL0r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00000000, (_val))
#define MODIFY_XGXS16G_IEEE0BLK_IEEECONTROL0r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00000000, (_val), (_mask))

/* IEEE MII status register */
#define READ_XGXS16G_IEEE0BLK_IEEESTATUS0r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00000001, (_val))
#define WRITE_XGXS16G_IEEE0BLK_IEEESTATUS0r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00000001, (_val))
#define MODIFY_XGXS16G_IEEE0BLK_IEEESTATUS0r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00000001, (_val), (_mask))

/* IEEE MII TX disable register */
#define READ_XGXS16G_IEEE0BLK_IEEETXDISABLEr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00000009, (_val))
#define WRITE_XGXS16G_IEEE0BLK_IEEETXDISABLEr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00000009, (_val))
#define MODIFY_XGXS16G_IEEE0BLK_IEEETXDISABLEr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00000009, (_val), (_mask))


/****************************************************************************
 * XGXS16G_IEEE_ieee1Blk
 ***************************************************************************/

/* IEEE MII control register */
#define READ_XGXS16G_IEEE1BLK_IEEECONTROL1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00000010, (_val))
#define WRITE_XGXS16G_IEEE1BLK_IEEECONTROL1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00000010, (_val))
#define MODIFY_XGXS16G_IEEE1BLK_IEEECONTROL1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00000010, (_val), (_mask))


/****************************************************************************
 * XGXS16G_USER_XgxsBlk0
 ***************************************************************************/

/* XGXG control register */
#define READ_XGXS16G_XGXSBLK0_XGXSCONTROLr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008000, (_val))
#define WRITE_XGXS16G_XGXSBLK0_XGXSCONTROLr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008000, (_val))
#define MODIFY_XGXS16G_XGXSBLK0_XGXSCONTROLr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008000, (_val), (_mask))

/* XGXG status register */
#define READ_XGXS16G_XGXSBLK0_XGXSSTATUSr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008001, (_val))
#define WRITE_XGXS16G_XGXSBLK0_XGXSSTATUSr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008001, (_val))
#define MODIFY_XGXS16G_XGXSBLK0_XGXSSTATUSr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008001, (_val), (_mask))

/* XGMII idle control character register */
#define READ_XGXS16G_XGXSBLK0_XGMIIIDLEr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008002, (_val))
#define WRITE_XGXS16G_XGXSBLK0_XGMIIIDLEr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008002, (_val))
#define MODIFY_XGXS16G_XGXSBLK0_XGMIIIDLEr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008002, (_val), (_mask))

/* XGMII sync control character register */
#define READ_XGXS16G_XGXSBLK0_XGMIISYNCr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008003, (_val))
#define WRITE_XGXS16G_XGXSBLK0_XGMIISYNCr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008003, (_val))
#define MODIFY_XGXS16G_XGXSBLK0_XGMIISYNCr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008003, (_val), (_mask))

/* XGMII skip control character register */
#define READ_XGXS16G_XGXSBLK0_XGMIISKIPr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008004, (_val))
#define WRITE_XGXS16G_XGXSBLK0_XGMIISKIPr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008004, (_val))
#define MODIFY_XGXS16G_XGXSBLK0_XGMIISKIPr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008004, (_val), (_mask))

/* XGMII sop & eop control character register */
#define READ_XGXS16G_XGXSBLK0_XGMIISOPEOPr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008005, (_val))
#define WRITE_XGXS16G_XGXSBLK0_XGMIISOPEOPr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008005, (_val))
#define MODIFY_XGXS16G_XGXSBLK0_XGMIISOPEOPr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008005, (_val), (_mask))

/* XGMII alignment & eror control character register */
#define READ_XGXS16G_XGXSBLK0_XGMIIALIGNr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008006, (_val))
#define WRITE_XGXS16G_XGXSBLK0_XGMIIALIGNr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008006, (_val))
#define MODIFY_XGXS16G_XGXSBLK0_XGMIIALIGNr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008006, (_val), (_mask))

/* XGMII receive control register */
#define READ_XGXS16G_XGXSBLK0_XGMIIRCONTROLr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008007, (_val))
#define WRITE_XGXS16G_XGXSBLK0_XGMIIRCONTROLr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008007, (_val))
#define MODIFY_XGXS16G_XGXSBLK0_XGMIIRCONTROLr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008007, (_val), (_mask))

/* XGMII transmit control register */
#define READ_XGXS16G_XGXSBLK0_XGMIITCONTROLr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008008, (_val))
#define WRITE_XGXS16G_XGXSBLK0_XGMIITCONTROLr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008008, (_val))
#define MODIFY_XGXS16G_XGXSBLK0_XGMIITCONTROLr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008008, (_val), (_mask))

/* XGMII ||A|| minimum swap spacing */
#define READ_XGXS16G_XGXSBLK0_XGMIISWAPr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008009, (_val))
#define WRITE_XGXS16G_XGXSBLK0_XGMIISWAPr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008009, (_val))
#define MODIFY_XGXS16G_XGXSBLK0_XGMIISWAPr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008009, (_val), (_mask))

/* LSS information byte resgister */
#define READ_XGXS16G_XGXSBLK0_LSSLSIDr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000800a, (_val))
#define WRITE_XGXS16G_XGXSBLK0_LSSLSIDr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000800a, (_val))
#define MODIFY_XGXS16G_XGXSBLK0_LSSLSIDr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000800a, (_val), (_mask))

/* LSS transmit information byte resgister */
#define READ_XGXS16G_XGXSBLK0_LSSTINFOr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000800b, (_val))
#define WRITE_XGXS16G_XGXSBLK0_LSSTINFOr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000800b, (_val))
#define MODIFY_XGXS16G_XGXSBLK0_LSSTINFOr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000800b, (_val), (_mask))

/* LSS receive information byte resgister */
#define READ_XGXS16G_XGXSBLK0_LSSRINFOr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000800c, (_val))
#define WRITE_XGXS16G_XGXSBLK0_LSSRINFOr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000800c, (_val))
#define MODIFY_XGXS16G_XGXSBLK0_LSSRINFOr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000800c, (_val), (_mask))

/* MMD select register */
#define READ_XGXS16G_XGXSBLK0_MMDSELECTr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000800d, (_val))
#define WRITE_XGXS16G_XGXSBLK0_MMDSELECTr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000800d, (_val))
#define MODIFY_XGXS16G_XGXSBLK0_MMDSELECTr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000800d, (_val), (_mask))

/* Miscellaneous control 1 register */
#define READ_XGXS16G_XGXSBLK0_MISCCONTROL1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000800e, (_val))
#define WRITE_XGXS16G_XGXSBLK0_MISCCONTROL1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000800e, (_val))
#define MODIFY_XGXS16G_XGXSBLK0_MISCCONTROL1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000800e, (_val), (_mask))

/* Block Address register */
#define READ_XGXS16G_XGXSBLK0_BLOCKADDRESSr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000800f, (_val))
#define WRITE_XGXS16G_XGXSBLK0_BLOCKADDRESSr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000800f, (_val))
#define MODIFY_XGXS16G_XGXSBLK0_BLOCKADDRESSr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000800f, (_val), (_mask))


/****************************************************************************
 * XGXS16G_USER_XgxsBlk1
 ***************************************************************************/

/* Lane deskew register */
#define READ_XGXS16G_XGXSBLK1_DESKEWr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008010, (_val))
#define WRITE_XGXS16G_XGXSBLK1_DESKEWr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008010, (_val))
#define MODIFY_XGXS16G_XGXSBLK1_DESKEWr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008010, (_val), (_mask))

/* Link ||A|| column timeout value register */
#define READ_XGXS16G_XGXSBLK1_LINKr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008011, (_val))
#define WRITE_XGXS16G_XGXSBLK1_LINKr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008011, (_val))
#define MODIFY_XGXS16G_XGXSBLK1_LINKr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008011, (_val), (_mask))

/* Receive test control register */
#define READ_XGXS16G_XGXSBLK1_TESTRXr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008012, (_val))
#define WRITE_XGXS16G_XGXSBLK1_TESTRXr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008012, (_val))
#define MODIFY_XGXS16G_XGXSBLK1_TESTRXr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008012, (_val), (_mask))

/* Transmit test control register */
#define READ_XGXS16G_XGXSBLK1_TESTTXr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008013, (_val))
#define WRITE_XGXS16G_XGXSBLK1_TESTTXr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008013, (_val))
#define MODIFY_XGXS16G_XGXSBLK1_TESTTXr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008013, (_val), (_mask))

/* XGXS test control register */
#define READ_XGXS16G_XGXSBLK1_TESTXGr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008014, (_val))
#define WRITE_XGXS16G_XGXSBLK1_TESTXGr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008014, (_val))
#define MODIFY_XGXS16G_XGXSBLK1_TESTXGr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008014, (_val), (_mask))

/* Lane control 0 register */
#define READ_XGXS16G_XGXSBLK1_LANECTRL0r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008015, (_val))
#define WRITE_XGXS16G_XGXSBLK1_LANECTRL0r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008015, (_val))
#define MODIFY_XGXS16G_XGXSBLK1_LANECTRL0r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008015, (_val), (_mask))

/* Lane control 1 register */
#define READ_XGXS16G_XGXSBLK1_LANECTRL1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008016, (_val))
#define WRITE_XGXS16G_XGXSBLK1_LANECTRL1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008016, (_val))
#define MODIFY_XGXS16G_XGXSBLK1_LANECTRL1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008016, (_val), (_mask))

/* Lane control 2 register */
#define READ_XGXS16G_XGXSBLK1_LANECTRL2r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008017, (_val))
#define WRITE_XGXS16G_XGXSBLK1_LANECTRL2r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008017, (_val))
#define MODIFY_XGXS16G_XGXSBLK1_LANECTRL2r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008017, (_val), (_mask))

/* Lane control 3 register */
#define READ_XGXS16G_XGXSBLK1_LANECTRL3r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008018, (_val))
#define WRITE_XGXS16G_XGXSBLK1_LANECTRL3r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008018, (_val))
#define MODIFY_XGXS16G_XGXSBLK1_LANECTRL3r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008018, (_val), (_mask))

/* Lane PRBS control register */
#define READ_XGXS16G_XGXSBLK1_LANEPRBSr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008019, (_val))
#define WRITE_XGXS16G_XGXSBLK1_LANEPRBSr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008019, (_val))
#define MODIFY_XGXS16G_XGXSBLK1_LANEPRBSr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008019, (_val), (_mask))

/* Lane test control register */
#define READ_XGXS16G_XGXSBLK1_LANETESTr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000801a, (_val))
#define WRITE_XGXS16G_XGXSBLK1_LANETESTr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000801a, (_val))
#define MODIFY_XGXS16G_XGXSBLK1_LANETESTr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000801a, (_val), (_mask))

/* LSS, ||Q|| column count register */
#define READ_XGXS16G_XGXSBLK1_LSSREVNTr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000801b, (_val))
#define WRITE_XGXS16G_XGXSBLK1_LSSREVNTr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000801b, (_val))
#define MODIFY_XGXS16G_XGXSBLK1_LSSREVNTr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000801b, (_val), (_mask))

/* Lane deskew event count register */
#define READ_XGXS16G_XGXSBLK1_DSKEVNTr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000801c, (_val))
#define WRITE_XGXS16G_XGXSBLK1_DSKEVNTr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000801c, (_val))
#define MODIFY_XGXS16G_XGXSBLK1_DSKEVNTr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000801c, (_val), (_mask))

/* Bad ||A|| column count register */
#define READ_XGXS16G_XGXSBLK1_AERREVNTr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000801d, (_val))
#define WRITE_XGXS16G_XGXSBLK1_AERREVNTr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000801d, (_val))
#define MODIFY_XGXS16G_XGXSBLK1_AERREVNTr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000801d, (_val), (_mask))

/* Clock compensation event count register */
#define READ_XGXS16G_XGXSBLK1_CKCMPEVNTr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000801e, (_val))
#define WRITE_XGXS16G_XGXSBLK1_CKCMPEVNTr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000801e, (_val))
#define MODIFY_XGXS16G_XGXSBLK1_CKCMPEVNTr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000801e, (_val), (_mask))

/****************************************************************************
 * XGXS16G_10G_TX_BERT
 ***************************************************************************/

/****************************************************************************
 * XGXS16G_10G_RX_BERT
 ***************************************************************************/

/****************************************************************************
 * XGXS16G_USER_PLL
 ***************************************************************************/

/* PLL status register */
#define READ_XGXS16G_PLL_PLLSTATUSr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008050, (_val))
#define WRITE_XGXS16G_PLL_PLLSTATUSr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008050, (_val))
#define MODIFY_XGXS16G_PLL_PLLSTATUSr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008050, (_val), (_mask))

/* PLL control register */
#define READ_XGXS16G_PLL_PLLCONTROLr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008051, (_val))
#define WRITE_XGXS16G_PLL_PLLCONTROLr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008051, (_val))
#define MODIFY_XGXS16G_PLL_PLLCONTROLr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008051, (_val), (_mask))

/* PLL start up state machine vco timers */
#define READ_XGXS16G_PLL_PLLTIMER1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008052, (_val))
#define WRITE_XGXS16G_PLL_PLLTIMER1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008052, (_val))
#define MODIFY_XGXS16G_PLL_PLLTIMER1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008052, (_val), (_mask))

/* PLL start up state machine retry timer */
#define READ_XGXS16G_PLL_PLLTIMER2r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008053, (_val))
#define WRITE_XGXS16G_PLL_PLLTIMER2r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008053, (_val))
#define MODIFY_XGXS16G_PLL_PLLTIMER2r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008053, (_val), (_mask))

/* PLL start up state machine freq. detect timer */
#define READ_XGXS16G_PLL_PLLTIMER3r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008054, (_val))
#define WRITE_XGXS16G_PLL_PLLTIMER3r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008054, (_val))
#define MODIFY_XGXS16G_PLL_PLLTIMER3r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008054, (_val), (_mask))

/* PLL vco range control state machine */
#define READ_XGXS16G_PLL_CAPCONTROLr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008055, (_val))
#define WRITE_XGXS16G_PLL_CAPCONTROLr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008055, (_val))
#define MODIFY_XGXS16G_PLL_CAPCONTROLr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008055, (_val), (_mask))

/* Currently unused */
#define READ_XGXS16G_PLL_AMPCONTROLr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008056, (_val))
#define WRITE_XGXS16G_PLL_AMPCONTROLr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008056, (_val))
#define MODIFY_XGXS16G_PLL_AMPCONTROLr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008056, (_val), (_mask))

/* Frequency detector control */
#define READ_XGXS16G_PLL_FREQDETCOUNTERr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008057, (_val))
#define WRITE_XGXS16G_PLL_FREQDETCOUNTERr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008057, (_val))
#define MODIFY_XGXS16G_PLL_FREQDETCOUNTERr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008057, (_val), (_mask))

/* PLL analog status */
#define READ_XGXS16G_PLL_PLLASTATUS1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008058, (_val))
#define WRITE_XGXS16G_PLL_PLLASTATUS1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008058, (_val))
#define MODIFY_XGXS16G_PLL_PLLASTATUS1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008058, (_val), (_mask))

/* PLL analog controls */
#define READ_XGXS16G_PLL_PLLCLOCKGENr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000805a, (_val))
#define WRITE_XGXS16G_PLL_PLLCLOCKGENr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000805a, (_val))
#define MODIFY_XGXS16G_PLL_PLLCLOCKGENr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000805a, (_val), (_mask))

/* PLL analog controls */
#define READ_XGXS16G_PLL_PLLNDIVr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000805b, (_val))
#define WRITE_XGXS16G_PLL_PLLNDIVr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000805b, (_val))
#define MODIFY_XGXS16G_PLL_PLLNDIVr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000805b, (_val), (_mask))

/* PLL analog controls */
#define READ_XGXS16G_PLL_PLLBGLQPr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000805c, (_val))
#define WRITE_XGXS16G_PLL_PLLBGLQPr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000805c, (_val))
#define MODIFY_XGXS16G_PLL_PLLBGLQPr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000805c, (_val), (_mask))

/* PLL analog controls */
#define READ_XGXS16G_PLL_PLLTESTKVHr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000805d, (_val))
#define WRITE_XGXS16G_PLL_PLLTESTKVHr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000805d, (_val))
#define MODIFY_XGXS16G_PLL_PLLTESTKVHr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000805d, (_val), (_mask))

/* PLL analog controls */
#define READ_XGXS16G_PLL_PLLACONTROL5r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000805e, (_val))
#define WRITE_XGXS16G_PLL_PLLACONTROL5r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000805e, (_val))
#define MODIFY_XGXS16G_PLL_PLLACONTROL5r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000805e, (_val), (_mask))


/****************************************************************************
 * XGXS16G_USER_TX0
 ***************************************************************************/

/* Tx analog status 0 register */
#define READ_XGXS16G_TX0_TX_ASTATUS0r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008060, (_val))
#define WRITE_XGXS16G_TX0_TX_ASTATUS0r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008060, (_val))
#define MODIFY_XGXS16G_TX0_TX_ASTATUS0r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008060, (_val), (_mask))

/* Tx analog control 0 register */
#define READ_XGXS16G_TX0_TX_ACONTROL0r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008061, (_val))
#define WRITE_XGXS16G_TX0_TX_ACONTROL0r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008061, (_val))
#define MODIFY_XGXS16G_TX0_TX_ACONTROL0r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008061, (_val), (_mask))

/* Tx test mux data 0 register */
#define READ_XGXS16G_TX0_TX_MDATA0r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008062, (_val))
#define WRITE_XGXS16G_TX0_TX_MDATA0r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008062, (_val))
#define MODIFY_XGXS16G_TX0_TX_MDATA0r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008062, (_val), (_mask))

/* Tx test mux data 1 register */
#define READ_XGXS16G_TX0_TX_MDATA1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008063, (_val))
#define WRITE_XGXS16G_TX0_TX_MDATA1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008063, (_val))
#define MODIFY_XGXS16G_TX0_TX_MDATA1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008063, (_val), (_mask))

/* Tx analog status 1 register */
#define READ_XGXS16G_TX0_TX_ASTATUS1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008064, (_val))
#define WRITE_XGXS16G_TX0_TX_ASTATUS1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008064, (_val))
#define MODIFY_XGXS16G_TX0_TX_ASTATUS1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008064, (_val), (_mask))

/* Tx reserved analog control register */
#define READ_XGXS16G_TX0_TX_BGVCMr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008065, (_val))
#define WRITE_XGXS16G_TX0_TX_BGVCMr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008065, (_val))
#define MODIFY_XGXS16G_TX0_TX_BGVCMr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008065, (_val), (_mask))

/* Tx reserved analog control register */
#define READ_XGXS16G_TX0_TX_IBUFF_1T2Tr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008066, (_val))
#define WRITE_XGXS16G_TX0_TX_IBUFF_1T2Tr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008066, (_val))
#define MODIFY_XGXS16G_TX0_TX_IBUFF_1T2Tr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008066, (_val), (_mask))

/* Tx reserved analog control register */
#define READ_XGXS16G_TX0_TX_DRIVERr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008067, (_val))
#define WRITE_XGXS16G_TX0_TX_DRIVERr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008067, (_val))
#define MODIFY_XGXS16G_TX0_TX_DRIVERr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008067, (_val), (_mask))


/****************************************************************************
 * XGXS16G_USER_TX1
 ***************************************************************************/

/* Tx analog status 0 register */
#define READ_XGXS16G_TX1_TX_ASTATUS0r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008070, (_val))
#define WRITE_XGXS16G_TX1_TX_ASTATUS0r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008070, (_val))
#define MODIFY_XGXS16G_TX1_TX_ASTATUS0r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008070, (_val), (_mask))

/* Tx analog control 0 register */
#define READ_XGXS16G_TX1_TX_ACONTROL0r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008071, (_val))
#define WRITE_XGXS16G_TX1_TX_ACONTROL0r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008071, (_val))
#define MODIFY_XGXS16G_TX1_TX_ACONTROL0r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008071, (_val), (_mask))

/* Tx test mux data 0 register */
#define READ_XGXS16G_TX1_TX_MDATA0r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008072, (_val))
#define WRITE_XGXS16G_TX1_TX_MDATA0r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008072, (_val))
#define MODIFY_XGXS16G_TX1_TX_MDATA0r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008072, (_val), (_mask))

/* Tx test mux data 1 register */
#define READ_XGXS16G_TX1_TX_MDATA1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008073, (_val))
#define WRITE_XGXS16G_TX1_TX_MDATA1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008073, (_val))
#define MODIFY_XGXS16G_TX1_TX_MDATA1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008073, (_val), (_mask))

/* Tx analog status 1 register */
#define READ_XGXS16G_TX1_TX_ASTATUS1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008074, (_val))
#define WRITE_XGXS16G_TX1_TX_ASTATUS1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008074, (_val))
#define MODIFY_XGXS16G_TX1_TX_ASTATUS1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008074, (_val), (_mask))

/* Tx reserved analog control register */
#define READ_XGXS16G_TX1_TX_BGVCMr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008075, (_val))
#define WRITE_XGXS16G_TX1_TX_BGVCMr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008075, (_val))
#define MODIFY_XGXS16G_TX1_TX_BGVCMr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008075, (_val), (_mask))

/* Tx reserved analog control register */
#define READ_XGXS16G_TX1_TX_IBUFF_1T2Tr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008076, (_val))
#define WRITE_XGXS16G_TX1_TX_IBUFF_1T2Tr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008076, (_val))
#define MODIFY_XGXS16G_TX1_TX_IBUFF_1T2Tr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008076, (_val), (_mask))

/* Tx reserved analog control register */
#define READ_XGXS16G_TX1_TX_DRIVERr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008077, (_val))
#define WRITE_XGXS16G_TX1_TX_DRIVERr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008077, (_val))
#define MODIFY_XGXS16G_TX1_TX_DRIVERr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008077, (_val), (_mask))


/****************************************************************************
 * XGXS16G_USER_TX2
 ***************************************************************************/

/* Tx analog status 0 register */
#define READ_XGXS16G_TX2_TX_ASTATUS0r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008080, (_val))
#define WRITE_XGXS16G_TX2_TX_ASTATUS0r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008080, (_val))
#define MODIFY_XGXS16G_TX2_TX_ASTATUS0r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008080, (_val), (_mask))

/* Tx analog control 0 register */
#define READ_XGXS16G_TX2_TX_ACONTROL0r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008081, (_val))
#define WRITE_XGXS16G_TX2_TX_ACONTROL0r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008081, (_val))
#define MODIFY_XGXS16G_TX2_TX_ACONTROL0r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008081, (_val), (_mask))

/* Tx test mux data 0 register */
#define READ_XGXS16G_TX2_TX_MDATA0r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008082, (_val))
#define WRITE_XGXS16G_TX2_TX_MDATA0r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008082, (_val))
#define MODIFY_XGXS16G_TX2_TX_MDATA0r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008082, (_val), (_mask))

/* Tx test mux data 1 register */
#define READ_XGXS16G_TX2_TX_MDATA1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008083, (_val))
#define WRITE_XGXS16G_TX2_TX_MDATA1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008083, (_val))
#define MODIFY_XGXS16G_TX2_TX_MDATA1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008083, (_val), (_mask))

/* Tx analog status 1 register */
#define READ_XGXS16G_TX2_TX_ASTATUS1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008084, (_val))
#define WRITE_XGXS16G_TX2_TX_ASTATUS1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008084, (_val))
#define MODIFY_XGXS16G_TX2_TX_ASTATUS1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008084, (_val), (_mask))

/* Tx reserved analog control register */
#define READ_XGXS16G_TX2_TX_BGVCMr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008085, (_val))
#define WRITE_XGXS16G_TX2_TX_BGVCMr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008085, (_val))
#define MODIFY_XGXS16G_TX2_TX_BGVCMr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008085, (_val), (_mask))

/* Tx reserved analog control register */
#define READ_XGXS16G_TX2_TX_IBUFF_1T2Tr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008086, (_val))
#define WRITE_XGXS16G_TX2_TX_IBUFF_1T2Tr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008086, (_val))
#define MODIFY_XGXS16G_TX2_TX_IBUFF_1T2Tr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008086, (_val), (_mask))

/* Tx reserved analog control register */
#define READ_XGXS16G_TX2_TX_DRIVERr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008087, (_val))
#define WRITE_XGXS16G_TX2_TX_DRIVERr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008087, (_val))
#define MODIFY_XGXS16G_TX2_TX_DRIVERr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008087, (_val), (_mask))


/****************************************************************************
 * XGXS16G_USER_TX3
 ***************************************************************************/

/* Tx analog status 0 register */
#define READ_XGXS16G_TX3_TX_ASTATUS0r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008090, (_val))
#define WRITE_XGXS16G_TX3_TX_ASTATUS0r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008090, (_val))
#define MODIFY_XGXS16G_TX3_TX_ASTATUS0r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008090, (_val), (_mask))

/* Tx analog control 0 register */
#define READ_XGXS16G_TX3_TX_ACONTROL0r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008091, (_val))
#define WRITE_XGXS16G_TX3_TX_ACONTROL0r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008091, (_val))
#define MODIFY_XGXS16G_TX3_TX_ACONTROL0r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008091, (_val), (_mask))

/* Tx test mux data 0 register */
#define READ_XGXS16G_TX3_TX_MDATA0r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008092, (_val))
#define WRITE_XGXS16G_TX3_TX_MDATA0r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008092, (_val))
#define MODIFY_XGXS16G_TX3_TX_MDATA0r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008092, (_val), (_mask))

/* Tx test mux data 1 register */
#define READ_XGXS16G_TX3_TX_MDATA1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008093, (_val))
#define WRITE_XGXS16G_TX3_TX_MDATA1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008093, (_val))
#define MODIFY_XGXS16G_TX3_TX_MDATA1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008093, (_val), (_mask))

/* Tx analog status 1 register */
#define READ_XGXS16G_TX3_TX_ASTATUS1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008094, (_val))
#define WRITE_XGXS16G_TX3_TX_ASTATUS1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008094, (_val))
#define MODIFY_XGXS16G_TX3_TX_ASTATUS1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008094, (_val), (_mask))

/* Tx reserved analog control register */
#define READ_XGXS16G_TX3_TX_BGVCMr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008095, (_val))
#define WRITE_XGXS16G_TX3_TX_BGVCMr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008095, (_val))
#define MODIFY_XGXS16G_TX3_TX_BGVCMr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008095, (_val), (_mask))

/* Tx reserved analog control register */
#define READ_XGXS16G_TX3_TX_IBUFF_1T2Tr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008096, (_val))
#define WRITE_XGXS16G_TX3_TX_IBUFF_1T2Tr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008096, (_val))
#define MODIFY_XGXS16G_TX3_TX_IBUFF_1T2Tr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008096, (_val), (_mask))

/* Tx reserved analog control register */
#define READ_XGXS16G_TX3_TX_DRIVERr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008097, (_val))
#define WRITE_XGXS16G_TX3_TX_DRIVERr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008097, (_val))
#define MODIFY_XGXS16G_TX3_TX_DRIVERr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008097, (_val), (_mask))


/****************************************************************************
 * XGXS16G_USER_TX_All
 ***************************************************************************/

/* Tx analog status 0 register */
#define READ_XGXS16G_TX_ALL_TX_ASTATUS0r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080a0, (_val))
#define WRITE_XGXS16G_TX_ALL_TX_ASTATUS0r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080a0, (_val))
#define MODIFY_XGXS16G_TX_ALL_TX_ASTATUS0r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a0, (_val), (_mask))

/* Tx analog control 0 register */
#define READ_XGXS16G_TX_ALL_TX_ACONTROL0r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080a1, (_val))
#define WRITE_XGXS16G_TX_ALL_TX_ACONTROL0r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080a1, (_val))
#define MODIFY_XGXS16G_TX_ALL_TX_ACONTROL0r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a1, (_val), (_mask))

/* Tx test mux data 0 register */
#define READ_XGXS16G_TX_ALL_TX_MDATA0r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080a2, (_val))
#define WRITE_XGXS16G_TX_ALL_TX_MDATA0r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080a2, (_val))
#define MODIFY_XGXS16G_TX_ALL_TX_MDATA0r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a2, (_val), (_mask))

/* Tx test mux data 1 register */
#define READ_XGXS16G_TX_ALL_TX_MDATA1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080a3, (_val))
#define WRITE_XGXS16G_TX_ALL_TX_MDATA1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080a3, (_val))
#define MODIFY_XGXS16G_TX_ALL_TX_MDATA1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a3, (_val), (_mask))

/* Tx analog status 1 register */
#define READ_XGXS16G_TX_ALL_TX_ASTATUS1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080a4, (_val))
#define WRITE_XGXS16G_TX_ALL_TX_ASTATUS1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080a4, (_val))
#define MODIFY_XGXS16G_TX_ALL_TX_ASTATUS1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a4, (_val), (_mask))

/* Tx reserved analog control register */
#define READ_XGXS16G_TX_ALL_TX_BGVCMr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080a5, (_val))
#define WRITE_XGXS16G_TX_ALL_TX_BGVCMr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080a5, (_val))
#define MODIFY_XGXS16G_TX_ALL_TX_BGVCMr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a5, (_val), (_mask))

/* Tx reserved analog control register */
#define READ_XGXS16G_TX_ALL_TX_IBUFF_1T2Tr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080a6, (_val))
#define WRITE_XGXS16G_TX_ALL_TX_IBUFF_1T2Tr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080a6, (_val))
#define MODIFY_XGXS16G_TX_ALL_TX_IBUFF_1T2Tr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a6, (_val), (_mask))

/* Tx reserved analog control register */
#define READ_XGXS16G_TX_ALL_TX_DRIVERr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080a7, (_val))
#define WRITE_XGXS16G_TX_ALL_TX_DRIVERr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080a7, (_val))
#define MODIFY_XGXS16G_TX_ALL_TX_DRIVERr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a7, (_val), (_mask))


/****************************************************************************
 * XGXS16G_USER_RX0
 ***************************************************************************/

/* Rx lane status register */
#define READ_XGXS16G_RX0_RX_STATUSr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080b0, (_val))
#define WRITE_XGXS16G_RX0_RX_STATUSr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080b0, (_val))
#define MODIFY_XGXS16G_RX0_RX_STATUSr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080b0, (_val), (_mask))

/* Rx lane control register */
#define READ_XGXS16G_RX0_RX_CONTROLr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080b1, (_val))
#define WRITE_XGXS16G_RX0_RX_CONTROLr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080b1, (_val))
#define MODIFY_XGXS16G_RX0_RX_CONTROLr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080b1, (_val), (_mask))

/* Rx lane control register */
#define READ_XGXS16G_RX0_RX_TESTr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080b8, (_val))
#define WRITE_XGXS16G_RX0_RX_TESTr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080b8, (_val))
#define MODIFY_XGXS16G_RX0_RX_TESTr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080b8, (_val), (_mask))

/* Rx 1G Control register */
#define READ_XGXS16G_RX0_RX_CONTROL_1G_TYPEr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080b9, (_val))
#define WRITE_XGXS16G_RX0_RX_CONTROL_1G_TYPEr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080b9, (_val))
#define MODIFY_XGXS16G_RX0_RX_CONTROL_1G_TYPEr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080b9, (_val), (_mask))

/* Rx analog status register */
#define READ_XGXS16G_RX0_RX_ASTATUSr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080bb, (_val))
#define WRITE_XGXS16G_RX0_RX_ASTATUSr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080bb, (_val))
#define MODIFY_XGXS16G_RX0_RX_ASTATUSr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080bb, (_val), (_mask))

/* Rx reserved analog control register */
#define READ_XGXS16G_RX0_RX_ANALOGBIAS0r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080bc, (_val))
#define WRITE_XGXS16G_RX0_RX_ANALOGBIAS0r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080bc, (_val))
#define MODIFY_XGXS16G_RX0_RX_ANALOGBIAS0r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080bc, (_val), (_mask))

/* Rx reserved analog control register */
#define READ_XGXS16G_RX0_RX_ANALOGBIAS1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080bd, (_val))
#define WRITE_XGXS16G_RX0_RX_ANALOGBIAS1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080bd, (_val))
#define MODIFY_XGXS16G_RX0_RX_ANALOGBIAS1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080bd, (_val), (_mask))

/* Rx reserved analog control register */
#define READ_XGXS16G_RX0_RX_ANALOGBIAS2r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080be, (_val))
#define WRITE_XGXS16G_RX0_RX_ANALOGBIAS2r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080be, (_val))
#define MODIFY_XGXS16G_RX0_RX_ANALOGBIAS2r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080be, (_val), (_mask))


/****************************************************************************
 * XGXS16G_USER_RX1
 ***************************************************************************/

/* Rx lane status register */
#define READ_XGXS16G_RX1_RX_STATUSr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080c0, (_val))
#define WRITE_XGXS16G_RX1_RX_STATUSr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080c0, (_val))
#define MODIFY_XGXS16G_RX1_RX_STATUSr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080c0, (_val), (_mask))

/* Rx lane control register */
#define READ_XGXS16G_RX1_RX_CONTROLr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080c1, (_val))
#define WRITE_XGXS16G_RX1_RX_CONTROLr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080c1, (_val))
#define MODIFY_XGXS16G_RX1_RX_CONTROLr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080c1, (_val), (_mask))

/* Rx lane control register */
#define READ_XGXS16G_RX1_RX_TESTr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080c8, (_val))
#define WRITE_XGXS16G_RX1_RX_TESTr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080c8, (_val))
#define MODIFY_XGXS16G_RX1_RX_TESTr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080c8, (_val), (_mask))

/* Rx 1G Control register */
#define READ_XGXS16G_RX1_RX_CONTROL_1G_TYPEr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080c9, (_val))
#define WRITE_XGXS16G_RX1_RX_CONTROL_1G_TYPEr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080c9, (_val))
#define MODIFY_XGXS16G_RX1_RX_CONTROL_1G_TYPEr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080c9, (_val), (_mask))

/* Rx analog status register */
#define READ_XGXS16G_RX1_RX_ASTATUSr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080cb, (_val))
#define WRITE_XGXS16G_RX1_RX_ASTATUSr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080cb, (_val))
#define MODIFY_XGXS16G_RX1_RX_ASTATUSr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080cb, (_val), (_mask))

/* Rx reserved analog control register */
#define READ_XGXS16G_RX1_RX_ANALOGBIAS0r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080cc, (_val))
#define WRITE_XGXS16G_RX1_RX_ANALOGBIAS0r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080cc, (_val))
#define MODIFY_XGXS16G_RX1_RX_ANALOGBIAS0r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080cc, (_val), (_mask))

/* Rx reserved analog control register */
#define READ_XGXS16G_RX1_RX_ANALOGBIAS1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080cd, (_val))
#define WRITE_XGXS16G_RX1_RX_ANALOGBIAS1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080cd, (_val))
#define MODIFY_XGXS16G_RX1_RX_ANALOGBIAS1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080cd, (_val), (_mask))

/* Rx reserved analog control register */
#define READ_XGXS16G_RX1_RX_ANALOGBIAS2r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080ce, (_val))
#define WRITE_XGXS16G_RX1_RX_ANALOGBIAS2r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080ce, (_val))
#define MODIFY_XGXS16G_RX1_RX_ANALOGBIAS2r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080ce, (_val), (_mask))


/****************************************************************************
 * XGXS16G_USER_RX2
 ***************************************************************************/

/* Rx lane status register */
#define READ_XGXS16G_RX2_RX_STATUSr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080d0, (_val))
#define WRITE_XGXS16G_RX2_RX_STATUSr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080d0, (_val))
#define MODIFY_XGXS16G_RX2_RX_STATUSr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080d0, (_val), (_mask))

/* Rx lane control register */
#define READ_XGXS16G_RX2_RX_CONTROLr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080d1, (_val))
#define WRITE_XGXS16G_RX2_RX_CONTROLr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080d1, (_val))
#define MODIFY_XGXS16G_RX2_RX_CONTROLr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080d1, (_val), (_mask))

/* Rx lane control register */
#define READ_XGXS16G_RX2_RX_TESTr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080d8, (_val))
#define WRITE_XGXS16G_RX2_RX_TESTr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080d8, (_val))
#define MODIFY_XGXS16G_RX2_RX_TESTr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080d8, (_val), (_mask))

/* Rx 1G Control register */
#define READ_XGXS16G_RX2_RX_CONTROL_1G_TYPEr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080d9, (_val))
#define WRITE_XGXS16G_RX2_RX_CONTROL_1G_TYPEr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080d9, (_val))
#define MODIFY_XGXS16G_RX2_RX_CONTROL_1G_TYPEr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080d9, (_val), (_mask))

/* Rx analog status register */
#define READ_XGXS16G_RX2_RX_ASTATUSr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080db, (_val))
#define WRITE_XGXS16G_RX2_RX_ASTATUSr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080db, (_val))
#define MODIFY_XGXS16G_RX2_RX_ASTATUSr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080db, (_val), (_mask))

/* Rx reserved analog control register */
#define READ_XGXS16G_RX2_RX_ANALOGBIAS0r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080dc, (_val))
#define WRITE_XGXS16G_RX2_RX_ANALOGBIAS0r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080dc, (_val))
#define MODIFY_XGXS16G_RX2_RX_ANALOGBIAS0r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080dc, (_val), (_mask))

/* Rx reserved analog control register */
#define READ_XGXS16G_RX2_RX_ANALOGBIAS1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080dd, (_val))
#define WRITE_XGXS16G_RX2_RX_ANALOGBIAS1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080dd, (_val))
#define MODIFY_XGXS16G_RX2_RX_ANALOGBIAS1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080dd, (_val), (_mask))

/* Rx reserved analog control register */
#define READ_XGXS16G_RX2_RX_ANALOGBIAS2r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080de, (_val))
#define WRITE_XGXS16G_RX2_RX_ANALOGBIAS2r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080de, (_val))
#define MODIFY_XGXS16G_RX2_RX_ANALOGBIAS2r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080de, (_val), (_mask))


/****************************************************************************
 * XGXS16G_USER_RX3
 ***************************************************************************/

/* Rx lane status register */
#define READ_XGXS16G_RX3_RX_STATUSr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080e0, (_val))
#define WRITE_XGXS16G_RX3_RX_STATUSr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080e0, (_val))
#define MODIFY_XGXS16G_RX3_RX_STATUSr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080e0, (_val), (_mask))

/* Rx lane control register */
#define READ_XGXS16G_RX3_RX_CONTROLr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080e1, (_val))
#define WRITE_XGXS16G_RX3_RX_CONTROLr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080e1, (_val))
#define MODIFY_XGXS16G_RX3_RX_CONTROLr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080e1, (_val), (_mask))

/* Rx lane control register */
#define READ_XGXS16G_RX3_RX_TESTr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080e8, (_val))
#define WRITE_XGXS16G_RX3_RX_TESTr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080e8, (_val))
#define MODIFY_XGXS16G_RX3_RX_TESTr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080e8, (_val), (_mask))

/* Rx 1G Control register */
#define READ_XGXS16G_RX3_RX_CONTROL_1G_TYPEr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080e9, (_val))
#define WRITE_XGXS16G_RX3_RX_CONTROL_1G_TYPEr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080e9, (_val))
#define MODIFY_XGXS16G_RX3_RX_CONTROL_1G_TYPEr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080e9, (_val), (_mask))

/* Rx analog status register */
#define READ_XGXS16G_RX3_RX_ASTATUSr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080eb, (_val))
#define WRITE_XGXS16G_RX3_RX_ASTATUSr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080eb, (_val))
#define MODIFY_XGXS16G_RX3_RX_ASTATUSr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080eb, (_val), (_mask))

/* Rx reserved analog control register */
#define READ_XGXS16G_RX3_RX_ANALOGBIAS0r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080ec, (_val))
#define WRITE_XGXS16G_RX3_RX_ANALOGBIAS0r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080ec, (_val))
#define MODIFY_XGXS16G_RX3_RX_ANALOGBIAS0r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080ec, (_val), (_mask))

/* Rx reserved analog control register */
#define READ_XGXS16G_RX3_RX_ANALOGBIAS1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080ed, (_val))
#define WRITE_XGXS16G_RX3_RX_ANALOGBIAS1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080ed, (_val))
#define MODIFY_XGXS16G_RX3_RX_ANALOGBIAS1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080ed, (_val), (_mask))

/* Rx reserved analog control register */
#define READ_XGXS16G_RX3_RX_ANALOGBIAS2r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080ee, (_val))
#define WRITE_XGXS16G_RX3_RX_ANALOGBIAS2r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080ee, (_val))
#define MODIFY_XGXS16G_RX3_RX_ANALOGBIAS2r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080ee, (_val), (_mask))


/****************************************************************************
 * XGXS16G_USER_RX_All
 ***************************************************************************/

/* Rx lane status register */
#define READ_XGXS16G_RX_ALL_RX_STATUSr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080f0, (_val))
#define WRITE_XGXS16G_RX_ALL_RX_STATUSr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080f0, (_val))
#define MODIFY_XGXS16G_RX_ALL_RX_STATUSr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080f0, (_val), (_mask))

/* Rx lane control register */
#define READ_XGXS16G_RX_ALL_RX_CONTROLr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080f1, (_val))
#define WRITE_XGXS16G_RX_ALL_RX_CONTROLr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080f1, (_val))
#define MODIFY_XGXS16G_RX_ALL_RX_CONTROLr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080f1, (_val), (_mask))

/* Rx lane control register */
#define READ_XGXS16G_RX_ALL_RX_TESTr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080f8, (_val))
#define WRITE_XGXS16G_RX_ALL_RX_TESTr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080f8, (_val))
#define MODIFY_XGXS16G_RX_ALL_RX_TESTr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080f8, (_val), (_mask))

/* Rx 1G Control register */
#define READ_XGXS16G_RX_ALL_RX_CONTROL_1G_TYPEr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080f9, (_val))
#define WRITE_XGXS16G_RX_ALL_RX_CONTROL_1G_TYPEr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080f9, (_val))
#define MODIFY_XGXS16G_RX_ALL_RX_CONTROL_1G_TYPEr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080f9, (_val), (_mask))

/* Rx analog status register */
#define READ_XGXS16G_RX_ALL_RX_ASTATUSr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080fb, (_val))
#define WRITE_XGXS16G_RX_ALL_RX_ASTATUSr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080fb, (_val))
#define MODIFY_XGXS16G_RX_ALL_RX_ASTATUSr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080fb, (_val), (_mask))

/* Rx reserved analog control register */
#define READ_XGXS16G_RX_ALL_RX_ANALOGBIAS0r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080fc, (_val))
#define WRITE_XGXS16G_RX_ALL_RX_ANALOGBIAS0r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080fc, (_val))
#define MODIFY_XGXS16G_RX_ALL_RX_ANALOGBIAS0r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080fc, (_val), (_mask))

/* Rx reserved analog control register */
#define READ_XGXS16G_RX_ALL_RX_ANALOGBIAS1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080fd, (_val))
#define WRITE_XGXS16G_RX_ALL_RX_ANALOGBIAS1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080fd, (_val))
#define MODIFY_XGXS16G_RX_ALL_RX_ANALOGBIAS1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080fd, (_val), (_mask))

/* Rx reserved analog control register */
#define READ_XGXS16G_RX_ALL_RX_ANALOGBIAS2r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080fe, (_val))
#define WRITE_XGXS16G_RX_ALL_RX_ANALOGBIAS2r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080fe, (_val))
#define MODIFY_XGXS16G_RX_ALL_RX_ANALOGBIAS2r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080fe, (_val), (_mask))


/****************************************************************************
 * XGXS16G_USER_XgxsBlk2
 ***************************************************************************/

/* Receiver lane swap control register */
#define READ_XGXS16G_XGXSBLK2_RXLNSWAPr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008100, (_val))
#define WRITE_XGXS16G_XGXSBLK2_RXLNSWAPr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008100, (_val))
#define MODIFY_XGXS16G_XGXSBLK2_RXLNSWAPr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008100, (_val), (_mask))

/* Transmit lane swap control register */
#define READ_XGXS16G_XGXSBLK2_TXLNSWAPr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008101, (_val))
#define WRITE_XGXS16G_XGXSBLK2_TXLNSWAPr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008101, (_val))
#define MODIFY_XGXS16G_XGXSBLK2_TXLNSWAPr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008101, (_val), (_mask))

/* ||Q|| ordered set, lanes 0 & 1 register */
#define READ_XGXS16G_XGXSBLK2_QSETLNS01r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008102, (_val))
#define WRITE_XGXS16G_XGXSBLK2_QSETLNS01r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008102, (_val))
#define MODIFY_XGXS16G_XGXSBLK2_QSETLNS01r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008102, (_val), (_mask))

/* ||Q|| ordered set, lanes 2 & 3 register */
#define READ_XGXS16G_XGXSBLK2_QSETLNS23r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008103, (_val))
#define WRITE_XGXS16G_XGXSBLK2_QSETLNS23r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008103, (_val))
#define MODIFY_XGXS16G_XGXSBLK2_QSETLNS23r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008103, (_val), (_mask))

/* AN 10G resolution mode control register */
#define READ_XGXS16G_XGXSBLK2_UNICOREMODE10Gr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008104, (_val))
#define WRITE_XGXS16G_XGXSBLK2_UNICOREMODE10Gr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008104, (_val))
#define MODIFY_XGXS16G_XGXSBLK2_UNICOREMODE10Gr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008104, (_val), (_mask))

/* indCombCtrl  register */
#define READ_XGXS16G_XGXSBLK2_INDCOMBCTRLr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008105, (_val))
#define WRITE_XGXS16G_XGXSBLK2_INDCOMBCTRLr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008105, (_val))
#define MODIFY_XGXS16G_XGXSBLK2_INDCOMBCTRLr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008105, (_val), (_mask))

/* Test mode lane select register */
#define READ_XGXS16G_XGXSBLK2_TESTMODELANEr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008106, (_val))
#define WRITE_XGXS16G_XGXSBLK2_TESTMODELANEr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008106, (_val))
#define MODIFY_XGXS16G_XGXSBLK2_TESTMODELANEr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008106, (_val), (_mask))

/* Test mode monitor control register */
#define READ_XGXS16G_XGXSBLK2_TESTMODECOMBOr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008107, (_val))
#define WRITE_XGXS16G_XGXSBLK2_TESTMODECOMBOr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008107, (_val))
#define MODIFY_XGXS16G_XGXSBLK2_TESTMODECOMBOr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008107, (_val), (_mask))

/* Test mode mux control register */
#define READ_XGXS16G_XGXSBLK2_TESTMODEMUXr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008108, (_val))
#define WRITE_XGXS16G_XGXSBLK2_TESTMODEMUXr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008108, (_val))
#define MODIFY_XGXS16G_XGXSBLK2_TESTMODEMUXr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008108, (_val), (_mask))

/* 10GBASE-CX4 signal detect timeout value */
#define READ_XGXS16G_XGXSBLK2_CX4SIGDETCNTr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008109, (_val))
#define WRITE_XGXS16G_XGXSBLK2_CX4SIGDETCNTr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008109, (_val))
#define MODIFY_XGXS16G_XGXSBLK2_CX4SIGDETCNTr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008109, (_val), (_mask))


/****************************************************************************
 * XGXS16G_IN_BAND_MDIO
 ***************************************************************************/

/****************************************************************************
 * XGXS16G_USER_GP_Status
 ***************************************************************************/

/* Miscelaneous Rx status register */
#define READ_XGXS16G_GP_STATUS_MISCRXSTATUSr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008120, (_val))
#define WRITE_XGXS16G_GP_STATUS_MISCRXSTATUSr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008120, (_val))
#define MODIFY_XGXS16G_GP_STATUS_MISCRXSTATUSr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008120, (_val), (_mask))

/* XGXG status register */
#define READ_XGXS16G_GP_STATUS_XGXSSTATUS0r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008121, (_val))
#define WRITE_XGXS16G_GP_STATUS_XGXSSTATUS0r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008121, (_val))
#define MODIFY_XGXS16G_GP_STATUS_XGXSSTATUS0r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008121, (_val), (_mask))

/* XGXG status 1 register */
#define READ_XGXS16G_GP_STATUS_XGXSSTATUS1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008122, (_val))
#define WRITE_XGXS16G_GP_STATUS_XGXSSTATUS1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008122, (_val))
#define MODIFY_XGXS16G_GP_STATUS_XGXSSTATUS1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008122, (_val), (_mask))

/* XGXG status 2 register */
#define READ_XGXS16G_GP_STATUS_XGXSSTATUS2r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008123, (_val))
#define WRITE_XGXS16G_GP_STATUS_XGXSSTATUS2r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008123, (_val))
#define MODIFY_XGXS16G_GP_STATUS_XGXSSTATUS2r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008123, (_val), (_mask))

/* 1000X status 1 register */
#define READ_XGXS16G_GP_STATUS_STATUS1000X1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008124, (_val))
#define WRITE_XGXS16G_GP_STATUS_STATUS1000X1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008124, (_val))
#define MODIFY_XGXS16G_GP_STATUS_STATUS1000X1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008124, (_val), (_mask))

/* 1000X status 2 register */
#define READ_XGXS16G_GP_STATUS_STATUS1000X2r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008125, (_val))
#define WRITE_XGXS16G_GP_STATUS_STATUS1000X2r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008125, (_val))
#define MODIFY_XGXS16G_GP_STATUS_STATUS1000X2r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008125, (_val), (_mask))

/* 1000X status 3 register */
#define READ_XGXS16G_GP_STATUS_STATUS1000X3r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008126, (_val))
#define WRITE_XGXS16G_GP_STATUS_STATUS1000X3r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008126, (_val))
#define MODIFY_XGXS16G_GP_STATUS_STATUS1000X3r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008126, (_val), (_mask))

/* Test port out bits 15:0, tpout[15:0] */
#define READ_XGXS16G_GP_STATUS_TPOUT_1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008127, (_val))
#define WRITE_XGXS16G_GP_STATUS_TPOUT_1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008127, (_val))
#define MODIFY_XGXS16G_GP_STATUS_TPOUT_1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008127, (_val), (_mask))

/* Test port out bits 23:8, tpout[23:8] */
#define READ_XGXS16G_GP_STATUS_TPOUT_2r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008128, (_val))
#define WRITE_XGXS16G_GP_STATUS_TPOUT_2r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008128, (_val))
#define MODIFY_XGXS16G_GP_STATUS_TPOUT_2r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008128, (_val), (_mask))

/* XGXG status 3 register */
#define READ_XGXS16G_GP_STATUS_XGXSSTATUS3r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008129, (_val))
#define WRITE_XGXS16G_GP_STATUS_XGXSSTATUS3r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008129, (_val))
#define MODIFY_XGXS16G_GP_STATUS_XGXSSTATUS3r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008129, (_val), (_mask))

/* 2500X status register */
#define READ_XGXS16G_GP_STATUS_X2500STATUS1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000812a, (_val))
#define WRITE_XGXS16G_GP_STATUS_X2500STATUS1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000812a, (_val))
#define MODIFY_XGXS16G_GP_STATUS_X2500STATUS1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000812a, (_val), (_mask))

/* CL73 AN status 1 register */
#define READ_XGXS16G_GP_STATUS_TOPANSTATUS1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000812b, (_val))
#define WRITE_XGXS16G_GP_STATUS_TOPANSTATUS1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000812b, (_val))
#define MODIFY_XGXS16G_GP_STATUS_TOPANSTATUS1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000812b, (_val), (_mask))

/* AN link partner user page 1 */
#define READ_XGXS16G_GP_STATUS_LP_UP1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000812c, (_val))
#define WRITE_XGXS16G_GP_STATUS_LP_UP1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000812c, (_val))
#define MODIFY_XGXS16G_GP_STATUS_LP_UP1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000812c, (_val), (_mask))

/* AN link partner user page 2 */
#define READ_XGXS16G_GP_STATUS_LP_UP2r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000812d, (_val))
#define WRITE_XGXS16G_GP_STATUS_LP_UP2r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000812d, (_val))
#define MODIFY_XGXS16G_GP_STATUS_LP_UP2r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000812d, (_val), (_mask))

/* AN link partner user page 3 */
#define READ_XGXS16G_GP_STATUS_LP_UP3r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000812e, (_val))
#define WRITE_XGXS16G_GP_STATUS_LP_UP3r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000812e, (_val))
#define MODIFY_XGXS16G_GP_STATUS_LP_UP3r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000812e, (_val), (_mask))


/****************************************************************************
 * XGXS16G_USER_AN73_pdet
 ***************************************************************************/

/* 10G parallel detect status register */
#define READ_XGXS16G_AN73_PDET_PARDET10GSTATUSr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008130, (_val))
#define WRITE_XGXS16G_AN73_PDET_PARDET10GSTATUSr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008130, (_val))
#define MODIFY_XGXS16G_AN73_PDET_PARDET10GSTATUSr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008130, (_val), (_mask))

/* 10G parallel detect control register */
#define READ_XGXS16G_AN73_PDET_PARDET10GCONTROLr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008131, (_val))
#define WRITE_XGXS16G_AN73_PDET_PARDET10GCONTROLr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008131, (_val))
#define MODIFY_XGXS16G_AN73_PDET_PARDET10GCONTROLr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008131, (_val), (_mask))

/* 10G parallel detect signal detect register */
#define READ_XGXS16G_AN73_PDET_PARDET10GSIGDETr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008132, (_val))
#define WRITE_XGXS16G_AN73_PDET_PARDET10GSIGDETr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008132, (_val))
#define MODIFY_XGXS16G_AN73_PDET_PARDET10GSIGDETr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008132, (_val), (_mask))

/* 10G parallel detect link register */
#define READ_XGXS16G_AN73_PDET_PARDET10GLINKr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008133, (_val))
#define WRITE_XGXS16G_AN73_PDET_PARDET10GLINKr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008133, (_val))
#define MODIFY_XGXS16G_AN73_PDET_PARDET10GLINKr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008133, (_val), (_mask))

/* 10G parallel detect lost link register */
#define READ_XGXS16G_AN73_PDET_PARDET10GLOSTLINKr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008134, (_val))
#define WRITE_XGXS16G_AN73_PDET_PARDET10GLOSTLINKr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008134, (_val))
#define MODIFY_XGXS16G_AN73_PDET_PARDET10GLOSTLINKr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008134, (_val), (_mask))

/* Clasue 73 auto-negotiation control register 1 */
#define READ_XGXS16G_AN73_PDET_CL73CONTROL1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008135, (_val))
#define WRITE_XGXS16G_AN73_PDET_CL73CONTROL1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008135, (_val))
#define MODIFY_XGXS16G_AN73_PDET_CL73CONTROL1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008135, (_val), (_mask))

/* Clasue 73 auto-negotiation control register 2 */
#define READ_XGXS16G_AN73_PDET_CL73CONTROL2r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008136, (_val))
#define WRITE_XGXS16G_AN73_PDET_CL73CONTROL2r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008136, (_val))
#define MODIFY_XGXS16G_AN73_PDET_CL73CONTROL2r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008136, (_val), (_mask))

/* Clasue 73 auto-negotiation control register 3 */
#define READ_XGXS16G_AN73_PDET_CL73CONTROL3r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008137, (_val))
#define WRITE_XGXS16G_AN73_PDET_CL73CONTROL3r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008137, (_val))
#define MODIFY_XGXS16G_AN73_PDET_CL73CONTROL3r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008137, (_val), (_mask))

/* Clasue 73 auto-negotiation control register 4 */
#define READ_XGXS16G_AN73_PDET_CL73CONTROL4r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008138, (_val))
#define WRITE_XGXS16G_AN73_PDET_CL73CONTROL4r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008138, (_val))
#define MODIFY_XGXS16G_AN73_PDET_CL73CONTROL4r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008138, (_val), (_mask))


/* TX Lane Swap Control 1 Register */
#define READ_XGXS16G_XGXSBLK8_TXLNSWAP1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008169, (_val))
#define WRITE_XGXS16G_XGXSBLK8_TXLNSWAP1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008169, (_val))
#define MODIFY_XGXS16G_XGXSBLK8_TXLNSWAP1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008169, (_val), (_mask))

/* RX Lane Swap Control 1 Register */
#define READ_XGXS16G_XGXSBLK8_RXLNSWAP1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000816b, (_val))
#define WRITE_XGXS16G_XGXSBLK8_RXLNSWAP1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000816b, (_val))
#define MODIFY_XGXS16G_XGXSBLK8_RXLNSWAP1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000816b, (_val), (_mask))

/****************************************************************************
 * XGXS16G_USER_XgxsBlk7
 ***************************************************************************/

/* Cl48 PCS EEE Control register */
#define READ_XGXS16G_XGXSBLK7_EEECONTROLr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008150, (_val))
#define WRITE_XGXS16G_XGXSBLK7_EEECONTROLr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008150, (_val))
#define MODIFY_XGXS16G_XGXSBLK7_EEECONTROLr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008150, (_val), (_mask))

/****************************************************************************
 * XGXS16G_USER_SerdesDigital
 ***************************************************************************/

/* 1000X control 1 register */
#define READ_XGXS16G_SERDESDIGITAL_CONTROL1000X1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008300, (_val))
#define WRITE_XGXS16G_SERDESDIGITAL_CONTROL1000X1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008300, (_val))
#define MODIFY_XGXS16G_SERDESDIGITAL_CONTROL1000X1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008300, (_val), (_mask))

/* 1000X control 2 register */
#define READ_XGXS16G_SERDESDIGITAL_CONTROL1000X2r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008301, (_val))
#define WRITE_XGXS16G_SERDESDIGITAL_CONTROL1000X2r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008301, (_val))
#define MODIFY_XGXS16G_SERDESDIGITAL_CONTROL1000X2r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008301, (_val), (_mask))

/* 1000X control 3 register */
#define READ_XGXS16G_SERDESDIGITAL_CONTROL1000X3r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008302, (_val))
#define WRITE_XGXS16G_SERDESDIGITAL_CONTROL1000X3r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008302, (_val))
#define MODIFY_XGXS16G_SERDESDIGITAL_CONTROL1000X3r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008302, (_val), (_mask))

/* 1000X control 4 register */
#define READ_XGXS16G_SERDESDIGITAL_CONTROL1000X4r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008303, (_val))
#define WRITE_XGXS16G_SERDESDIGITAL_CONTROL1000X4r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008303, (_val))
#define MODIFY_XGXS16G_SERDESDIGITAL_CONTROL1000X4r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008303, (_val), (_mask))

/* 1000X status 1 register */
#define READ_XGXS16G_SERDESDIGITAL_STATUS1000X1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008304, (_val))
#define WRITE_XGXS16G_SERDESDIGITAL_STATUS1000X1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008304, (_val))
#define MODIFY_XGXS16G_SERDESDIGITAL_STATUS1000X1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008304, (_val), (_mask))

/* 1000X status 2 register */
#define READ_XGXS16G_SERDESDIGITAL_STATUS1000X2r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008305, (_val))
#define WRITE_XGXS16G_SERDESDIGITAL_STATUS1000X2r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008305, (_val))
#define MODIFY_XGXS16G_SERDESDIGITAL_STATUS1000X2r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008305, (_val), (_mask))

/* 1000X status 3 register */
#define READ_XGXS16G_SERDESDIGITAL_STATUS1000X3r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008306, (_val))
#define WRITE_XGXS16G_SERDESDIGITAL_STATUS1000X3r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008306, (_val))
#define MODIFY_XGXS16G_SERDESDIGITAL_STATUS1000X3r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008306, (_val), (_mask))

/* CRC error & Rx byte count register */
#define READ_XGXS16G_SERDESDIGITAL_CRCERR_RXPKTr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008307, (_val))
#define WRITE_XGXS16G_SERDESDIGITAL_CRCERR_RXPKTr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008307, (_val))
#define MODIFY_XGXS16G_SERDESDIGITAL_CRCERR_RXPKTr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008307, (_val), (_mask))

/* Miscellaneous 1 control register */
#define READ_XGXS16G_SERDESDIGITAL_MISC1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008308, (_val))
#define WRITE_XGXS16G_SERDESDIGITAL_MISC1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008308, (_val))
#define MODIFY_XGXS16G_SERDESDIGITAL_MISC1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008308, (_val), (_mask))

/* Miscellaneous 2 control register */
#define READ_XGXS16G_SERDESDIGITAL_MISC2r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008309, (_val))
#define WRITE_XGXS16G_SERDESDIGITAL_MISC2r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008309, (_val))
#define MODIFY_XGXS16G_SERDESDIGITAL_MISC2r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008309, (_val), (_mask))

/* Pattern generator control register */
#define READ_XGXS16G_SERDESDIGITAL_PATGENCTRLr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000830a, (_val))
#define WRITE_XGXS16G_SERDESDIGITAL_PATGENCTRLr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000830a, (_val))
#define MODIFY_XGXS16G_SERDESDIGITAL_PATGENCTRLr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000830a, (_val), (_mask))

/* Pattern generator status register */
#define READ_XGXS16G_SERDESDIGITAL_PATGENSTATr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000830b, (_val))
#define WRITE_XGXS16G_SERDESDIGITAL_PATGENSTATr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000830b, (_val))
#define MODIFY_XGXS16G_SERDESDIGITAL_PATGENSTATr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000830b, (_val), (_mask))

/* Test mode register */
#define READ_XGXS16G_SERDESDIGITAL_TESTMODEr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000830c, (_val))
#define WRITE_XGXS16G_SERDESDIGITAL_TESTMODEr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000830c, (_val))
#define MODIFY_XGXS16G_SERDESDIGITAL_TESTMODEr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000830c, (_val), (_mask))

/* Tx packet count register */
#define READ_XGXS16G_SERDESDIGITAL_TXPKTCNTr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000830d, (_val))
#define WRITE_XGXS16G_SERDESDIGITAL_TXPKTCNTr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000830d, (_val))
#define MODIFY_XGXS16G_SERDESDIGITAL_TXPKTCNTr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000830d, (_val), (_mask))

/* Rx packet count register */
#define READ_XGXS16G_SERDESDIGITAL_RXPKTCNTr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000830e, (_val))
#define WRITE_XGXS16G_SERDESDIGITAL_RXPKTCNTr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000830e, (_val))
#define MODIFY_XGXS16G_SERDESDIGITAL_RXPKTCNTr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000830e, (_val), (_mask))


/****************************************************************************
 * XGXS16G_USER_serdesID
 ***************************************************************************/

/* Serdes ID 0 register */
#define READ_XGXS16G_SERDESID_SERDESID0r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008310, (_val))
#define WRITE_XGXS16G_SERDESID_SERDESID0r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008310, (_val))
#define MODIFY_XGXS16G_SERDESID_SERDESID0r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008310, (_val), (_mask))

/* Serdes ID 1 register */
#define READ_XGXS16G_SERDESID_SERDESID1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008311, (_val))
#define WRITE_XGXS16G_SERDESID_SERDESID1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008311, (_val))
#define MODIFY_XGXS16G_SERDESID_SERDESID1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008311, (_val), (_mask))

/* Serdes ID 2 register */
#define READ_XGXS16G_SERDESID_SERDESID2r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008312, (_val))
#define WRITE_XGXS16G_SERDESID_SERDESID2r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008312, (_val))
#define MODIFY_XGXS16G_SERDESID_SERDESID2r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008312, (_val), (_mask))

/* Serdes ID 3 register */
#define READ_XGXS16G_SERDESID_SERDESID3r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008313, (_val))
#define WRITE_XGXS16G_SERDESID_SERDESID3r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008313, (_val))
#define MODIFY_XGXS16G_SERDESID_SERDESID3r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008313, (_val), (_mask))


/****************************************************************************
 * XGXS16G_USER_Over1G
 ***************************************************************************/

/* AN lost link count time, bits 15:0 */
#define READ_XGXS16G_OVER1G_DIGCTL_3_0r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008320, (_val))
#define WRITE_XGXS16G_OVER1G_DIGCTL_3_0r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008320, (_val))
#define MODIFY_XGXS16G_OVER1G_DIGCTL_3_0r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008320, (_val), (_mask))

/* AN switch count time, bits 15:0 */
#define READ_XGXS16G_OVER1G_DIGCTL_3_1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008321, (_val))
#define WRITE_XGXS16G_OVER1G_DIGCTL_3_1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008321, (_val))
#define MODIFY_XGXS16G_OVER1G_DIGCTL_3_1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008321, (_val), (_mask))

/* AN link count time, bits 15:0 */
#define READ_XGXS16G_OVER1G_DIGCTL_3_2r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008322, (_val))
#define WRITE_XGXS16G_OVER1G_DIGCTL_3_2r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008322, (_val))
#define MODIFY_XGXS16G_OVER1G_DIGCTL_3_2r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008322, (_val), (_mask))

/* AN switch count & link count time, bits 23:16 */
#define READ_XGXS16G_OVER1G_DIGCTL_3_3r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008323, (_val))
#define WRITE_XGXS16G_OVER1G_DIGCTL_3_3r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008323, (_val))
#define MODIFY_XGXS16G_OVER1G_DIGCTL_3_3r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008323, (_val), (_mask))

/* Over 1G message page number & AN fail count timer */
#define READ_XGXS16G_OVER1G_DIGCTL_3_4r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008324, (_val))
#define WRITE_XGXS16G_OVER1G_DIGCTL_3_4r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008324, (_val))
#define MODIFY_XGXS16G_OVER1G_DIGCTL_3_4r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008324, (_val), (_mask))

/* AN ignore link count time, bits 15:0 */
#define READ_XGXS16G_OVER1G_DIGCTL_3_5r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008325, (_val))
#define WRITE_XGXS16G_OVER1G_DIGCTL_3_5r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008325, (_val))
#define MODIFY_XGXS16G_OVER1G_DIGCTL_3_5r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008325, (_val), (_mask))

/* AN lost link count & ignore link count time, bits 23:16 */
#define READ_XGXS16G_OVER1G_DIGCTL_3_6r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008326, (_val))
#define WRITE_XGXS16G_OVER1G_DIGCTL_3_6r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008326, (_val))
#define MODIFY_XGXS16G_OVER1G_DIGCTL_3_6r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008326, (_val), (_mask))

/* Test port out bits 15:0, tpout[15:0] */
#define READ_XGXS16G_OVER1G_TPOUT_1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008327, (_val))
#define WRITE_XGXS16G_OVER1G_TPOUT_1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008327, (_val))
#define MODIFY_XGXS16G_OVER1G_TPOUT_1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008327, (_val), (_mask))

/* Test port out bits 23:8, tpout[23:8] */
#define READ_XGXS16G_OVER1G_TPOUT_2r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008328, (_val))
#define WRITE_XGXS16G_OVER1G_TPOUT_2r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008328, (_val))
#define MODIFY_XGXS16G_OVER1G_TPOUT_2r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008328, (_val), (_mask))

/* AN local device user page 1 */
#define READ_XGXS16G_OVER1G_UP1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008329, (_val))
#define WRITE_XGXS16G_OVER1G_UP1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008329, (_val))
#define MODIFY_XGXS16G_OVER1G_UP1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008329, (_val), (_mask))

/* AN local device user page 2 */
#define READ_XGXS16G_OVER1G_UP2r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000832a, (_val))
#define WRITE_XGXS16G_OVER1G_UP2r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000832a, (_val))
#define MODIFY_XGXS16G_OVER1G_UP2r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000832a, (_val), (_mask))

/* AN local device user page 3 */
#define READ_XGXS16G_OVER1G_UP3r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000832b, (_val))
#define WRITE_XGXS16G_OVER1G_UP3r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000832b, (_val))
#define MODIFY_XGXS16G_OVER1G_UP3r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000832b, (_val), (_mask))

/* AN link partner user page 1 */
#define READ_XGXS16G_OVER1G_LP_UP1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000832c, (_val))
#define WRITE_XGXS16G_OVER1G_LP_UP1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000832c, (_val))
#define MODIFY_XGXS16G_OVER1G_LP_UP1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000832c, (_val), (_mask))

/* AN link partner user page 2 */
#define READ_XGXS16G_OVER1G_LP_UP2r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000832d, (_val))
#define WRITE_XGXS16G_OVER1G_LP_UP2r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000832d, (_val))
#define MODIFY_XGXS16G_OVER1G_LP_UP2r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000832d, (_val), (_mask))

/* AN link partner user page 3 */
#define READ_XGXS16G_OVER1G_LP_UP3r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000832e, (_val))
#define WRITE_XGXS16G_OVER1G_LP_UP3r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000832e, (_val))

#define MODIFY_XGXS16G_OVER1G_LP_UP3r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000832e, (_val), (_mask))


/****************************************************************************
 * XGXS16G_USER_RemotePhy
 ***************************************************************************/

/* Miscelaneous Rx status register */
#define READ_XGXS16G_REMOTEPHY_MISCRXSTATUSr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008330, (_val))
#define WRITE_XGXS16G_REMOTEPHY_MISCRXSTATUSr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008330, (_val))
#define MODIFY_XGXS16G_REMOTEPHY_MISCRXSTATUSr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008330, (_val), (_mask))


/* Link partner basepage register */
#define READ_XGXS16G_REMOTEPHY_LP_BASEPAGEr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008331, (_val))
#define WRITE_XGXS16G_REMOTEPHY_LP_BASEPAGEr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008331, (_val))
#define MODIFY_XGXS16G_REMOTEPHY_LP_BASEPAGEr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008331, (_val), (_mask))

/* Link partner nextpage 0 register */
#define READ_XGXS16G_REMOTEPHY_LP_NEXTPAGE_0r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008332, (_val))
#define WRITE_XGXS16G_REMOTEPHY_LP_NEXTPAGE_0r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008332, (_val))
#define MODIFY_XGXS16G_REMOTEPHY_LP_NEXTPAGE_0r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008332, (_val), (_mask))

/* Link partner nextpage 1 register */
#define READ_XGXS16G_REMOTEPHY_LP_NEXTPAGE_1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008333, (_val))
#define WRITE_XGXS16G_REMOTEPHY_LP_NEXTPAGE_1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008333, (_val))
#define MODIFY_XGXS16G_REMOTEPHY_LP_NEXTPAGE_1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008333, (_val), (_mask))

/* Link partner nextpage 2 register */
#define READ_XGXS16G_REMOTEPHY_LP_NEXTPAGE_2r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008334, (_val))
#define WRITE_XGXS16G_REMOTEPHY_LP_NEXTPAGE_2r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008334, (_val))
#define MODIFY_XGXS16G_REMOTEPHY_LP_NEXTPAGE_2r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008334, (_val), (_mask))

/* Link partner nextpage 3 register */
#define READ_XGXS16G_REMOTEPHY_LP_NEXTPAGE_3r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008335, (_val))
#define WRITE_XGXS16G_REMOTEPHY_LP_NEXTPAGE_3r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008335, (_val))
#define MODIFY_XGXS16G_REMOTEPHY_LP_NEXTPAGE_3r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008335, (_val), (_mask))

/* Link partner nextpage 4 register */
#define READ_XGXS16G_REMOTEPHY_LP_NEXTPAGE_4r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008336, (_val))
#define WRITE_XGXS16G_REMOTEPHY_LP_NEXTPAGE_4r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008336, (_val))
#define MODIFY_XGXS16G_REMOTEPHY_LP_NEXTPAGE_4r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008336, (_val), (_mask))

/* Remote phy nextpage 0 register */
#define READ_XGXS16G_REMOTEPHY_RP_NEXTPAGE_0r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008337, (_val))
#define WRITE_XGXS16G_REMOTEPHY_RP_NEXTPAGE_0r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008337, (_val))
#define MODIFY_XGXS16G_REMOTEPHY_RP_NEXTPAGE_0r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008337, (_val), (_mask))

/* Remote phy nextpage 1 register */
#define READ_XGXS16G_REMOTEPHY_RP_NEXTPAGE_1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008338, (_val))
#define WRITE_XGXS16G_REMOTEPHY_RP_NEXTPAGE_1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008338, (_val))
#define MODIFY_XGXS16G_REMOTEPHY_RP_NEXTPAGE_1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008338, (_val), (_mask))

/* Remote phy nextpage 2 register */
#define READ_XGXS16G_REMOTEPHY_RP_NEXTPAGE_2r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008339, (_val))
#define WRITE_XGXS16G_REMOTEPHY_RP_NEXTPAGE_2r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008339, (_val))
#define MODIFY_XGXS16G_REMOTEPHY_RP_NEXTPAGE_2r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008339, (_val), (_mask))

/* Remote phy nextpage 3 register */
#define READ_XGXS16G_REMOTEPHY_RP_NEXTPAGE_3r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000833a, (_val))
#define WRITE_XGXS16G_REMOTEPHY_RP_NEXTPAGE_3r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000833a, (_val))
#define MODIFY_XGXS16G_REMOTEPHY_RP_NEXTPAGE_3r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000833a, (_val), (_mask))

/* Remote phy nextpage 4 register */
#define READ_XGXS16G_REMOTEPHY_RP_NEXTPAGE_4r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000833b, (_val))
#define WRITE_XGXS16G_REMOTEPHY_RP_NEXTPAGE_4r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000833b, (_val))
#define MODIFY_XGXS16G_REMOTEPHY_RP_NEXTPAGE_4r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000833b, (_val), (_mask))

/* Miscelaneous 3 control register */
#define READ_XGXS16G_REMOTEPHY_MISC3r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000833c, (_val))
#define WRITE_XGXS16G_REMOTEPHY_MISC3r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000833c, (_val))
#define MODIFY_XGXS16G_REMOTEPHY_MISC3r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000833c, (_val), (_mask))

/* Miscelaneous 5 control register */
#define READ_XGXS16G_REMOTEPHY_MISC5r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000833e, (_val))
#define WRITE_XGXS16G_REMOTEPHY_MISC5r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000833e, (_val))
#define MODIFY_XGXS16G_REMOTEPHY_MISC5r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000833e, (_val), (_mask))


/****************************************************************************
 * XGXS16G_USER_BAM_NextPage
 ***************************************************************************/

/* MP5, Message Page 5, next page control register */
#define READ_XGXS16G_BAM_NEXTPAGE_MP5_NEXTPAGECTRLr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008350, (_val))
#define WRITE_XGXS16G_BAM_NEXTPAGE_MP5_NEXTPAGECTRLr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008350, (_val))
#define MODIFY_XGXS16G_BAM_NEXTPAGE_MP5_NEXTPAGECTRLr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008350, (_val), (_mask))

/* sgmii & max timer offsets */
#define READ_XGXS16G_BAM_NEXTPAGE_LINK_TIMER_OFFSET1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008351, (_val))
#define WRITE_XGXS16G_BAM_NEXTPAGE_LINK_TIMER_OFFSET1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008351, (_val))
#define MODIFY_XGXS16G_BAM_NEXTPAGE_LINK_TIMER_OFFSET1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008351, (_val), (_mask))

/* link up & link down timer offsets */
#define READ_XGXS16G_BAM_NEXTPAGE_LINK_TIMER_OFFSET2r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008352, (_val))
#define WRITE_XGXS16G_BAM_NEXTPAGE_LINK_TIMER_OFFSET2r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008352, (_val))
#define MODIFY_XGXS16G_BAM_NEXTPAGE_LINK_TIMER_OFFSET2r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008352, (_val), (_mask))

/* break link & next page link timer offsets */
#define READ_XGXS16G_BAM_NEXTPAGE_LINK_TIMER_OFFSET3r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008353, (_val))
#define WRITE_XGXS16G_BAM_NEXTPAGE_LINK_TIMER_OFFSET3r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008353, (_val))
#define MODIFY_XGXS16G_BAM_NEXTPAGE_LINK_TIMER_OFFSET3r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008353, (_val), (_mask))

/* 11 MSbits of the oui, oui[23:13] */
#define READ_XGXS16G_BAM_NEXTPAGE_OUI_MSB_FIELDr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008354, (_val))
#define WRITE_XGXS16G_BAM_NEXTPAGE_OUI_MSB_FIELDr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008354, (_val))
#define MODIFY_XGXS16G_BAM_NEXTPAGE_OUI_MSB_FIELDr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008354, (_val), (_mask))

/* 11 middle bits of the oui, oui[12:2] */
#define READ_XGXS16G_BAM_NEXTPAGE_OUI_LSB_FIELDr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008355, (_val))
#define WRITE_XGXS16G_BAM_NEXTPAGE_OUI_LSB_FIELDr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008355, (_val))
#define MODIFY_XGXS16G_BAM_NEXTPAGE_OUI_LSB_FIELDr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008355, (_val), (_mask))

/* 2 LSbits of the oui, oui[1:0] */
#define READ_XGXS16G_BAM_NEXTPAGE_BAM_FIELDr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008356, (_val))
#define WRITE_XGXS16G_BAM_NEXTPAGE_BAM_FIELDr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008356, (_val))
#define MODIFY_XGXS16G_BAM_NEXTPAGE_BAM_FIELDr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008356, (_val), (_mask))

/* User defined field of MP5 */
#define READ_XGXS16G_BAM_NEXTPAGE_UD_FIELDr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008357, (_val))
#define WRITE_XGXS16G_BAM_NEXTPAGE_UD_FIELDr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008357, (_val))
#define MODIFY_XGXS16G_BAM_NEXTPAGE_UD_FIELDr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008357, (_val), (_mask))

/* Link partner's 11 MSbits of the oui, oui[23:13] */
#define READ_XGXS16G_BAM_NEXTPAGE_LP_OUI_MSB_FIELDr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008358, (_val))
#define WRITE_XGXS16G_BAM_NEXTPAGE_LP_OUI_MSB_FIELDr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008358, (_val))
#define MODIFY_XGXS16G_BAM_NEXTPAGE_LP_OUI_MSB_FIELDr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008358, (_val), (_mask))

/* Link partner's 11 middle bits of the oui, oui[12:2] */
#define READ_XGXS16G_BAM_NEXTPAGE_LP_OUI_LSB_FIELDr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008359, (_val))
#define WRITE_XGXS16G_BAM_NEXTPAGE_LP_OUI_LSB_FIELDr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008359, (_val))
#define MODIFY_XGXS16G_BAM_NEXTPAGE_LP_OUI_LSB_FIELDr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008359, (_val), (_mask))

/* Link partner's 2 LSbits of the oui, oui[1:0] */
#define READ_XGXS16G_BAM_NEXTPAGE_LP_BAM_FIELDr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000835a, (_val))
#define WRITE_XGXS16G_BAM_NEXTPAGE_LP_BAM_FIELDr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000835a, (_val))
#define MODIFY_XGXS16G_BAM_NEXTPAGE_LP_BAM_FIELDr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000835a, (_val), (_mask))

/* Link partner's User defined field of MP5 */
#define READ_XGXS16G_BAM_NEXTPAGE_LP_UD_FIELDr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000835b, (_val))
#define WRITE_XGXS16G_BAM_NEXTPAGE_LP_UD_FIELDr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000835b, (_val))
#define MODIFY_XGXS16G_BAM_NEXTPAGE_LP_UD_FIELDr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000835b, (_val), (_mask))


/****************************************************************************
 * XGXS16G_USER_CL73_UserB0
 ***************************************************************************/

/* Clause 73 user control */
#define READ_XGXS16G_CL73_USERB0_CL73_UCTRL1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008370, (_val))
#define WRITE_XGXS16G_CL73_USERB0_CL73_UCTRL1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008370, (_val))
#define MODIFY_XGXS16G_CL73_USERB0_CL73_UCTRL1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008370, (_val), (_mask))

/* Clause 73 user status */
#define READ_XGXS16G_CL73_USERB0_CL73_USTAT1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008371, (_val))
#define WRITE_XGXS16G_CL73_USERB0_CL73_USTAT1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008371, (_val))
#define MODIFY_XGXS16G_CL73_USERB0_CL73_USTAT1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008371, (_val), (_mask))

/* Clause 73 BAM control 1 */
#define READ_XGXS16G_CL73_USERB0_CL73_BAMCTRL1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008372, (_val))
#define WRITE_XGXS16G_CL73_USERB0_CL73_BAMCTRL1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008372, (_val))
#define MODIFY_XGXS16G_CL73_USERB0_CL73_BAMCTRL1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008372, (_val), (_mask))

/* Clause 73 BAM control 2 */
#define READ_XGXS16G_CL73_USERB0_CL73_BAMCTRL2r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008373, (_val))
#define WRITE_XGXS16G_CL73_USERB0_CL73_BAMCTRL2r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008373, (_val))
#define MODIFY_XGXS16G_CL73_USERB0_CL73_BAMCTRL2r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008373, (_val), (_mask))

/* Clause 73 BAM control 3 */
#define READ_XGXS16G_CL73_USERB0_CL73_BAMCTRL3r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008374, (_val))
#define WRITE_XGXS16G_CL73_USERB0_CL73_BAMCTRL3r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008374, (_val))
#define MODIFY_XGXS16G_CL73_USERB0_CL73_BAMCTRL3r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008374, (_val), (_mask))

/* Clause 73 BAM status 1 */
#define READ_XGXS16G_CL73_USERB0_CL73_BAMSTAT1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008375, (_val))
#define WRITE_XGXS16G_CL73_USERB0_CL73_BAMSTAT1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008375, (_val))
#define MODIFY_XGXS16G_CL73_USERB0_CL73_BAMSTAT1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008375, (_val), (_mask))

/* Clause 73 BAM status 2 */
#define READ_XGXS16G_CL73_USERB0_CL73_BAMSTAT2r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008376, (_val))
#define WRITE_XGXS16G_CL73_USERB0_CL73_BAMSTAT2r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008376, (_val))
#define MODIFY_XGXS16G_CL73_USERB0_CL73_BAMSTAT2r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008376, (_val), (_mask))

/* Clause 73 BAM status 3 */
#define READ_XGXS16G_CL73_USERB0_CL73_BAMSTAT3r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008377, (_val))
#define WRITE_XGXS16G_CL73_USERB0_CL73_BAMSTAT3r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008377, (_val))
#define MODIFY_XGXS16G_CL73_USERB0_CL73_BAMSTAT3r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008377, (_val), (_mask))

/****************************************************************************
 * Hypercore_USER_FX100
 ***************************************************************************/

/* 100FX control register 1 */
#define READ_XGXS16G_FX100_CONTROL1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008400, (_val))
#define WRITE_XGXS16G_FX100_CONTROL1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008400, (_val))
#define MODIFY_XGXS16G_FX100_CONTROL1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008400, (_val), (_mask))

/* 100FX control register 2 */
#define READ_XGXS16G_FX100_CONTROL2r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008401, (_val))
#define WRITE_XGXS16G_FX100_CONTROL2r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008401, (_val))
#define MODIFY_XGXS16G_FX100_CONTROL2r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008401, (_val), (_mask))

/* 100FX control register 3 */
#define READ_XGXS16G_FX100_CONTROL3r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008402, (_val))
#define WRITE_XGXS16G_FX100_CONTROL3r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008402, (_val))
#define MODIFY_XGXS16G_FX100_CONTROL3r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008402, (_val), (_mask))

/* 100FX status register 1 */
#define READ_XGXS16G_FX100_STATUS1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008403, (_val))
#define WRITE_XGXS16G_FX100_STATUS1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008403, (_val))
#define MODIFY_XGXS16G_FX100_STATUS1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008403, (_val), (_mask))

/* 100FX status register 3 */
#define READ_XGXS16G_FX100_STATUS3r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008405, (_val))
#define WRITE_XGXS16G_FX100_STATUS3r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008405, (_val))
#define MODIFY_XGXS16G_FX100_STATUS3r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008405, (_val), (_mask))

/* 100FX status register 4 */
#define READ_XGXS16G_FX100_STATUS4r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008406, (_val))
#define WRITE_XGXS16G_FX100_STATUS4r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008406, (_val))
#define MODIFY_XGXS16G_FX100_STATUS4r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008406, (_val), (_mask))

/****************************************************************************
 * XGXS16G_USER_aerBlk
 ***************************************************************************/

/* Address Expansion Register */
#define READ_XGXS16G_AERBLK_AERr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000ffde, (_val))
#define WRITE_XGXS16G_AERBLK_AERr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffde, (_val))
#define MODIFY_XGXS16G_AERBLK_AERr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffde, (_val), (_mask))


/****************************************************************************
 * XGXS16G_USER_Combo_IEEE0
 ***************************************************************************/

/* IEEE MII control register */
#define READ_XGXS16G_COMBO_IEEE0_MIICNTLr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000ffe0, (_val))
#define WRITE_XGXS16G_COMBO_IEEE0_MIICNTLr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe0, (_val))
#define MODIFY_XGXS16G_COMBO_IEEE0_MIICNTLr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe0, (_val), (_mask))

/* IEEE MII status register */
#define READ_XGXS16G_COMBO_IEEE0_MIISTATr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000ffe1, (_val))
#define WRITE_XGXS16G_COMBO_IEEE0_MIISTATr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe1, (_val))
#define MODIFY_XGXS16G_COMBO_IEEE0_MIISTATr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe1, (_val), (_mask))

/* IEEE phy ID LSByte register */
#define READ_XGXS16G_COMBO_IEEE0_ID1r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000ffe2, (_val))
#define WRITE_XGXS16G_COMBO_IEEE0_ID1r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe2, (_val))
#define MODIFY_XGXS16G_COMBO_IEEE0_ID1r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe2, (_val), (_mask))

/* IEEE phy ID MSByte register */
#define READ_XGXS16G_COMBO_IEEE0_ID2r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000ffe3, (_val))
#define WRITE_XGXS16G_COMBO_IEEE0_ID2r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe3, (_val))
#define MODIFY_XGXS16G_COMBO_IEEE0_ID2r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe3, (_val), (_mask))

/* IEEE auto-negotiation advertiesed abilities register */
#define READ_XGXS16G_COMBO_IEEE0_AUTONEGADVr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000ffe4, (_val))
#define WRITE_XGXS16G_COMBO_IEEE0_AUTONEGADVr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe4, (_val))
#define MODIFY_XGXS16G_COMBO_IEEE0_AUTONEGADVr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe4, (_val), (_mask))

/* IEEE auto-negotiation link partner abilities register */
#define READ_XGXS16G_COMBO_IEEE0_AUTONEGLPABILr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000ffe5, (_val))
#define WRITE_XGXS16G_COMBO_IEEE0_AUTONEGLPABILr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe5, (_val))
#define MODIFY_XGXS16G_COMBO_IEEE0_AUTONEGLPABILr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe5, (_val), (_mask))

/* IEEE auto-negotiation expansion register */
#define READ_XGXS16G_COMBO_IEEE0_AUTONEGEXPr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000ffe6, (_val))
#define WRITE_XGXS16G_COMBO_IEEE0_AUTONEGEXPr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe6, (_val))
#define MODIFY_XGXS16G_COMBO_IEEE0_AUTONEGEXPr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe6, (_val), (_mask))

/* IEEE auto-negotiation next page register */
#define READ_XGXS16G_COMBO_IEEE0_AUTONEGNPr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000ffe7, (_val))
#define WRITE_XGXS16G_COMBO_IEEE0_AUTONEGNPr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe7, (_val))
#define MODIFY_XGXS16G_COMBO_IEEE0_AUTONEGNPr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe7, (_val), (_mask))

/* IEEE auto-negotiation link partner next page register */
#define READ_XGXS16G_COMBO_IEEE0_AUTONEGLPABIL2r(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000ffe8, (_val))
#define WRITE_XGXS16G_COMBO_IEEE0_AUTONEGLPABIL2r(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe8, (_val))
#define MODIFY_XGXS16G_COMBO_IEEE0_AUTONEGLPABIL2r(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe8, (_val), (_mask))

/* IEEE MII extended status register */
#define READ_XGXS16G_COMBO_IEEE0_MIIEXTSTATr(_unit, _pc, _val) \
             XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000ffef, (_val))
#define WRITE_XGXS16G_COMBO_IEEE0_MIIEXTSTATr(_unit, _pc, _val) \
             XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffef, (_val))
#define MODIFY_XGXS16G_COMBO_IEEE0_MIIEXTSTATr(_unit, _pc, _val, _mask) \
             XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffef, (_val), (_mask))


/****************************************************************************
 * XGXS16G_IEEE_ieee0Blk
 ***************************************************************************/
/****************************************************************************
 * ieee0Blk :: ieeeControl0
 ***************************************************************************/
/* ieee0Blk :: ieeeControl0 :: rst_hw [15:15] */
#define IEEE0BLK_IEEECONTROL0_RST_HW_MASK                          0x8000
#define IEEE0BLK_IEEECONTROL0_RST_HW_ALIGN                         0
#define IEEE0BLK_IEEECONTROL0_RST_HW_BITS                          1
#define IEEE0BLK_IEEECONTROL0_RST_HW_SHIFT                         15

/* ieee0Blk :: ieeeControl0 :: gloopback [14:14] */
#define IEEE0BLK_IEEECONTROL0_GLOOPBACK_MASK                       0x4000
#define IEEE0BLK_IEEECONTROL0_GLOOPBACK_ALIGN                      0
#define IEEE0BLK_IEEECONTROL0_GLOOPBACK_BITS                       1
#define IEEE0BLK_IEEECONTROL0_GLOOPBACK_SHIFT                      14

/* ieee0Blk :: ieeeControl0 :: manual_speed0 [13:13] */
#define IEEE0BLK_IEEECONTROL0_MANUAL_SPEED0_MASK                   0x2000
#define IEEE0BLK_IEEECONTROL0_MANUAL_SPEED0_ALIGN                  0
#define IEEE0BLK_IEEECONTROL0_MANUAL_SPEED0_BITS                   1
#define IEEE0BLK_IEEECONTROL0_MANUAL_SPEED0_SHIFT                  13

/* ieee0Blk :: ieeeControl0 :: autoneg_enable [12:12] */
#define IEEE0BLK_IEEECONTROL0_AUTONEG_ENABLE_MASK                  0x1000
#define IEEE0BLK_IEEECONTROL0_AUTONEG_ENABLE_ALIGN                 0
#define IEEE0BLK_IEEECONTROL0_AUTONEG_ENABLE_BITS                  1
#define IEEE0BLK_IEEECONTROL0_AUTONEG_ENABLE_SHIFT                 12

/* ieee0Blk :: ieeeControl0 :: pwrdwn_sw [11:11] */
#define IEEE0BLK_IEEECONTROL0_PWRDWN_SW_MASK                       0x0800
#define IEEE0BLK_IEEECONTROL0_PWRDWN_SW_ALIGN                      0
#define IEEE0BLK_IEEECONTROL0_PWRDWN_SW_BITS                       1
#define IEEE0BLK_IEEECONTROL0_PWRDWN_SW_SHIFT                      11

/* ieee0Blk :: ieeeControl0 :: reserved0 [10:10] */
#define IEEE0BLK_IEEECONTROL0_RESERVED0_MASK                       0x0400
#define IEEE0BLK_IEEECONTROL0_RESERVED0_ALIGN                      0
#define IEEE0BLK_IEEECONTROL0_RESERVED0_BITS                       1
#define IEEE0BLK_IEEECONTROL0_RESERVED0_SHIFT                      10

/* ieee0Blk :: ieeeControl0 :: restart_autoneg [09:09] */
#define IEEE0BLK_IEEECONTROL0_RESTART_AUTONEG_MASK                 0x0200
#define IEEE0BLK_IEEECONTROL0_RESTART_AUTONEG_ALIGN                0
#define IEEE0BLK_IEEECONTROL0_RESTART_AUTONEG_BITS                 1
#define IEEE0BLK_IEEECONTROL0_RESTART_AUTONEG_SHIFT                9

/* ieee0Blk :: ieeeControl0 :: full_duplex [08:08] */
#define IEEE0BLK_IEEECONTROL0_FULL_DUPLEX_MASK                     0x0100
#define IEEE0BLK_IEEECONTROL0_FULL_DUPLEX_ALIGN                    0
#define IEEE0BLK_IEEECONTROL0_FULL_DUPLEX_BITS                     1
#define IEEE0BLK_IEEECONTROL0_FULL_DUPLEX_SHIFT                    8

/* ieee0Blk :: ieeeControl0 :: collision_test_en [07:07] */
#define IEEE0BLK_IEEECONTROL0_COLLISION_TEST_EN_MASK               0x0080
#define IEEE0BLK_IEEECONTROL0_COLLISION_TEST_EN_ALIGN              0
#define IEEE0BLK_IEEECONTROL0_COLLISION_TEST_EN_BITS               1
#define IEEE0BLK_IEEECONTROL0_COLLISION_TEST_EN_SHIFT              7

/* ieee0Blk :: ieeeControl0 :: manual_speed1 [06:06] */
#define IEEE0BLK_IEEECONTROL0_MANUAL_SPEED1_MASK                   0x0040
#define IEEE0BLK_IEEECONTROL0_MANUAL_SPEED1_ALIGN                  0
#define IEEE0BLK_IEEECONTROL0_MANUAL_SPEED1_BITS                   1
#define IEEE0BLK_IEEECONTROL0_MANUAL_SPEED1_SHIFT                  6

/* ieee0Blk :: ieeeControl0 :: reserved1 [05:00] */
#define IEEE0BLK_IEEECONTROL0_RESERVED1_MASK                       0x003f
#define IEEE0BLK_IEEECONTROL0_RESERVED1_ALIGN                      0
#define IEEE0BLK_IEEECONTROL0_RESERVED1_BITS                       6
#define IEEE0BLK_IEEECONTROL0_RESERVED1_SHIFT                      0


/****************************************************************************
 * XGXS16G_IEEE_ieee1Blk
 ***************************************************************************/
/****************************************************************************
 * ieee1Blk :: ieeeControl1
 ***************************************************************************/
/* ieee1Blk :: ieeeControl1 :: rst_hw [15:15] */
#define IEEE1BLK_IEEECONTROL1_RST_HW_MASK                          0x8000
#define IEEE1BLK_IEEECONTROL1_RST_HW_ALIGN                         0
#define IEEE1BLK_IEEECONTROL1_RST_HW_BITS                          1
#define IEEE1BLK_IEEECONTROL1_RST_HW_SHIFT                         15

/* ieee1Blk :: ieeeControl1 :: gloopback [14:14] */
#define IEEE1BLK_IEEECONTROL1_GLOOPBACK_MASK                       0x4000
#define IEEE1BLK_IEEECONTROL1_GLOOPBACK_ALIGN                      0
#define IEEE1BLK_IEEECONTROL1_GLOOPBACK_BITS                       1
#define IEEE1BLK_IEEECONTROL1_GLOOPBACK_SHIFT                      14

/* ieee1Blk :: ieeeControl1 :: manual_speed0 [13:13] */
#define IEEE1BLK_IEEECONTROL1_MANUAL_SPEED0_MASK                   0x2000
#define IEEE1BLK_IEEECONTROL1_MANUAL_SPEED0_ALIGN                  0
#define IEEE1BLK_IEEECONTROL1_MANUAL_SPEED0_BITS                   1
#define IEEE1BLK_IEEECONTROL1_MANUAL_SPEED0_SHIFT                  13

/* ieee1Blk :: ieeeControl1 :: autoneg_enable [12:12] */
#define IEEE1BLK_IEEECONTROL1_AUTONEG_ENABLE_MASK                  0x1000
#define IEEE1BLK_IEEECONTROL1_AUTONEG_ENABLE_ALIGN                 0
#define IEEE1BLK_IEEECONTROL1_AUTONEG_ENABLE_BITS                  1
#define IEEE1BLK_IEEECONTROL1_AUTONEG_ENABLE_SHIFT                 12

/* ieee1Blk :: ieeeControl1 :: pwrdwn_sw [11:11] */
#define IEEE1BLK_IEEECONTROL1_PWRDWN_SW_MASK                       0x0800
#define IEEE1BLK_IEEECONTROL1_PWRDWN_SW_ALIGN                      0
#define IEEE1BLK_IEEECONTROL1_PWRDWN_SW_BITS                       1
#define IEEE1BLK_IEEECONTROL1_PWRDWN_SW_SHIFT                      11

/* ieee1Blk :: ieeeControl1 :: reserved0 [10:10] */
#define IEEE1BLK_IEEECONTROL1_RESERVED0_MASK                       0x0400
#define IEEE1BLK_IEEECONTROL1_RESERVED0_ALIGN                      0
#define IEEE1BLK_IEEECONTROL1_RESERVED0_BITS                       1
#define IEEE1BLK_IEEECONTROL1_RESERVED0_SHIFT                      10

/* ieee1Blk :: ieeeControl1 :: restart_autoneg [09:09] */
#define IEEE1BLK_IEEECONTROL1_RESTART_AUTONEG_MASK                 0x0200
#define IEEE1BLK_IEEECONTROL1_RESTART_AUTONEG_ALIGN                0
#define IEEE1BLK_IEEECONTROL1_RESTART_AUTONEG_BITS                 1
#define IEEE1BLK_IEEECONTROL1_RESTART_AUTONEG_SHIFT                9

/* ieee1Blk :: ieeeControl1 :: full_duplex [08:08] */
#define IEEE1BLK_IEEECONTROL1_FULL_DUPLEX_MASK                     0x0100
#define IEEE1BLK_IEEECONTROL1_FULL_DUPLEX_ALIGN                    0
#define IEEE1BLK_IEEECONTROL1_FULL_DUPLEX_BITS                     1
#define IEEE1BLK_IEEECONTROL1_FULL_DUPLEX_SHIFT                    8

/* ieee1Blk :: ieeeControl1 :: collision_test_en [07:07] */
#define IEEE1BLK_IEEECONTROL1_COLLISION_TEST_EN_MASK               0x0080
#define IEEE1BLK_IEEECONTROL1_COLLISION_TEST_EN_ALIGN              0
#define IEEE1BLK_IEEECONTROL1_COLLISION_TEST_EN_BITS               1
#define IEEE1BLK_IEEECONTROL1_COLLISION_TEST_EN_SHIFT              7

/* ieee1Blk :: ieeeControl1 :: manual_speed1 [06:06] */
#define IEEE1BLK_IEEECONTROL1_MANUAL_SPEED1_MASK                   0x0040
#define IEEE1BLK_IEEECONTROL1_MANUAL_SPEED1_ALIGN                  0
#define IEEE1BLK_IEEECONTROL1_MANUAL_SPEED1_BITS                   1
#define IEEE1BLK_IEEECONTROL1_MANUAL_SPEED1_SHIFT                  6

/* ieee1Blk :: ieeeControl1 :: reserved1 [05:00] */
#define IEEE1BLK_IEEECONTROL1_RESERVED1_MASK                       0x003f
#define IEEE1BLK_IEEECONTROL1_RESERVED1_ALIGN                      0
#define IEEE1BLK_IEEECONTROL1_RESERVED1_BITS                       6
#define IEEE1BLK_IEEECONTROL1_RESERVED1_SHIFT                      0


/****************************************************************************
 * XGXS16G_USER_XgxsBlk0
 ***************************************************************************/
/****************************************************************************
 * XgxsBlk0 :: xgxsControl
 ***************************************************************************/
/* XgxsBlk0 :: xgxsControl :: pgen_en [15:15] */
#define XGXSBLK0_XGXSCONTROL_PGEN_EN_MASK                          0x8000
#define XGXSBLK0_XGXSCONTROL_PGEN_EN_ALIGN                         0
#define XGXSBLK0_XGXSCONTROL_PGEN_EN_BITS                          1
#define XGXSBLK0_XGXSCONTROL_PGEN_EN_SHIFT                         15

/* XgxsBlk0 :: xgxsControl :: pcmp_en [14:14] */
#define XGXSBLK0_XGXSCONTROL_PCMP_EN_MASK                          0x4000
#define XGXSBLK0_XGXSCONTROL_PCMP_EN_ALIGN                         0
#define XGXSBLK0_XGXSCONTROL_PCMP_EN_BITS                          1
#define XGXSBLK0_XGXSCONTROL_PCMP_EN_SHIFT                         14

/* XgxsBlk0 :: xgxsControl :: start_sequencer [13:13] */
#define XGXSBLK0_XGXSCONTROL_START_SEQUENCER_MASK                  0x2000
#define XGXSBLK0_XGXSCONTROL_START_SEQUENCER_ALIGN                 0
#define XGXSBLK0_XGXSCONTROL_START_SEQUENCER_BITS                  1
#define XGXSBLK0_XGXSCONTROL_START_SEQUENCER_SHIFT                 13

/* XgxsBlk0 :: xgxsControl :: reset_anlg [12:12] */
#define XGXSBLK0_XGXSCONTROL_RESET_ANLG_MASK                       0x1000
#define XGXSBLK0_XGXSCONTROL_RESET_ANLG_ALIGN                      0
#define XGXSBLK0_XGXSCONTROL_RESET_ANLG_BITS                       1
#define XGXSBLK0_XGXSCONTROL_RESET_ANLG_SHIFT                      12

/* XgxsBlk0 :: xgxsControl :: mode_10g [11:08] */
#define XGXSBLK0_XGXSCONTROL_MODE_10G_MASK                         0x0f00
#define XGXSBLK0_XGXSCONTROL_MODE_10G_ALIGN                        0
#define XGXSBLK0_XGXSCONTROL_MODE_10G_BITS                         4
#define XGXSBLK0_XGXSCONTROL_MODE_10G_SHIFT                        8
#define XGXSBLK0_XGXSCONTROL_MODE_10G_XGXS                         0
#define XGXSBLK0_XGXSCONTROL_MODE_10G_XGXS_noCC                    1
#define XGXSBLK0_XGXSCONTROL_MODE_10G_IndLane                      6
#define XGXSBLK0_XGXSCONTROL_MODE_10G_XGXS_noLss                   8
#define XGXSBLK0_XGXSCONTROL_MODE_10G_XGXS_noLss_noCC              9
#define XGXSBLK0_XGXSCONTROL_MODE_10G_protBypass                   10
#define XGXSBLK0_XGXSCONTROL_MODE_10G_protBypass_noDsk             11
#define XGXSBLK0_XGXSCONTROL_MODE_10G_ComboCoreMode                12
#define XGXSBLK0_XGXSCONTROL_MODE_10G_ClocksOff                    15

/* XgxsBlk0 :: xgxsControl :: pll_bypass [07:07] */
#define XGXSBLK0_XGXSCONTROL_PLL_BYPASS_MASK                       0x0080
#define XGXSBLK0_XGXSCONTROL_PLL_BYPASS_ALIGN                      0
#define XGXSBLK0_XGXSCONTROL_PLL_BYPASS_BITS                       1
#define XGXSBLK0_XGXSCONTROL_PLL_BYPASS_SHIFT                      7

/* XgxsBlk0 :: xgxsControl :: rloop [06:06] */
#define XGXSBLK0_XGXSCONTROL_RLOOP_MASK                            0x0040
#define XGXSBLK0_XGXSCONTROL_RLOOP_ALIGN                           0
#define XGXSBLK0_XGXSCONTROL_RLOOP_BITS                            1
#define XGXSBLK0_XGXSCONTROL_RLOOP_SHIFT                           6

/* XgxsBlk0 :: xgxsControl :: hstl [05:05] */
#define XGXSBLK0_XGXSCONTROL_HSTL_MASK                             0x0020
#define XGXSBLK0_XGXSCONTROL_HSTL_ALIGN                            0
#define XGXSBLK0_XGXSCONTROL_HSTL_BITS                             1
#define XGXSBLK0_XGXSCONTROL_HSTL_SHIFT                            5

/* XgxsBlk0 :: xgxsControl :: mdio_cont_en [04:04] */
#define XGXSBLK0_XGXSCONTROL_MDIO_CONT_EN_MASK                     0x0010
#define XGXSBLK0_XGXSCONTROL_MDIO_CONT_EN_ALIGN                    0
#define XGXSBLK0_XGXSCONTROL_MDIO_CONT_EN_BITS                     1
#define XGXSBLK0_XGXSCONTROL_MDIO_CONT_EN_SHIFT                    4

/* XgxsBlk0 :: xgxsControl :: cdet_en [03:03] */
#define XGXSBLK0_XGXSCONTROL_CDET_EN_MASK                          0x0008
#define XGXSBLK0_XGXSCONTROL_CDET_EN_ALIGN                         0
#define XGXSBLK0_XGXSCONTROL_CDET_EN_BITS                          1
#define XGXSBLK0_XGXSCONTROL_CDET_EN_SHIFT                         3

/* XgxsBlk0 :: xgxsControl :: eden [02:02] */
#define XGXSBLK0_XGXSCONTROL_EDEN_MASK                             0x0004
#define XGXSBLK0_XGXSCONTROL_EDEN_ALIGN                            0
#define XGXSBLK0_XGXSCONTROL_EDEN_BITS                             1
#define XGXSBLK0_XGXSCONTROL_EDEN_SHIFT                            2

/* XgxsBlk0 :: xgxsControl :: afrst_en [01:01] */
#define XGXSBLK0_XGXSCONTROL_AFRST_EN_MASK                         0x0002
#define XGXSBLK0_XGXSCONTROL_AFRST_EN_ALIGN                        0
#define XGXSBLK0_XGXSCONTROL_AFRST_EN_BITS                         1
#define XGXSBLK0_XGXSCONTROL_AFRST_EN_SHIFT                        1

/* XgxsBlk0 :: xgxsControl :: txcko_div [00:00] */
#define XGXSBLK0_XGXSCONTROL_TXCKO_DIV_MASK                        0x0001
#define XGXSBLK0_XGXSCONTROL_TXCKO_DIV_ALIGN                       0
#define XGXSBLK0_XGXSCONTROL_TXCKO_DIV_BITS                        1
#define XGXSBLK0_XGXSCONTROL_TXCKO_DIV_SHIFT                       0


/****************************************************************************
 * XgxsBlk0 :: xgxsStatus
 ***************************************************************************/
/* XgxsBlk0 :: xgxsStatus :: status_en [15:15] */
#define XGXSBLK0_XGXSSTATUS_STATUS_EN_MASK                         0x8000
#define XGXSBLK0_XGXSSTATUS_STATUS_EN_ALIGN                        0
#define XGXSBLK0_XGXSSTATUS_STATUS_EN_BITS                         1
#define XGXSBLK0_XGXSSTATUS_STATUS_EN_SHIFT                        15

/* XgxsBlk0 :: xgxsStatus :: reserved0 [14:14] */
#define XGXSBLK0_XGXSSTATUS_RESERVED0_MASK                         0x4000
#define XGXSBLK0_XGXSSTATUS_RESERVED0_ALIGN                        0
#define XGXSBLK0_XGXSSTATUS_RESERVED0_BITS                         1
#define XGXSBLK0_XGXSSTATUS_RESERVED0_SHIFT                        14

/* XgxsBlk0 :: xgxsStatus :: tx_remote_fault [13:13] */
#define XGXSBLK0_XGXSSTATUS_TX_REMOTE_FAULT_MASK                   0x2000
#define XGXSBLK0_XGXSSTATUS_TX_REMOTE_FAULT_ALIGN                  0
#define XGXSBLK0_XGXSSTATUS_TX_REMOTE_FAULT_BITS                   1
#define XGXSBLK0_XGXSSTATUS_TX_REMOTE_FAULT_SHIFT                  13

/* XgxsBlk0 :: xgxsStatus :: rx_remote_fault [12:12] */
#define XGXSBLK0_XGXSSTATUS_RX_REMOTE_FAULT_MASK                   0x1000
#define XGXSBLK0_XGXSSTATUS_RX_REMOTE_FAULT_ALIGN                  0
#define XGXSBLK0_XGXSSTATUS_RX_REMOTE_FAULT_BITS                   1
#define XGXSBLK0_XGXSSTATUS_RX_REMOTE_FAULT_SHIFT                  12

/* XgxsBlk0 :: xgxsStatus :: txpll_lock [11:11] */
#define XGXSBLK0_XGXSSTATUS_TXPLL_LOCK_MASK                        0x0800
#define XGXSBLK0_XGXSSTATUS_TXPLL_LOCK_ALIGN                       0
#define XGXSBLK0_XGXSSTATUS_TXPLL_LOCK_BITS                        1
#define XGXSBLK0_XGXSSTATUS_TXPLL_LOCK_SHIFT                       11

/* XgxsBlk0 :: xgxsStatus :: txd_fifo_err [10:10] */
#define XGXSBLK0_XGXSSTATUS_TXD_FIFO_ERR_MASK                      0x0400
#define XGXSBLK0_XGXSSTATUS_TXD_FIFO_ERR_ALIGN                     0
#define XGXSBLK0_XGXSSTATUS_TXD_FIFO_ERR_BITS                      1
#define XGXSBLK0_XGXSSTATUS_TXD_FIFO_ERR_SHIFT                     10

/* XgxsBlk0 :: xgxsStatus :: sequencer_done [09:09] */
#define XGXSBLK0_XGXSSTATUS_SEQUENCER_DONE_MASK                    0x0200
#define XGXSBLK0_XGXSSTATUS_SEQUENCER_DONE_ALIGN                   0
#define XGXSBLK0_XGXSSTATUS_SEQUENCER_DONE_BITS                    1
#define XGXSBLK0_XGXSSTATUS_SEQUENCER_DONE_SHIFT                   9

/* XgxsBlk0 :: xgxsStatus :: sequencer_pass [08:08] */
#define XGXSBLK0_XGXSSTATUS_SEQUENCER_PASS_MASK                    0x0100
#define XGXSBLK0_XGXSSTATUS_SEQUENCER_PASS_ALIGN                   0
#define XGXSBLK0_XGXSSTATUS_SEQUENCER_PASS_BITS                    1
#define XGXSBLK0_XGXSSTATUS_SEQUENCER_PASS_SHIFT                   8

/* XgxsBlk0 :: xgxsStatus :: rxferr [07:04] */
#define XGXSBLK0_XGXSSTATUS_RXFERR_MASK                            0x00f0
#define XGXSBLK0_XGXSSTATUS_RXFERR_ALIGN                           0
#define XGXSBLK0_XGXSSTATUS_RXFERR_BITS                            4
#define XGXSBLK0_XGXSSTATUS_RXFERR_SHIFT                           4

/* XgxsBlk0 :: xgxsStatus :: pll_mode_afe [03:03] */
#define XGXSBLK0_XGXSSTATUS_PLL_MODE_AFE_MASK                      0x0008
#define XGXSBLK0_XGXSSTATUS_PLL_MODE_AFE_ALIGN                     0
#define XGXSBLK0_XGXSSTATUS_PLL_MODE_AFE_BITS                      1
#define XGXSBLK0_XGXSSTATUS_PLL_MODE_AFE_SHIFT                     3

/* XgxsBlk0 :: xgxsStatus :: ckcmp_unflow [02:02] */
#define XGXSBLK0_XGXSSTATUS_CKCMP_UNFLOW_MASK                      0x0004
#define XGXSBLK0_XGXSSTATUS_CKCMP_UNFLOW_ALIGN                     0
#define XGXSBLK0_XGXSSTATUS_CKCMP_UNFLOW_BITS                      1
#define XGXSBLK0_XGXSSTATUS_CKCMP_UNFLOW_SHIFT                     2

/* XgxsBlk0 :: xgxsStatus :: ckcmp_ovflow [01:01] */
#define XGXSBLK0_XGXSSTATUS_CKCMP_OVFLOW_MASK                      0x0002
#define XGXSBLK0_XGXSSTATUS_CKCMP_OVFLOW_ALIGN                     0
#define XGXSBLK0_XGXSSTATUS_CKCMP_OVFLOW_BITS                      1
#define XGXSBLK0_XGXSSTATUS_CKCMP_OVFLOW_SHIFT                     1

/* XgxsBlk0 :: xgxsStatus :: skew_status [00:00] */
#define XGXSBLK0_XGXSSTATUS_SKEW_STATUS_MASK                       0x0001
#define XGXSBLK0_XGXSSTATUS_SKEW_STATUS_ALIGN                      0
#define XGXSBLK0_XGXSSTATUS_SKEW_STATUS_BITS                       1
#define XGXSBLK0_XGXSSTATUS_SKEW_STATUS_SHIFT                      0


/****************************************************************************
 * XgxsBlk0 :: xgmiiIdle
 ***************************************************************************/
/* XgxsBlk0 :: xgmiiIdle :: I [15:08] */
#define XGXSBLK0_XGMIIIDLE_I_MASK                                  0xff00
#define XGXSBLK0_XGMIIIDLE_I_ALIGN                                 0
#define XGXSBLK0_XGMIIIDLE_I_BITS                                  8
#define XGXSBLK0_XGMIIIDLE_I_SHIFT                                 8

/* XgxsBlk0 :: xgmiiIdle :: Ib [07:00] */
#define XGXSBLK0_XGMIIIDLE_IB_MASK                                 0x00ff
#define XGXSBLK0_XGMIIIDLE_IB_ALIGN                                0
#define XGXSBLK0_XGMIIIDLE_IB_BITS                                 8
#define XGXSBLK0_XGMIIIDLE_IB_SHIFT                                0


/****************************************************************************
 * XgxsBlk0 :: xgmiiSync
 ***************************************************************************/
/* XgxsBlk0 :: xgmiiSync :: K [15:08] */
#define XGXSBLK0_XGMIISYNC_K_MASK                                  0xff00
#define XGXSBLK0_XGMIISYNC_K_ALIGN                                 0
#define XGXSBLK0_XGMIISYNC_K_BITS                                  8
#define XGXSBLK0_XGMIISYNC_K_SHIFT                                 8

/* XgxsBlk0 :: xgmiiSync :: Kb [07:00] */
#define XGXSBLK0_XGMIISYNC_KB_MASK                                 0x00ff
#define XGXSBLK0_XGMIISYNC_KB_ALIGN                                0
#define XGXSBLK0_XGMIISYNC_KB_BITS                                 8
#define XGXSBLK0_XGMIISYNC_KB_SHIFT                                0


/****************************************************************************
 * XgxsBlk0 :: xgmiiSkip
 ***************************************************************************/
/* XgxsBlk0 :: xgmiiSkip :: R [15:08] */
#define XGXSBLK0_XGMIISKIP_R_MASK                                  0xff00
#define XGXSBLK0_XGMIISKIP_R_ALIGN                                 0
#define XGXSBLK0_XGMIISKIP_R_BITS                                  8
#define XGXSBLK0_XGMIISKIP_R_SHIFT                                 8

/* XgxsBlk0 :: xgmiiSkip :: Rb [07:00] */
#define XGXSBLK0_XGMIISKIP_RB_MASK                                 0x00ff
#define XGXSBLK0_XGMIISKIP_RB_ALIGN                                0
#define XGXSBLK0_XGMIISKIP_RB_BITS                                 8
#define XGXSBLK0_XGMIISKIP_RB_SHIFT                                0


/****************************************************************************
 * XgxsBlk0 :: xgmiiSopEop
 ***************************************************************************/
/* XgxsBlk0 :: xgmiiSopEop :: S [15:08] */
#define XGXSBLK0_XGMIISOPEOP_S_MASK                                0xff00
#define XGXSBLK0_XGMIISOPEOP_S_ALIGN                               0
#define XGXSBLK0_XGMIISOPEOP_S_BITS                                8
#define XGXSBLK0_XGMIISOPEOP_S_SHIFT                               8

/* XgxsBlk0 :: xgmiiSopEop :: T [07:00] */
#define XGXSBLK0_XGMIISOPEOP_T_MASK                                0x00ff
#define XGXSBLK0_XGMIISOPEOP_T_ALIGN                               0
#define XGXSBLK0_XGMIISOPEOP_T_BITS                                8
#define XGXSBLK0_XGMIISOPEOP_T_SHIFT                               0


/****************************************************************************
 * XgxsBlk0 :: xgmiiAlign
 ***************************************************************************/
/* XgxsBlk0 :: xgmiiAlign :: E [15:08] */
#define XGXSBLK0_XGMIIALIGN_E_MASK                                 0xff00
#define XGXSBLK0_XGMIIALIGN_E_ALIGN                                0
#define XGXSBLK0_XGMIIALIGN_E_BITS                                 8
#define XGXSBLK0_XGMIIALIGN_E_SHIFT                                8

/* XgxsBlk0 :: xgmiiAlign :: A [07:00] */
#define XGXSBLK0_XGMIIALIGN_A_MASK                                 0x00ff
#define XGXSBLK0_XGMIIALIGN_A_ALIGN                                0
#define XGXSBLK0_XGMIIALIGN_A_BITS                                 8
#define XGXSBLK0_XGMIIALIGN_A_SHIFT                                0


/****************************************************************************
 * XgxsBlk0 :: xgmiiRcontrol
 ***************************************************************************/
/* XgxsBlk0 :: xgmiiRcontrol :: reserved0 [15:15] */
#define XGXSBLK0_XGMIIRCONTROL_RESERVED0_MASK                      0x8000
#define XGXSBLK0_XGMIIRCONTROL_RESERVED0_ALIGN                     0
#define XGXSBLK0_XGMIIRCONTROL_RESERVED0_BITS                      1
#define XGXSBLK0_XGMIIRCONTROL_RESERVED0_SHIFT                     15

/* XgxsBlk0 :: xgmiiRcontrol :: tx_lf0_en [14:14] */
#define XGXSBLK0_XGMIIRCONTROL_TX_LF0_EN_MASK                      0x4000
#define XGXSBLK0_XGMIIRCONTROL_TX_LF0_EN_ALIGN                     0
#define XGXSBLK0_XGMIIRCONTROL_TX_LF0_EN_BITS                      1
#define XGXSBLK0_XGMIIRCONTROL_TX_LF0_EN_SHIFT                     14

/* XgxsBlk0 :: xgmiiRcontrol :: tx_lf1_en [13:13] */
#define XGXSBLK0_XGMIIRCONTROL_TX_LF1_EN_MASK                      0x2000
#define XGXSBLK0_XGMIIRCONTROL_TX_LF1_EN_ALIGN                     0
#define XGXSBLK0_XGMIIRCONTROL_TX_LF1_EN_BITS                      1
#define XGXSBLK0_XGMIIRCONTROL_TX_LF1_EN_SHIFT                     13

/* XgxsBlk0 :: xgmiiRcontrol :: tx_lf2_en [12:12] */
#define XGXSBLK0_XGMIIRCONTROL_TX_LF2_EN_MASK                      0x1000
#define XGXSBLK0_XGMIIRCONTROL_TX_LF2_EN_ALIGN                     0
#define XGXSBLK0_XGMIIRCONTROL_TX_LF2_EN_BITS                      1
#define XGXSBLK0_XGMIIRCONTROL_TX_LF2_EN_SHIFT                     12

/* XgxsBlk0 :: xgmiiRcontrol :: force_inbndls_en [11:11] */
#define XGXSBLK0_XGMIIRCONTROL_FORCE_INBNDLS_EN_MASK               0x0800
#define XGXSBLK0_XGMIIRCONTROL_FORCE_INBNDLS_EN_ALIGN              0
#define XGXSBLK0_XGMIIRCONTROL_FORCE_INBNDLS_EN_BITS               1
#define XGXSBLK0_XGMIIRCONTROL_FORCE_INBNDLS_EN_SHIFT              11

/* XgxsBlk0 :: xgmiiRcontrol :: chk_end_en [10:10] */
#define XGXSBLK0_XGMIIRCONTROL_CHK_END_EN_MASK                     0x0400
#define XGXSBLK0_XGMIIRCONTROL_CHK_END_EN_ALIGN                    0
#define XGXSBLK0_XGMIIRCONTROL_CHK_END_EN_BITS                     1
#define XGXSBLK0_XGMIIRCONTROL_CHK_END_EN_SHIFT                    10

/* XgxsBlk0 :: xgmiiRcontrol :: chk_end_std_en [09:09] */
#define XGXSBLK0_XGMIIRCONTROL_CHK_END_STD_EN_MASK                 0x0200
#define XGXSBLK0_XGMIIRCONTROL_CHK_END_STD_EN_ALIGN                0
#define XGXSBLK0_XGMIIRCONTROL_CHK_END_STD_EN_BITS                 1
#define XGXSBLK0_XGMIIRCONTROL_CHK_END_STD_EN_SHIFT                9

/* XgxsBlk0 :: xgmiiRcontrol :: chk_end_force [08:08] */
#define XGXSBLK0_XGMIIRCONTROL_CHK_END_FORCE_MASK                  0x0100
#define XGXSBLK0_XGMIIRCONTROL_CHK_END_FORCE_ALIGN                 0
#define XGXSBLK0_XGMIIRCONTROL_CHK_END_FORCE_BITS                  1
#define XGXSBLK0_XGMIIRCONTROL_CHK_END_FORCE_SHIFT                 8

/* XgxsBlk0 :: xgmiiRcontrol :: reserved1 [07:07] */
#define XGXSBLK0_XGMIIRCONTROL_RESERVED1_MASK                      0x0080
#define XGXSBLK0_XGMIIRCONTROL_RESERVED1_ALIGN                     0
#define XGXSBLK0_XGMIIRCONTROL_RESERVED1_BITS                      1
#define XGXSBLK0_XGMIIRCONTROL_RESERVED1_SHIFT                     7

/* XgxsBlk0 :: xgmiiRcontrol :: scr_en_4lane [06:06] */
#define XGXSBLK0_XGMIIRCONTROL_SCR_EN_4LANE_MASK                   0x0040
#define XGXSBLK0_XGMIIRCONTROL_SCR_EN_4LANE_ALIGN                  0
#define XGXSBLK0_XGMIIRCONTROL_SCR_EN_4LANE_BITS                   1
#define XGXSBLK0_XGMIIRCONTROL_SCR_EN_4LANE_SHIFT                  6

/* XgxsBlk0 :: xgmiiRcontrol :: ckcmp_noIPG_en [05:05] */
#define XGXSBLK0_XGMIIRCONTROL_CKCMP_NOIPG_EN_MASK                 0x0020
#define XGXSBLK0_XGMIIRCONTROL_CKCMP_NOIPG_EN_ALIGN                0
#define XGXSBLK0_XGMIIRCONTROL_CKCMP_NOIPG_EN_BITS                 1
#define XGXSBLK0_XGMIIRCONTROL_CKCMP_NOIPG_EN_SHIFT                5

/* XgxsBlk0 :: xgmiiRcontrol :: ckcmp_afrst_en [04:04] */
#define XGXSBLK0_XGMIIRCONTROL_CKCMP_AFRST_EN_MASK                 0x0010
#define XGXSBLK0_XGMIIRCONTROL_CKCMP_AFRST_EN_ALIGN                0
#define XGXSBLK0_XGMIIRCONTROL_CKCMP_AFRST_EN_BITS                 1
#define XGXSBLK0_XGMIIRCONTROL_CKCMP_AFRST_EN_SHIFT                4

/* XgxsBlk0 :: xgmiiRcontrol :: ckcmp_gt1_Icol_dis [03:03] */
#define XGXSBLK0_XGMIIRCONTROL_CKCMP_GT1_ICOL_DIS_MASK             0x0008
#define XGXSBLK0_XGMIIRCONTROL_CKCMP_GT1_ICOL_DIS_ALIGN            0
#define XGXSBLK0_XGMIIRCONTROL_CKCMP_GT1_ICOL_DIS_BITS             1
#define XGXSBLK0_XGMIIRCONTROL_CKCMP_GT1_ICOL_DIS_SHIFT            3

/* XgxsBlk0 :: xgmiiRcontrol :: reserved2 [02:00] */
#define XGXSBLK0_XGMIIRCONTROL_RESERVED2_MASK                      0x0007
#define XGXSBLK0_XGMIIRCONTROL_RESERVED2_ALIGN                     0
#define XGXSBLK0_XGMIIRCONTROL_RESERVED2_BITS                      3
#define XGXSBLK0_XGMIIRCONTROL_RESERVED2_SHIFT                     0


/****************************************************************************
 * XgxsBlk0 :: xgmiiTcontrol
 ***************************************************************************/
/* XgxsBlk0 :: xgmiiTcontrol :: swapen [15:15] */
#define XGXSBLK0_XGMIITCONTROL_SWAPEN_MASK                         0x8000
#define XGXSBLK0_XGMIITCONTROL_SWAPEN_ALIGN                        0
#define XGXSBLK0_XGMIITCONTROL_SWAPEN_BITS                         1
#define XGXSBLK0_XGMIITCONTROL_SWAPEN_SHIFT                        15

/* XgxsBlk0 :: xgmiiTcontrol :: swap_lane_ind [14:14] */
#define XGXSBLK0_XGMIITCONTROL_SWAP_LANE_IND_MASK                  0x4000
#define XGXSBLK0_XGMIITCONTROL_SWAP_LANE_IND_ALIGN                 0
#define XGXSBLK0_XGMIITCONTROL_SWAP_LANE_IND_BITS                  1
#define XGXSBLK0_XGMIITCONTROL_SWAP_LANE_IND_SHIFT                 14

/* XgxsBlk0 :: xgmiiTcontrol :: pn_sel [13:13] */
#define XGXSBLK0_XGMIITCONTROL_PN_SEL_MASK                         0x2000
#define XGXSBLK0_XGMIITCONTROL_PN_SEL_ALIGN                        0
#define XGXSBLK0_XGMIITCONTROL_PN_SEL_BITS                         1
#define XGXSBLK0_XGMIITCONTROL_PN_SEL_SHIFT                        13

/* XgxsBlk0 :: xgmiiTcontrol :: reserved0 [12:09] */
#define XGXSBLK0_XGMIITCONTROL_RESERVED0_MASK                      0x1e00
#define XGXSBLK0_XGMIITCONTROL_RESERVED0_ALIGN                     0
#define XGXSBLK0_XGMIITCONTROL_RESERVED0_BITS                      4
#define XGXSBLK0_XGMIITCONTROL_RESERVED0_SHIFT                     9

/* XgxsBlk0 :: xgmiiTcontrol :: alignstat_rxlf_en [08:08] */
#define XGXSBLK0_XGMIITCONTROL_ALIGNSTAT_RXLF_EN_MASK              0x0100
#define XGXSBLK0_XGMIITCONTROL_ALIGNSTAT_RXLF_EN_ALIGN             0
#define XGXSBLK0_XGMIITCONTROL_ALIGNSTAT_RXLF_EN_BITS              1
#define XGXSBLK0_XGMIITCONTROL_ALIGNSTAT_RXLF_EN_SHIFT             8

/* XgxsBlk0 :: xgmiiTcontrol :: flip_txrx_lf [07:07] */
#define XGXSBLK0_XGMIITCONTROL_FLIP_TXRX_LF_MASK                   0x0080
#define XGXSBLK0_XGMIITCONTROL_FLIP_TXRX_LF_ALIGN                  0
#define XGXSBLK0_XGMIITCONTROL_FLIP_TXRX_LF_BITS                   1
#define XGXSBLK0_XGMIITCONTROL_FLIP_TXRX_LF_SHIFT                  7

/* XgxsBlk0 :: xgmiiTcontrol :: xenpak_lfclr_en [06:06] */
#define XGXSBLK0_XGMIITCONTROL_XENPAK_LFCLR_EN_MASK                0x0040
#define XGXSBLK0_XGMIITCONTROL_XENPAK_LFCLR_EN_ALIGN               0
#define XGXSBLK0_XGMIITCONTROL_XENPAK_LFCLR_EN_BITS                1
#define XGXSBLK0_XGMIITCONTROL_XENPAK_LFCLR_EN_SHIFT               6

/* XgxsBlk0 :: xgmiiTcontrol :: tx_xgmii_Tcol_old_en [05:05] */
#define XGXSBLK0_XGMIITCONTROL_TX_XGMII_TCOL_OLD_EN_MASK           0x0020
#define XGXSBLK0_XGMIITCONTROL_TX_XGMII_TCOL_OLD_EN_ALIGN          0
#define XGXSBLK0_XGMIITCONTROL_TX_XGMII_TCOL_OLD_EN_BITS           1
#define XGXSBLK0_XGMIITCONTROL_TX_XGMII_TCOL_OLD_EN_SHIFT          5

/* XgxsBlk0 :: xgmiiTcontrol :: tx_force_dpath_IorRF_en [04:04] */
#define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_IORRF_EN_MASK        0x0010
#define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_IORRF_EN_ALIGN       0
#define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_IORRF_EN_BITS        1
#define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_IORRF_EN_SHIFT       4

/* XgxsBlk0 :: xgmiiTcontrol :: tx_force_dpath_I_en [03:03] */
#define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_I_EN_MASK            0x0008
#define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_I_EN_ALIGN           0
#define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_I_EN_BITS            1
#define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_I_EN_SHIFT           3

/* XgxsBlk0 :: xgmiiTcontrol :: reserved1 [02:00] */
#define XGXSBLK0_XGMIITCONTROL_RESERVED1_MASK                      0x0007
#define XGXSBLK0_XGMIITCONTROL_RESERVED1_ALIGN                     0
#define XGXSBLK0_XGMIITCONTROL_RESERVED1_BITS                      3
#define XGXSBLK0_XGMIITCONTROL_RESERVED1_SHIFT                     0


/****************************************************************************
 * XgxsBlk0 :: xgmiiSwap
 ***************************************************************************/
/* XgxsBlk0 :: xgmiiSwap :: swap_count [15:00] */
#define XGXSBLK0_XGMIISWAP_SWAP_COUNT_MASK                         0xffff
#define XGXSBLK0_XGMIISWAP_SWAP_COUNT_ALIGN                        0
#define XGXSBLK0_XGMIISWAP_SWAP_COUNT_BITS                         16
#define XGXSBLK0_XGMIISWAP_SWAP_COUNT_SHIFT                        0


/****************************************************************************
 * XgxsBlk0 :: lssLsid
 ***************************************************************************/
/* XgxsBlk0 :: lssLsid :: lss_ls_id [15:08] */
#define XGXSBLK0_LSSLSID_LSS_LS_ID_MASK                            0xff00
#define XGXSBLK0_LSSLSID_LSS_LS_ID_ALIGN                           0
#define XGXSBLK0_LSSLSID_LSS_LS_ID_BITS                            8
#define XGXSBLK0_LSSLSID_LSS_LS_ID_SHIFT                           8

/* XgxsBlk0 :: lssLsid :: lss_domain_id [07:00] */
#define XGXSBLK0_LSSLSID_LSS_DOMAIN_ID_MASK                        0x00ff
#define XGXSBLK0_LSSLSID_LSS_DOMAIN_ID_ALIGN                       0
#define XGXSBLK0_LSSLSID_LSS_DOMAIN_ID_BITS                        8
#define XGXSBLK0_LSSLSID_LSS_DOMAIN_ID_SHIFT                       0


/****************************************************************************
 * XgxsBlk0 :: lssTinfo
 ***************************************************************************/
/* XgxsBlk0 :: lssTinfo :: lss_function_id [15:08] */
#define XGXSBLK0_LSSTINFO_LSS_FUNCTION_ID_MASK                     0xff00
#define XGXSBLK0_LSSTINFO_LSS_FUNCTION_ID_ALIGN                    0
#define XGXSBLK0_LSSTINFO_LSS_FUNCTION_ID_BITS                     8
#define XGXSBLK0_LSSTINFO_LSS_FUNCTION_ID_SHIFT                    8

/* XgxsBlk0 :: lssTinfo :: lssL_info_byte [07:00] */
#define XGXSBLK0_LSSTINFO_LSSL_INFO_BYTE_MASK                      0x00ff
#define XGXSBLK0_LSSTINFO_LSSL_INFO_BYTE_ALIGN                     0
#define XGXSBLK0_LSSTINFO_LSSL_INFO_BYTE_BITS                      8
#define XGXSBLK0_LSSTINFO_LSSL_INFO_BYTE_SHIFT                     0


/****************************************************************************
 * XgxsBlk0 :: lssRinfo
 ***************************************************************************/
/* XgxsBlk0 :: lssRinfo :: control_en [15:15] */
#define XGXSBLK0_LSSRINFO_CONTROL_EN_MASK                          0x8000
#define XGXSBLK0_LSSRINFO_CONTROL_EN_ALIGN                         0
#define XGXSBLK0_LSSRINFO_CONTROL_EN_BITS                          1
#define XGXSBLK0_LSSRINFO_CONTROL_EN_SHIFT                         15

/* XgxsBlk0 :: lssRinfo :: reserved0 [14:14] */
#define XGXSBLK0_LSSRINFO_RESERVED0_MASK                           0x4000
#define XGXSBLK0_LSSRINFO_RESERVED0_ALIGN                          0
#define XGXSBLK0_LSSRINFO_RESERVED0_BITS                           1
#define XGXSBLK0_LSSRINFO_RESERVED0_SHIFT                          14

/* XgxsBlk0 :: lssRinfo :: lss_ls_id8 [13:13] */
#define XGXSBLK0_LSSRINFO_LSS_LS_ID8_MASK                          0x2000
#define XGXSBLK0_LSSRINFO_LSS_LS_ID8_ALIGN                         0
#define XGXSBLK0_LSSRINFO_LSS_LS_ID8_BITS                          1
#define XGXSBLK0_LSSRINFO_LSS_LS_ID8_SHIFT                         13

/* XgxsBlk0 :: lssRinfo :: lss_domain_id8 [12:12] */
#define XGXSBLK0_LSSRINFO_LSS_DOMAIN_ID8_MASK                      0x1000
#define XGXSBLK0_LSSRINFO_LSS_DOMAIN_ID8_ALIGN                     0
#define XGXSBLK0_LSSRINFO_LSS_DOMAIN_ID8_BITS                      1
#define XGXSBLK0_LSSRINFO_LSS_DOMAIN_ID8_SHIFT                     12

/* XgxsBlk0 :: lssRinfo :: lss_function_id8 [11:11] */
#define XGXSBLK0_LSSRINFO_LSS_FUNCTION_ID8_MASK                    0x0800
#define XGXSBLK0_LSSRINFO_LSS_FUNCTION_ID8_ALIGN                   0
#define XGXSBLK0_LSSRINFO_LSS_FUNCTION_ID8_BITS                    1
#define XGXSBLK0_LSSRINFO_LSS_FUNCTION_ID8_SHIFT                   11

/* XgxsBlk0 :: lssRinfo :: lssL_info_byte8 [10:10] */
#define XGXSBLK0_LSSRINFO_LSSL_INFO_BYTE8_MASK                     0x0400
#define XGXSBLK0_LSSRINFO_LSSL_INFO_BYTE8_ALIGN                    0
#define XGXSBLK0_LSSRINFO_LSSL_INFO_BYTE8_BITS                     1
#define XGXSBLK0_LSSRINFO_LSSL_INFO_BYTE8_SHIFT                    10

/* XgxsBlk0 :: lssRinfo :: reserved1 [09:09] */
#define XGXSBLK0_LSSRINFO_RESERVED1_MASK                           0x0200
#define XGXSBLK0_LSSRINFO_RESERVED1_ALIGN                          0
#define XGXSBLK0_LSSRINFO_RESERVED1_BITS                           1
#define XGXSBLK0_LSSRINFO_RESERVED1_SHIFT                          9

/* XgxsBlk0 :: lssRinfo :: lssR_info_byte [08:00] */
#define XGXSBLK0_LSSRINFO_LSSR_INFO_BYTE_MASK                      0x01ff
#define XGXSBLK0_LSSRINFO_LSSR_INFO_BYTE_ALIGN                     0
#define XGXSBLK0_LSSRINFO_LSSR_INFO_BYTE_BITS                      9
#define XGXSBLK0_LSSRINFO_LSSR_INFO_BYTE_SHIFT                     0


/****************************************************************************
 * XgxsBlk0 :: mmdSelect
 ***************************************************************************/
/* XgxsBlk0 :: mmdSelect :: multiPRTs_en [15:15] */
#define XGXSBLK0_MMDSELECT_MULTIPRTS_EN_MASK                       0x8000
#define XGXSBLK0_MMDSELECT_MULTIPRTS_EN_ALIGN                      0
#define XGXSBLK0_MMDSELECT_MULTIPRTS_EN_BITS                       1
#define XGXSBLK0_MMDSELECT_MULTIPRTS_EN_SHIFT                      15

/* XgxsBlk0 :: mmdSelect :: multiMMDs_en [14:14] */
#define XGXSBLK0_MMDSELECT_MULTIMMDS_EN_MASK                       0x4000
#define XGXSBLK0_MMDSELECT_MULTIMMDS_EN_ALIGN                      0
#define XGXSBLK0_MMDSELECT_MULTIMMDS_EN_BITS                       1
#define XGXSBLK0_MMDSELECT_MULTIMMDS_EN_SHIFT                      14

/* XgxsBlk0 :: mmdSelect :: reserved0 [13:04] */
#define XGXSBLK0_MMDSELECT_RESERVED0_MASK                          0x3ff0
#define XGXSBLK0_MMDSELECT_RESERVED0_ALIGN                         0
#define XGXSBLK0_MMDSELECT_RESERVED0_BITS                          10
#define XGXSBLK0_MMDSELECT_RESERVED0_SHIFT                         4

/* XgxsBlk0 :: mmdSelect :: devAN_en [03:03] */
#define XGXSBLK0_MMDSELECT_DEVAN_EN_MASK                           0x0008
#define XGXSBLK0_MMDSELECT_DEVAN_EN_ALIGN                          0
#define XGXSBLK0_MMDSELECT_DEVAN_EN_BITS                           1
#define XGXSBLK0_MMDSELECT_DEVAN_EN_SHIFT                          3

/* XgxsBlk0 :: mmdSelect :: devPMD_en [02:02] */
#define XGXSBLK0_MMDSELECT_DEVPMD_EN_MASK                          0x0004
#define XGXSBLK0_MMDSELECT_DEVPMD_EN_ALIGN                         0
#define XGXSBLK0_MMDSELECT_DEVPMD_EN_BITS                          1
#define XGXSBLK0_MMDSELECT_DEVPMD_EN_SHIFT                         2

/* XgxsBlk0 :: mmdSelect :: devDEVAD_en [01:01] */
#define XGXSBLK0_MMDSELECT_DEVDEVAD_EN_MASK                        0x0002
#define XGXSBLK0_MMDSELECT_DEVDEVAD_EN_ALIGN                       0
#define XGXSBLK0_MMDSELECT_DEVDEVAD_EN_BITS                        1
#define XGXSBLK0_MMDSELECT_DEVDEVAD_EN_SHIFT                       1

/* XgxsBlk0 :: mmdSelect :: devCL22_en [00:00] */
#define XGXSBLK0_MMDSELECT_DEVCL22_EN_MASK                         0x0001
#define XGXSBLK0_MMDSELECT_DEVCL22_EN_ALIGN                        0
#define XGXSBLK0_MMDSELECT_DEVCL22_EN_BITS                         1
#define XGXSBLK0_MMDSELECT_DEVCL22_EN_SHIFT                        0


/****************************************************************************
 * XgxsBlk0 :: miscControl1
 ***************************************************************************/
/* XgxsBlk0 :: miscControl1 :: PMD_Lane3_tx_disable [15:15] */
#define XGXSBLK0_MISCCONTROL1_PMD_LANE3_TX_DISABLE_MASK            0x8000
#define XGXSBLK0_MISCCONTROL1_PMD_LANE3_TX_DISABLE_ALIGN           0
#define XGXSBLK0_MISCCONTROL1_PMD_LANE3_TX_DISABLE_BITS            1
#define XGXSBLK0_MISCCONTROL1_PMD_LANE3_TX_DISABLE_SHIFT           15

/* XgxsBlk0 :: miscControl1 :: PMD_Lane2_tx_disable [14:14] */
#define XGXSBLK0_MISCCONTROL1_PMD_LANE2_TX_DISABLE_MASK            0x4000
#define XGXSBLK0_MISCCONTROL1_PMD_LANE2_TX_DISABLE_ALIGN           0
#define XGXSBLK0_MISCCONTROL1_PMD_LANE2_TX_DISABLE_BITS            1
#define XGXSBLK0_MISCCONTROL1_PMD_LANE2_TX_DISABLE_SHIFT           14

/* XgxsBlk0 :: miscControl1 :: PMD_Lane1_tx_disable [13:13] */
#define XGXSBLK0_MISCCONTROL1_PMD_LANE1_TX_DISABLE_MASK            0x2000
#define XGXSBLK0_MISCCONTROL1_PMD_LANE1_TX_DISABLE_ALIGN           0
#define XGXSBLK0_MISCCONTROL1_PMD_LANE1_TX_DISABLE_BITS            1
#define XGXSBLK0_MISCCONTROL1_PMD_LANE1_TX_DISABLE_SHIFT           13

/* XgxsBlk0 :: miscControl1 :: PMD_Lane0_tx_disable [12:12] */
#define XGXSBLK0_MISCCONTROL1_PMD_LANE0_TX_DISABLE_MASK            0x1000
#define XGXSBLK0_MISCCONTROL1_PMD_LANE0_TX_DISABLE_ALIGN           0
#define XGXSBLK0_MISCCONTROL1_PMD_LANE0_TX_DISABLE_BITS            1
#define XGXSBLK0_MISCCONTROL1_PMD_LANE0_TX_DISABLE_SHIFT           12

/* XgxsBlk0 :: miscControl1 :: Global_PMD_tx_disable [11:11] */
#define XGXSBLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_MASK           0x0800
#define XGXSBLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_ALIGN          0
#define XGXSBLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_BITS           1
#define XGXSBLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_SHIFT          11

/* XgxsBlk0 :: miscControl1 :: PCS_dev_en_override [10:10] */
#define XGXSBLK0_MISCCONTROL1_PCS_DEV_EN_OVERRIDE_MASK             0x0400
#define XGXSBLK0_MISCCONTROL1_PCS_DEV_EN_OVERRIDE_ALIGN            0
#define XGXSBLK0_MISCCONTROL1_PCS_DEV_EN_OVERRIDE_BITS             1
#define XGXSBLK0_MISCCONTROL1_PCS_DEV_EN_OVERRIDE_SHIFT            10

/* XgxsBlk0 :: miscControl1 :: PMD_dev_en_override [09:09] */
#define XGXSBLK0_MISCCONTROL1_PMD_DEV_EN_OVERRIDE_MASK             0x0200
#define XGXSBLK0_MISCCONTROL1_PMD_DEV_EN_OVERRIDE_ALIGN            0
#define XGXSBLK0_MISCCONTROL1_PMD_DEV_EN_OVERRIDE_BITS             1
#define XGXSBLK0_MISCCONTROL1_PMD_DEV_EN_OVERRIDE_SHIFT            9

/* XgxsBlk0 :: miscControl1 :: reserved0 [08:08] */
#define XGXSBLK0_MISCCONTROL1_RESERVED0_MASK                       0x0100
#define XGXSBLK0_MISCCONTROL1_RESERVED0_ALIGN                      0
#define XGXSBLK0_MISCCONTROL1_RESERVED0_BITS                       1
#define XGXSBLK0_MISCCONTROL1_RESERVED0_SHIFT                      8

/* XgxsBlk0 :: miscControl1 :: clear_linkdown [07:07] */
#define XGXSBLK0_MISCCONTROL1_CLEAR_LINKDOWN_MASK                  0x0080
#define XGXSBLK0_MISCCONTROL1_CLEAR_LINKDOWN_ALIGN                 0
#define XGXSBLK0_MISCCONTROL1_CLEAR_LINKDOWN_BITS                  1
#define XGXSBLK0_MISCCONTROL1_CLEAR_LINKDOWN_SHIFT                 7

/* XgxsBlk0 :: miscControl1 :: latch_linkdown_enable [06:06] */
#define XGXSBLK0_MISCCONTROL1_LATCH_LINKDOWN_ENABLE_MASK           0x0040
#define XGXSBLK0_MISCCONTROL1_LATCH_LINKDOWN_ENABLE_ALIGN          0
#define XGXSBLK0_MISCCONTROL1_LATCH_LINKDOWN_ENABLE_BITS           1
#define XGXSBLK0_MISCCONTROL1_LATCH_LINKDOWN_ENABLE_SHIFT          6

/* XgxsBlk0 :: miscControl1 :: reserved1 [05:05] */
#define XGXSBLK0_MISCCONTROL1_RESERVED1_MASK                       0x0020
#define XGXSBLK0_MISCCONTROL1_RESERVED1_ALIGN                      0
#define XGXSBLK0_MISCCONTROL1_RESERVED1_BITS                       1
#define XGXSBLK0_MISCCONTROL1_RESERVED1_SHIFT                      5

/* XgxsBlk0 :: miscControl1 :: force_div5_for_lxck25 [04:04] */
#define XGXSBLK0_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_MASK           0x0010
#define XGXSBLK0_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_ALIGN          0
#define XGXSBLK0_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_BITS           1
#define XGXSBLK0_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_SHIFT          4

/* XgxsBlk0 :: miscControl1 :: pardet10g_pwrdnLink_en [03:03] */
#define XGXSBLK0_MISCCONTROL1_PARDET10G_PWRDNLINK_EN_MASK          0x0008
#define XGXSBLK0_MISCCONTROL1_PARDET10G_PWRDNLINK_EN_ALIGN         0
#define XGXSBLK0_MISCCONTROL1_PARDET10G_PWRDNLINK_EN_BITS          1
#define XGXSBLK0_MISCCONTROL1_PARDET10G_PWRDNLINK_EN_SHIFT         3

/* XgxsBlk0 :: miscControl1 :: invert_rx_sigdet [02:02] */
#define XGXSBLK0_MISCCONTROL1_INVERT_RX_SIGDET_MASK                0x0004
#define XGXSBLK0_MISCCONTROL1_INVERT_RX_SIGDET_ALIGN               0
#define XGXSBLK0_MISCCONTROL1_INVERT_RX_SIGDET_BITS                1
#define XGXSBLK0_MISCCONTROL1_INVERT_RX_SIGDET_SHIFT               2

/* XgxsBlk0 :: miscControl1 :: ieee_blksel_autodet [01:01] */
#define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_AUTODET_MASK             0x0002
#define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_AUTODET_ALIGN            0
#define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_AUTODET_BITS             1
#define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_AUTODET_SHIFT            1

/* XgxsBlk0 :: miscControl1 :: ieee_blksel_val [00:00] */
#define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_VAL_MASK                 0x0001
#define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_VAL_ALIGN                0
#define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_VAL_BITS                 1
#define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_VAL_SHIFT                0


/****************************************************************************
 * XgxsBlk0 :: BlockAddress
 ***************************************************************************/
/* XgxsBlk0 :: BlockAddress :: reserved0 [15:15] */
#define XGXSBLK0_BLOCKADDRESS_RESERVED0_MASK                       0x8000
#define XGXSBLK0_BLOCKADDRESS_RESERVED0_ALIGN                      0
#define XGXSBLK0_BLOCKADDRESS_RESERVED0_BITS                       1
#define XGXSBLK0_BLOCKADDRESS_RESERVED0_SHIFT                      15

/* XgxsBlk0 :: BlockAddress :: BlockAddress [14:04] */
#define XGXSBLK0_BLOCKADDRESS_BLOCKADDRESS_MASK                    0x7ff0
#define XGXSBLK0_BLOCKADDRESS_BLOCKADDRESS_ALIGN                   0
#define XGXSBLK0_BLOCKADDRESS_BLOCKADDRESS_BITS                    11
#define XGXSBLK0_BLOCKADDRESS_BLOCKADDRESS_SHIFT                   4

/* XgxsBlk0 :: BlockAddress :: reserved1 [03:00] */
#define XGXSBLK0_BLOCKADDRESS_RESERVED1_MASK                       0x000f
#define XGXSBLK0_BLOCKADDRESS_RESERVED1_ALIGN                      0
#define XGXSBLK0_BLOCKADDRESS_RESERVED1_BITS                       4
#define XGXSBLK0_BLOCKADDRESS_RESERVED1_SHIFT                      0


/****************************************************************************
 * XGXS16G_USER_XgxsBlk1
 ***************************************************************************/
/****************************************************************************
 * XgxsBlk1 :: deskew
 ***************************************************************************/
/* XgxsBlk1 :: deskew :: link_en [15:15] */
#define XGXSBLK1_DESKEW_LINK_EN_MASK                               0x8000
#define XGXSBLK1_DESKEW_LINK_EN_ALIGN                              0
#define XGXSBLK1_DESKEW_LINK_EN_BITS                               1
#define XGXSBLK1_DESKEW_LINK_EN_SHIFT                              15

/* XgxsBlk1 :: deskew :: deskew_hyst_en [14:14] */
#define XGXSBLK1_DESKEW_DESKEW_HYST_EN_MASK                        0x4000
#define XGXSBLK1_DESKEW_DESKEW_HYST_EN_ALIGN                       0
#define XGXSBLK1_DESKEW_DESKEW_HYST_EN_BITS                        1
#define XGXSBLK1_DESKEW_DESKEW_HYST_EN_SHIFT                       14

/* XgxsBlk1 :: deskew :: dswin [13:09] */
#define XGXSBLK1_DESKEW_DSWIN_MASK                                 0x3e00
#define XGXSBLK1_DESKEW_DSWIN_ALIGN                                0
#define XGXSBLK1_DESKEW_DSWIN_BITS                                 5
#define XGXSBLK1_DESKEW_DSWIN_SHIFT                                9

/* XgxsBlk1 :: deskew :: mpwin [08:00] */
#define XGXSBLK1_DESKEW_MPWIN_MASK                                 0x01ff
#define XGXSBLK1_DESKEW_MPWIN_ALIGN                                0
#define XGXSBLK1_DESKEW_MPWIN_BITS                                 9
#define XGXSBLK1_DESKEW_MPWIN_SHIFT                                0


/****************************************************************************
 * XgxsBlk1 :: link
 ***************************************************************************/
/* XgxsBlk1 :: link :: Acolwin [15:00] */
#define XGXSBLK1_LINK_ACOLWIN_MASK                                 0xffff
#define XGXSBLK1_LINK_ACOLWIN_ALIGN                                0
#define XGXSBLK1_LINK_ACOLWIN_BITS                                 16
#define XGXSBLK1_LINK_ACOLWIN_SHIFT                                0


/****************************************************************************
 * XgxsBlk1 :: testRx
 ***************************************************************************/
/* XgxsBlk1 :: testRx :: reserved0 [15:08] */
#define XGXSBLK1_TESTRX_RESERVED0_MASK                             0xff00
#define XGXSBLK1_TESTRX_RESERVED0_ALIGN                            0
#define XGXSBLK1_TESTRX_RESERVED0_BITS                             8
#define XGXSBLK1_TESTRX_RESERVED0_SHIFT                            8

/* XgxsBlk1 :: testRx :: rx_inBandMdio_Qfltr_en [07:07] */
#define XGXSBLK1_TESTRX_RX_INBANDMDIO_QFLTR_EN_MASK                0x0080
#define XGXSBLK1_TESTRX_RX_INBANDMDIO_QFLTR_EN_ALIGN               0
#define XGXSBLK1_TESTRX_RX_INBANDMDIO_QFLTR_EN_BITS                1
#define XGXSBLK1_TESTRX_RX_INBANDMDIO_QFLTR_EN_SHIFT               7

/* XgxsBlk1 :: testRx :: link_force [06:06] */
#define XGXSBLK1_TESTRX_LINK_FORCE_MASK                            0x0040
#define XGXSBLK1_TESTRX_LINK_FORCE_ALIGN                           0
#define XGXSBLK1_TESTRX_LINK_FORCE_BITS                            1
#define XGXSBLK1_TESTRX_LINK_FORCE_SHIFT                           6

/* XgxsBlk1 :: testRx :: rxtm_modsel [05:03] */
#define XGXSBLK1_TESTRX_RXTM_MODSEL_MASK                           0x0038
#define XGXSBLK1_TESTRX_RXTM_MODSEL_ALIGN                          0
#define XGXSBLK1_TESTRX_RXTM_MODSEL_BITS                           3
#define XGXSBLK1_TESTRX_RXTM_MODSEL_SHIFT                          3

/* XgxsBlk1 :: testRx :: rxtm_tstsel [02:00] */
#define XGXSBLK1_TESTRX_RXTM_TSTSEL_MASK                           0x0007
#define XGXSBLK1_TESTRX_RXTM_TSTSEL_ALIGN                          0
#define XGXSBLK1_TESTRX_RXTM_TSTSEL_BITS                           3
#define XGXSBLK1_TESTRX_RXTM_TSTSEL_SHIFT                          0


/****************************************************************************
 * XgxsBlk1 :: testTx
 ***************************************************************************/
/* XgxsBlk1 :: testTx :: reserved0 [15:08] */
#define XGXSBLK1_TESTTX_RESERVED0_MASK                             0xff00
#define XGXSBLK1_TESTTX_RESERVED0_ALIGN                            0
#define XGXSBLK1_TESTTX_RESERVED0_BITS                             8
#define XGXSBLK1_TESTTX_RESERVED0_SHIFT                            8

/* XgxsBlk1 :: testTx :: rx_ck4x1muxsel [07:06] */
#define XGXSBLK1_TESTTX_RX_CK4X1MUXSEL_MASK                        0x00c0
#define XGXSBLK1_TESTTX_RX_CK4X1MUXSEL_ALIGN                       0
#define XGXSBLK1_TESTTX_RX_CK4X1MUXSEL_BITS                        2
#define XGXSBLK1_TESTTX_RX_CK4X1MUXSEL_SHIFT                       6

/* XgxsBlk1 :: testTx :: txtm_modsel [05:03] */
#define XGXSBLK1_TESTTX_TXTM_MODSEL_MASK                           0x0038
#define XGXSBLK1_TESTTX_TXTM_MODSEL_ALIGN                          0
#define XGXSBLK1_TESTTX_TXTM_MODSEL_BITS                           3
#define XGXSBLK1_TESTTX_TXTM_MODSEL_SHIFT                          3

/* XgxsBlk1 :: testTx :: txtm_tstsel [02:00] */
#define XGXSBLK1_TESTTX_TXTM_TSTSEL_MASK                           0x0007
#define XGXSBLK1_TESTTX_TXTM_TSTSEL_ALIGN                          0
#define XGXSBLK1_TESTTX_TXTM_TSTSEL_BITS                           3
#define XGXSBLK1_TESTTX_TXTM_TSTSEL_SHIFT                          0


/****************************************************************************
 * XgxsBlk1 :: testXg
 ***************************************************************************/
/* XgxsBlk1 :: testXg :: evnt_cntr_sel [15:15] */
#define XGXSBLK1_TESTXG_EVNT_CNTR_SEL_MASK                         0x8000
#define XGXSBLK1_TESTXG_EVNT_CNTR_SEL_ALIGN                        0
#define XGXSBLK1_TESTXG_EVNT_CNTR_SEL_BITS                         1
#define XGXSBLK1_TESTXG_EVNT_CNTR_SEL_SHIFT                        15

/* XgxsBlk1 :: testXg :: txdt_sel [14:14] */
#define XGXSBLK1_TESTXG_TXDT_SEL_MASK                              0x4000
#define XGXSBLK1_TESTXG_TXDT_SEL_ALIGN                             0
#define XGXSBLK1_TESTXG_TXDT_SEL_BITS                              1
#define XGXSBLK1_TESTXG_TXDT_SEL_SHIFT                             14

/* XgxsBlk1 :: testXg :: slice_sel [13:12] */
#define XGXSBLK1_TESTXG_SLICE_SEL_MASK                             0x3000
#define XGXSBLK1_TESTXG_SLICE_SEL_ALIGN                            0
#define XGXSBLK1_TESTXG_SLICE_SEL_BITS                             2
#define XGXSBLK1_TESTXG_SLICE_SEL_SHIFT                            12

/* XgxsBlk1 :: testXg :: reserved0 [11:08] */
#define XGXSBLK1_TESTXG_RESERVED0_MASK                             0x0f00
#define XGXSBLK1_TESTXG_RESERVED0_ALIGN                            0
#define XGXSBLK1_TESTXG_RESERVED0_BITS                             4
#define XGXSBLK1_TESTXG_RESERVED0_SHIFT                            8

/* XgxsBlk1 :: testXg :: test_reg_sel [07:07] */
#define XGXSBLK1_TESTXG_TEST_REG_SEL_MASK                          0x0080
#define XGXSBLK1_TESTXG_TEST_REG_SEL_ALIGN                         0
#define XGXSBLK1_TESTXG_TEST_REG_SEL_BITS                          1
#define XGXSBLK1_TESTXG_TEST_REG_SEL_SHIFT                         7

/* XgxsBlk1 :: testXg :: xg_txtstsel [06:04] */
#define XGXSBLK1_TESTXG_XG_TXTSTSEL_MASK                           0x0070
#define XGXSBLK1_TESTXG_XG_TXTSTSEL_ALIGN                          0
#define XGXSBLK1_TESTXG_XG_TXTSTSEL_BITS                           3
#define XGXSBLK1_TESTXG_XG_TXTSTSEL_SHIFT                          4

/* XgxsBlk1 :: testXg :: xg_rxtstsel [03:00] */
#define XGXSBLK1_TESTXG_XG_RXTSTSEL_MASK                           0x000f
#define XGXSBLK1_TESTXG_XG_RXTSTSEL_ALIGN                          0
#define XGXSBLK1_TESTXG_XG_RXTSTSEL_BITS                           4
#define XGXSBLK1_TESTXG_XG_RXTSTSEL_SHIFT                          0


/****************************************************************************
 * XgxsBlk1 :: laneCtrl0
 ***************************************************************************/
/* XgxsBlk1 :: laneCtrl0 :: ed66en [15:12] */
#define XGXSBLK1_LANECTRL0_ED66EN_MASK                             0xf000
#define XGXSBLK1_LANECTRL0_ED66EN_ALIGN                            0
#define XGXSBLK1_LANECTRL0_ED66EN_BITS                             4
#define XGXSBLK1_LANECTRL0_ED66EN_SHIFT                            12

/* XgxsBlk1 :: laneCtrl0 :: reserved0 [11:08] */
#define XGXSBLK1_LANECTRL0_RESERVED0_MASK                          0x0f00
#define XGXSBLK1_LANECTRL0_RESERVED0_ALIGN                         0
#define XGXSBLK1_LANECTRL0_RESERVED0_BITS                          4
#define XGXSBLK1_LANECTRL0_RESERVED0_SHIFT                         8

/* XgxsBlk1 :: laneCtrl0 :: cl36_pcs_en_rx [07:04] */
#define XGXSBLK1_LANECTRL0_CL36_PCS_EN_RX_MASK                     0x00f0
#define XGXSBLK1_LANECTRL0_CL36_PCS_EN_RX_ALIGN                    0
#define XGXSBLK1_LANECTRL0_CL36_PCS_EN_RX_BITS                     4
#define XGXSBLK1_LANECTRL0_CL36_PCS_EN_RX_SHIFT                    4

/* XgxsBlk1 :: laneCtrl0 :: cl36_pcs_en_tx [03:00] */
#define XGXSBLK1_LANECTRL0_CL36_PCS_EN_TX_MASK                     0x000f
#define XGXSBLK1_LANECTRL0_CL36_PCS_EN_TX_ALIGN                    0
#define XGXSBLK1_LANECTRL0_CL36_PCS_EN_TX_BITS                     4
#define XGXSBLK1_LANECTRL0_CL36_PCS_EN_TX_SHIFT                    0


/****************************************************************************
 * XgxsBlk1 :: laneCtrl1
 ***************************************************************************/
/* XgxsBlk1 :: laneCtrl1 :: rx1g_mode_ln3 [15:14] */
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_MASK                      0xc000
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_ALIGN                     0
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_BITS                      2
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_SHIFT                     14

/* XgxsBlk1 :: laneCtrl1 :: rx1g_mode_ln2 [13:12] */
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_MASK                      0x3000
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_ALIGN                     0
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_BITS                      2
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_SHIFT                     12

/* XgxsBlk1 :: laneCtrl1 :: rx1g_mode_ln1 [11:10] */
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_MASK                      0x0c00
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_ALIGN                     0
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_BITS                      2
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_SHIFT                     10

/* XgxsBlk1 :: laneCtrl1 :: rx1g_mode_ln0 [09:08] */
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_MASK                      0x0300
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_ALIGN                     0
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_BITS                      2
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_SHIFT                     8

/* XgxsBlk1 :: laneCtrl1 :: tx1g_mode_ln3 [07:06] */
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_MASK                      0x00c0
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_ALIGN                     0
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_BITS                      2
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_SHIFT                     6

/* XgxsBlk1 :: laneCtrl1 :: tx1g_mode_ln2 [05:04] */
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_MASK                      0x0030
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_ALIGN                     0
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_BITS                      2
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_SHIFT                     4

/* XgxsBlk1 :: laneCtrl1 :: tx1g_mode_ln1 [03:02] */
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_MASK                      0x000c
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_ALIGN                     0
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_BITS                      2
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_SHIFT                     2

/* XgxsBlk1 :: laneCtrl1 :: tx1g_mode_ln0 [01:00] */
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_MASK                      0x0003
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_ALIGN                     0
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_BITS                      2
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_SHIFT                     0


/****************************************************************************
 * XgxsBlk1 :: laneCtrl2
 ***************************************************************************/
/* XgxsBlk1 :: laneCtrl2 :: cdet_en1g [15:12] */
#define XGXSBLK1_LANECTRL2_CDET_EN1G_MASK                          0xf000
#define XGXSBLK1_LANECTRL2_CDET_EN1G_ALIGN                         0
#define XGXSBLK1_LANECTRL2_CDET_EN1G_BITS                          4
#define XGXSBLK1_LANECTRL2_CDET_EN1G_SHIFT                         12

/* XgxsBlk1 :: laneCtrl2 :: eden1g [11:08] */
#define XGXSBLK1_LANECTRL2_EDEN1G_MASK                             0x0f00
#define XGXSBLK1_LANECTRL2_EDEN1G_ALIGN                            0
#define XGXSBLK1_LANECTRL2_EDEN1G_BITS                             4
#define XGXSBLK1_LANECTRL2_EDEN1G_SHIFT                            8

/* XgxsBlk1 :: laneCtrl2 :: rloop1g [07:04] */
#define XGXSBLK1_LANECTRL2_RLOOP1G_MASK                            0x00f0
#define XGXSBLK1_LANECTRL2_RLOOP1G_ALIGN                           0
#define XGXSBLK1_LANECTRL2_RLOOP1G_BITS                            4
#define XGXSBLK1_LANECTRL2_RLOOP1G_SHIFT                           4

/* XgxsBlk1 :: laneCtrl2 :: gloop1g [03:00] */
#define XGXSBLK1_LANECTRL2_GLOOP1G_MASK                            0x000f
#define XGXSBLK1_LANECTRL2_GLOOP1G_ALIGN                           0
#define XGXSBLK1_LANECTRL2_GLOOP1G_BITS                            4
#define XGXSBLK1_LANECTRL2_GLOOP1G_SHIFT                           0


/****************************************************************************
 * XgxsBlk1 :: laneCtrl3
 ***************************************************************************/
/* XgxsBlk1 :: laneCtrl3 :: lock_ref [15:12] */
#define XGXSBLK1_LANECTRL3_LOCK_REF_MASK                           0xf000
#define XGXSBLK1_LANECTRL3_LOCK_REF_ALIGN                          0
#define XGXSBLK1_LANECTRL3_LOCK_REF_BITS                           4
#define XGXSBLK1_LANECTRL3_LOCK_REF_SHIFT                          12

/* XgxsBlk1 :: laneCtrl3 :: pwrdwn_force [11:11] */
#define XGXSBLK1_LANECTRL3_PWRDWN_FORCE_MASK                       0x0800
#define XGXSBLK1_LANECTRL3_PWRDWN_FORCE_ALIGN                      0
#define XGXSBLK1_LANECTRL3_PWRDWN_FORCE_BITS                       1
#define XGXSBLK1_LANECTRL3_PWRDWN_FORCE_SHIFT                      11

/* XgxsBlk1 :: laneCtrl3 :: lock_ref_en [10:10] */
#define XGXSBLK1_LANECTRL3_LOCK_REF_EN_MASK                        0x0400
#define XGXSBLK1_LANECTRL3_LOCK_REF_EN_ALIGN                       0
#define XGXSBLK1_LANECTRL3_LOCK_REF_EN_BITS                        1
#define XGXSBLK1_LANECTRL3_LOCK_REF_EN_SHIFT                       10

/* XgxsBlk1 :: laneCtrl3 :: pwrdwn10g_pll_dis [09:09] */
#define XGXSBLK1_LANECTRL3_PWRDWN10G_PLL_DIS_MASK                  0x0200
#define XGXSBLK1_LANECTRL3_PWRDWN10G_PLL_DIS_ALIGN                 0
#define XGXSBLK1_LANECTRL3_PWRDWN10G_PLL_DIS_BITS                  1
#define XGXSBLK1_LANECTRL3_PWRDWN10G_PLL_DIS_SHIFT                 9

/* XgxsBlk1 :: laneCtrl3 :: pwrdwn_pll [08:08] */
#define XGXSBLK1_LANECTRL3_PWRDWN_PLL_MASK                         0x0100
#define XGXSBLK1_LANECTRL3_PWRDWN_PLL_ALIGN                        0
#define XGXSBLK1_LANECTRL3_PWRDWN_PLL_BITS                         1
#define XGXSBLK1_LANECTRL3_PWRDWN_PLL_SHIFT                        8

/* XgxsBlk1 :: laneCtrl3 :: pwrdn_tx [07:04] */
#define XGXSBLK1_LANECTRL3_PWRDN_TX_MASK                           0x00f0
#define XGXSBLK1_LANECTRL3_PWRDN_TX_ALIGN                          0
#define XGXSBLK1_LANECTRL3_PWRDN_TX_BITS                           4
#define XGXSBLK1_LANECTRL3_PWRDN_TX_SHIFT                          4

/* XgxsBlk1 :: laneCtrl3 :: pwrdn_rx [03:00] */
#define XGXSBLK1_LANECTRL3_PWRDN_RX_MASK                           0x000f
#define XGXSBLK1_LANECTRL3_PWRDN_RX_ALIGN                          0
#define XGXSBLK1_LANECTRL3_PWRDN_RX_BITS                           4
#define XGXSBLK1_LANECTRL3_PWRDN_RX_SHIFT                          0


/****************************************************************************
 * XgxsBlk1 :: lanePrbs
 ***************************************************************************/
/* XgxsBlk1 :: lanePrbs :: prbs_en3 [15:15] */
#define XGXSBLK1_LANEPRBS_PRBS_EN3_MASK                            0x8000
#define XGXSBLK1_LANEPRBS_PRBS_EN3_ALIGN                           0
#define XGXSBLK1_LANEPRBS_PRBS_EN3_BITS                            1
#define XGXSBLK1_LANEPRBS_PRBS_EN3_SHIFT                           15

/* XgxsBlk1 :: lanePrbs :: prbs_inv3 [14:14] */
#define XGXSBLK1_LANEPRBS_PRBS_INV3_MASK                           0x4000
#define XGXSBLK1_LANEPRBS_PRBS_INV3_ALIGN                          0
#define XGXSBLK1_LANEPRBS_PRBS_INV3_BITS                           1
#define XGXSBLK1_LANEPRBS_PRBS_INV3_SHIFT                          14

/* XgxsBlk1 :: lanePrbs :: prbs_order3 [13:12] */
#define XGXSBLK1_LANEPRBS_PRBS_ORDER3_MASK                         0x3000
#define XGXSBLK1_LANEPRBS_PRBS_ORDER3_ALIGN                        0
#define XGXSBLK1_LANEPRBS_PRBS_ORDER3_BITS                         2
#define XGXSBLK1_LANEPRBS_PRBS_ORDER3_SHIFT                        12

/* XgxsBlk1 :: lanePrbs :: prbs_en2 [11:11] */
#define XGXSBLK1_LANEPRBS_PRBS_EN2_MASK                            0x0800
#define XGXSBLK1_LANEPRBS_PRBS_EN2_ALIGN                           0
#define XGXSBLK1_LANEPRBS_PRBS_EN2_BITS                            1
#define XGXSBLK1_LANEPRBS_PRBS_EN2_SHIFT                           11

/* XgxsBlk1 :: lanePrbs :: prbs_inv2 [10:10] */
#define XGXSBLK1_LANEPRBS_PRBS_INV2_MASK                           0x0400
#define XGXSBLK1_LANEPRBS_PRBS_INV2_ALIGN                          0
#define XGXSBLK1_LANEPRBS_PRBS_INV2_BITS                           1
#define XGXSBLK1_LANEPRBS_PRBS_INV2_SHIFT                          10

/* XgxsBlk1 :: lanePrbs :: prbs_order2 [09:08] */
#define XGXSBLK1_LANEPRBS_PRBS_ORDER2_MASK                         0x0300
#define XGXSBLK1_LANEPRBS_PRBS_ORDER2_ALIGN                        0
#define XGXSBLK1_LANEPRBS_PRBS_ORDER2_BITS                         2
#define XGXSBLK1_LANEPRBS_PRBS_ORDER2_SHIFT                        8

/* XgxsBlk1 :: lanePrbs :: prbs_en1 [07:07] */
#define XGXSBLK1_LANEPRBS_PRBS_EN1_MASK                            0x0080
#define XGXSBLK1_LANEPRBS_PRBS_EN1_ALIGN                           0
#define XGXSBLK1_LANEPRBS_PRBS_EN1_BITS                            1
#define XGXSBLK1_LANEPRBS_PRBS_EN1_SHIFT                           7

/* XgxsBlk1 :: lanePrbs :: prbs_inv1 [06:06] */
#define XGXSBLK1_LANEPRBS_PRBS_INV1_MASK                           0x0040
#define XGXSBLK1_LANEPRBS_PRBS_INV1_ALIGN                          0
#define XGXSBLK1_LANEPRBS_PRBS_INV1_BITS                           1
#define XGXSBLK1_LANEPRBS_PRBS_INV1_SHIFT                          6

/* XgxsBlk1 :: lanePrbs :: prbs_order1 [05:04] */
#define XGXSBLK1_LANEPRBS_PRBS_ORDER1_MASK                         0x0030
#define XGXSBLK1_LANEPRBS_PRBS_ORDER1_ALIGN                        0
#define XGXSBLK1_LANEPRBS_PRBS_ORDER1_BITS                         2
#define XGXSBLK1_LANEPRBS_PRBS_ORDER1_SHIFT                        4

/* XgxsBlk1 :: lanePrbs :: prbs_en0 [03:03] */
#define XGXSBLK1_LANEPRBS_PRBS_EN0_MASK                            0x0008
#define XGXSBLK1_LANEPRBS_PRBS_EN0_ALIGN                           0
#define XGXSBLK1_LANEPRBS_PRBS_EN0_BITS                            1
#define XGXSBLK1_LANEPRBS_PRBS_EN0_SHIFT                           3

/* XgxsBlk1 :: lanePrbs :: prbs_inv0 [02:02] */
#define XGXSBLK1_LANEPRBS_PRBS_INV0_MASK                           0x0004
#define XGXSBLK1_LANEPRBS_PRBS_INV0_ALIGN                          0
#define XGXSBLK1_LANEPRBS_PRBS_INV0_BITS                           1
#define XGXSBLK1_LANEPRBS_PRBS_INV0_SHIFT                          2

/* XgxsBlk1 :: lanePrbs :: prbs_order0 [01:00] */
#define XGXSBLK1_LANEPRBS_PRBS_ORDER0_MASK                         0x0003
#define XGXSBLK1_LANEPRBS_PRBS_ORDER0_ALIGN                        0
#define XGXSBLK1_LANEPRBS_PRBS_ORDER0_BITS                         2
#define XGXSBLK1_LANEPRBS_PRBS_ORDER0_SHIFT                        0


/****************************************************************************
 * XgxsBlk1 :: laneTest
 ***************************************************************************/
/* XgxsBlk1 :: laneTest :: tmux_sel [15:12] */
#define XGXSBLK1_LANETEST_TMUX_SEL_MASK                            0xf000
#define XGXSBLK1_LANETEST_TMUX_SEL_ALIGN                           0
#define XGXSBLK1_LANETEST_TMUX_SEL_BITS                            4
#define XGXSBLK1_LANETEST_TMUX_SEL_SHIFT                           12

/* XgxsBlk1 :: laneTest :: inBandMdioRxRstEn [11:11] */
#define XGXSBLK1_LANETEST_INBANDMDIORXRSTEN_MASK                   0x0800
#define XGXSBLK1_LANETEST_INBANDMDIORXRSTEN_ALIGN                  0
#define XGXSBLK1_LANETEST_INBANDMDIORXRSTEN_BITS                   1
#define XGXSBLK1_LANETEST_INBANDMDIORXRSTEN_SHIFT                  11

/* XgxsBlk1 :: laneTest :: pwrdn_ext_dis [10:10] */
#define XGXSBLK1_LANETEST_PWRDN_EXT_DIS_MASK                       0x0400
#define XGXSBLK1_LANETEST_PWRDN_EXT_DIS_ALIGN                      0
#define XGXSBLK1_LANETEST_PWRDN_EXT_DIS_BITS                       1
#define XGXSBLK1_LANETEST_PWRDN_EXT_DIS_SHIFT                      10

/* XgxsBlk1 :: laneTest :: pwrdn_safe_dis [09:09] */
#define XGXSBLK1_LANETEST_PWRDN_SAFE_DIS_MASK                      0x0200
#define XGXSBLK1_LANETEST_PWRDN_SAFE_DIS_ALIGN                     0
#define XGXSBLK1_LANETEST_PWRDN_SAFE_DIS_BITS                      1
#define XGXSBLK1_LANETEST_PWRDN_SAFE_DIS_SHIFT                     9

/* XgxsBlk1 :: laneTest :: pwrdwn_clks_en [08:08] */
#define XGXSBLK1_LANETEST_PWRDWN_CLKS_EN_MASK                      0x0100
#define XGXSBLK1_LANETEST_PWRDWN_CLKS_EN_ALIGN                     0
#define XGXSBLK1_LANETEST_PWRDWN_CLKS_EN_BITS                      1
#define XGXSBLK1_LANETEST_PWRDWN_CLKS_EN_SHIFT                     8

/* XgxsBlk1 :: laneTest :: rxSeqStart_ext_dis [07:07] */
#define XGXSBLK1_LANETEST_RXSEQSTART_EXT_DIS_MASK                  0x0080
#define XGXSBLK1_LANETEST_RXSEQSTART_EXT_DIS_ALIGN                 0
#define XGXSBLK1_LANETEST_RXSEQSTART_EXT_DIS_BITS                  1
#define XGXSBLK1_LANETEST_RXSEQSTART_EXT_DIS_SHIFT                 7

/* XgxsBlk1 :: laneTest :: pll_lock_rstb_r [06:06] */
#define XGXSBLK1_LANETEST_PLL_LOCK_RSTB_R_MASK                     0x0040
#define XGXSBLK1_LANETEST_PLL_LOCK_RSTB_R_ALIGN                    0
#define XGXSBLK1_LANETEST_PLL_LOCK_RSTB_R_BITS                     1
#define XGXSBLK1_LANETEST_PLL_LOCK_RSTB_R_SHIFT                    6

/* XgxsBlk1 :: laneTest :: lfck_bypass [05:05] */
#define XGXSBLK1_LANETEST_LFCK_BYPASS_MASK                         0x0020
#define XGXSBLK1_LANETEST_LFCK_BYPASS_ALIGN                        0
#define XGXSBLK1_LANETEST_LFCK_BYPASS_BITS                         1
#define XGXSBLK1_LANETEST_LFCK_BYPASS_SHIFT                        5

/* XgxsBlk1 :: laneTest :: rx_snoop_en [04:04] */
#define XGXSBLK1_LANETEST_RX_SNOOP_EN_MASK                         0x0010
#define XGXSBLK1_LANETEST_RX_SNOOP_EN_ALIGN                        0
#define XGXSBLK1_LANETEST_RX_SNOOP_EN_BITS                         1
#define XGXSBLK1_LANETEST_RX_SNOOP_EN_SHIFT                        4

/* XgxsBlk1 :: laneTest :: mode_10g_snoop [03:00] */
#define XGXSBLK1_LANETEST_MODE_10G_SNOOP_MASK                      0x000f
#define XGXSBLK1_LANETEST_MODE_10G_SNOOP_ALIGN                     0
#define XGXSBLK1_LANETEST_MODE_10G_SNOOP_BITS                      4
#define XGXSBLK1_LANETEST_MODE_10G_SNOOP_SHIFT                     0


/****************************************************************************
 * XgxsBlk1 :: lssRevnt
 ***************************************************************************/
/* XgxsBlk1 :: lssRevnt :: lssRevnt [15:00] */
#define XGXSBLK1_LSSREVNT_LSSREVNT_MASK                            0xffff
#define XGXSBLK1_LSSREVNT_LSSREVNT_ALIGN                           0
#define XGXSBLK1_LSSREVNT_LSSREVNT_BITS                            16
#define XGXSBLK1_LSSREVNT_LSSREVNT_SHIFT                           0


/****************************************************************************
 * XgxsBlk1 :: dskevnt
 ***************************************************************************/
/* XgxsBlk1 :: dskevnt :: dskevnt [15:00] */
#define XGXSBLK1_DSKEVNT_DSKEVNT_MASK                              0xffff
#define XGXSBLK1_DSKEVNT_DSKEVNT_ALIGN                             0
#define XGXSBLK1_DSKEVNT_DSKEVNT_BITS                              16
#define XGXSBLK1_DSKEVNT_DSKEVNT_SHIFT                             0


/****************************************************************************
 * XgxsBlk1 :: Aerrevnt
 ***************************************************************************/
/* XgxsBlk1 :: Aerrevnt :: Aerrevnt [15:00] */
#define XGXSBLK1_AERREVNT_AERREVNT_MASK                            0xffff
#define XGXSBLK1_AERREVNT_AERREVNT_ALIGN                           0
#define XGXSBLK1_AERREVNT_AERREVNT_BITS                            16
#define XGXSBLK1_AERREVNT_AERREVNT_SHIFT                           0


/****************************************************************************
 * XgxsBlk1 :: ckcmpevnt
 ***************************************************************************/
/* XgxsBlk1 :: ckcmpevnt :: ckcmpevnt [15:00] */
#define XGXSBLK1_CKCMPEVNT_CKCMPEVNT_MASK                          0xffff
#define XGXSBLK1_CKCMPEVNT_CKCMPEVNT_ALIGN                         0
#define XGXSBLK1_CKCMPEVNT_CKCMPEVNT_BITS                          16
#define XGXSBLK1_CKCMPEVNT_CKCMPEVNT_SHIFT                         0


/****************************************************************************
 * XGXS16G_USER_PLL
 ***************************************************************************/
/****************************************************************************
 * PLL :: pllStatus
 ***************************************************************************/
/* PLL :: pllStatus :: pllSeqDone [15:15] */
#define PLL_PLLSTATUS_PLLSEQDONE_MASK                              0x8000
#define PLL_PLLSTATUS_PLLSEQDONE_ALIGN                             0
#define PLL_PLLSTATUS_PLLSEQDONE_BITS                              1
#define PLL_PLLSTATUS_PLLSEQDONE_SHIFT                             15

/* PLL :: pllStatus :: freqDone [14:14] */
#define PLL_PLLSTATUS_FREQDONE_MASK                                0x4000
#define PLL_PLLSTATUS_FREQDONE_ALIGN                               0
#define PLL_PLLSTATUS_FREQDONE_BITS                                1
#define PLL_PLLSTATUS_FREQDONE_SHIFT                               14

/* PLL :: pllStatus :: capDone [13:13] */
#define PLL_PLLSTATUS_CAPDONE_MASK                                 0x2000
#define PLL_PLLSTATUS_CAPDONE_ALIGN                                0
#define PLL_PLLSTATUS_CAPDONE_BITS                                 1
#define PLL_PLLSTATUS_CAPDONE_SHIFT                                13

/* PLL :: pllStatus :: ampDone [12:12] */
#define PLL_PLLSTATUS_AMPDONE_MASK                                 0x1000
#define PLL_PLLSTATUS_AMPDONE_ALIGN                                0
#define PLL_PLLSTATUS_AMPDONE_BITS                                 1
#define PLL_PLLSTATUS_AMPDONE_SHIFT                                12

/* PLL :: pllStatus :: pllSeqPass [11:11] */
#define PLL_PLLSTATUS_PLLSEQPASS_MASK                              0x0800
#define PLL_PLLSTATUS_PLLSEQPASS_ALIGN                             0
#define PLL_PLLSTATUS_PLLSEQPASS_BITS                              1
#define PLL_PLLSTATUS_PLLSEQPASS_SHIFT                             11

/* PLL :: pllStatus :: freqPass [10:10] */
#define PLL_PLLSTATUS_FREQPASS_MASK                                0x0400
#define PLL_PLLSTATUS_FREQPASS_ALIGN                               0
#define PLL_PLLSTATUS_FREQPASS_BITS                                1
#define PLL_PLLSTATUS_FREQPASS_SHIFT                               10

/* PLL :: pllStatus :: capPass [09:09] */
#define PLL_PLLSTATUS_CAPPASS_MASK                                 0x0200
#define PLL_PLLSTATUS_CAPPASS_ALIGN                                0
#define PLL_PLLSTATUS_CAPPASS_BITS                                 1
#define PLL_PLLSTATUS_CAPPASS_SHIFT                                9

/* PLL :: pllStatus :: ampPass [08:08] */
#define PLL_PLLSTATUS_AMPPASS_MASK                                 0x0100
#define PLL_PLLSTATUS_AMPPASS_ALIGN                                0
#define PLL_PLLSTATUS_AMPPASS_BITS                                 1
#define PLL_PLLSTATUS_AMPPASS_SHIFT                                8

/* PLL :: pllStatus :: slowdn [07:07] */
#define PLL_PLLSTATUS_SLOWDN_MASK                                  0x0080
#define PLL_PLLSTATUS_SLOWDN_ALIGN                                 0
#define PLL_PLLSTATUS_SLOWDN_BITS                                  1
#define PLL_PLLSTATUS_SLOWDN_SHIFT                                 7

/* PLL :: pllStatus :: aboveVdd [06:06] */
#define PLL_PLLSTATUS_ABOVEVDD_MASK                                0x0040
#define PLL_PLLSTATUS_ABOVEVDD_ALIGN                               0
#define PLL_PLLSTATUS_ABOVEVDD_BITS                                1
#define PLL_PLLSTATUS_ABOVEVDD_SHIFT                               6

/* PLL :: pllStatus :: belowVss [05:05] */
#define PLL_PLLSTATUS_BELOWVSS_MASK                                0x0020
#define PLL_PLLSTATUS_BELOWVSS_ALIGN                               0
#define PLL_PLLSTATUS_BELOWVSS_BITS                                1
#define PLL_PLLSTATUS_BELOWVSS_SHIFT                               5

/* PLL :: pllStatus :: reserved0 [04:03] */
#define PLL_PLLSTATUS_RESERVED0_MASK                               0x0018
#define PLL_PLLSTATUS_RESERVED0_ALIGN                              0
#define PLL_PLLSTATUS_RESERVED0_BITS                               2
#define PLL_PLLSTATUS_RESERVED0_SHIFT                              3

/* PLL :: pllStatus :: pll_mode_afe [02:00] */
#define PLL_PLLSTATUS_PLL_MODE_AFE_MASK                            0x0007
#define PLL_PLLSTATUS_PLL_MODE_AFE_ALIGN                           0
#define PLL_PLLSTATUS_PLL_MODE_AFE_BITS                            3
#define PLL_PLLSTATUS_PLL_MODE_AFE_SHIFT                           0


/****************************************************************************
 * PLL :: pllControl
 ***************************************************************************/
/* PLL :: pllControl :: pllRestart [15:15] */
#define PLL_PLLCONTROL_PLLRESTART_MASK                             0x8000
#define PLL_PLLCONTROL_PLLRESTART_ALIGN                            0
#define PLL_PLLCONTROL_PLLRESTART_BITS                             1
#define PLL_PLLCONTROL_PLLRESTART_SHIFT                            15

/* PLL :: pllControl :: FreqDetRetry_en [14:14] */
#define PLL_PLLCONTROL_FREQDETRETRY_EN_MASK                        0x4000
#define PLL_PLLCONTROL_FREQDETRETRY_EN_ALIGN                       0
#define PLL_PLLCONTROL_FREQDETRETRY_EN_BITS                        1
#define PLL_PLLCONTROL_FREQDETRETRY_EN_SHIFT                       14

/* PLL :: pllControl :: FreqDetRestart_en [13:13] */
#define PLL_PLLCONTROL_FREQDETRESTART_EN_MASK                      0x2000
#define PLL_PLLCONTROL_FREQDETRESTART_EN_ALIGN                     0
#define PLL_PLLCONTROL_FREQDETRESTART_EN_BITS                      1
#define PLL_PLLCONTROL_FREQDETRESTART_EN_SHIFT                     13

/* PLL :: pllControl :: FreqMonitor_en [12:12] */
#define PLL_PLLCONTROL_FREQMONITOR_EN_MASK                         0x1000
#define PLL_PLLCONTROL_FREQMONITOR_EN_ALIGN                        0
#define PLL_PLLCONTROL_FREQMONITOR_EN_BITS                         1
#define PLL_PLLCONTROL_FREQMONITOR_EN_SHIFT                        12

/* PLL :: pllControl :: CapRetry_en [11:11] */
#define PLL_PLLCONTROL_CAPRETRY_EN_MASK                            0x0800
#define PLL_PLLCONTROL_CAPRETRY_EN_ALIGN                           0
#define PLL_PLLCONTROL_CAPRETRY_EN_BITS                            1
#define PLL_PLLCONTROL_CAPRETRY_EN_SHIFT                           11

/* PLL :: pllControl :: VcoDone_en [10:10] */
#define PLL_PLLCONTROL_VCODONE_EN_MASK                             0x0400
#define PLL_PLLCONTROL_VCODONE_EN_ALIGN                            0
#define PLL_PLLCONTROL_VCODONE_EN_BITS                             1
#define PLL_PLLCONTROL_VCODONE_EN_SHIFT                            10

/* PLL :: pllControl :: LinkRestart_en [09:09] */
#define PLL_PLLCONTROL_LINKRESTART_EN_MASK                         0x0200
#define PLL_PLLCONTROL_LINKRESTART_EN_ALIGN                        0
#define PLL_PLLCONTROL_LINKRESTART_EN_BITS                         1
#define PLL_PLLCONTROL_LINKRESTART_EN_SHIFT                        9

/* PLL :: pllControl :: ByteSyncRestart_en [08:08] */
#define PLL_PLLCONTROL_BYTESYNCRESTART_EN_MASK                     0x0100
#define PLL_PLLCONTROL_BYTESYNCRESTART_EN_ALIGN                    0
#define PLL_PLLCONTROL_BYTESYNCRESTART_EN_BITS                     1
#define PLL_PLLCONTROL_BYTESYNCRESTART_EN_SHIFT                    8

/* PLL :: pllControl :: PllForceDone_en [07:07] */
#define PLL_PLLCONTROL_PLLFORCEDONE_EN_MASK                        0x0080
#define PLL_PLLCONTROL_PLLFORCEDONE_EN_ALIGN                       0
#define PLL_PLLCONTROL_PLLFORCEDONE_EN_BITS                        1
#define PLL_PLLCONTROL_PLLFORCEDONE_EN_SHIFT                       7

/* PLL :: pllControl :: PllForceDone [06:06] */
#define PLL_PLLCONTROL_PLLFORCEDONE_MASK                           0x0040
#define PLL_PLLCONTROL_PLLFORCEDONE_ALIGN                          0
#define PLL_PLLCONTROL_PLLFORCEDONE_BITS                           1
#define PLL_PLLCONTROL_PLLFORCEDONE_SHIFT                          6

/* PLL :: pllControl :: PllForcePass [05:05] */
#define PLL_PLLCONTROL_PLLFORCEPASS_MASK                           0x0020
#define PLL_PLLCONTROL_PLLFORCEPASS_ALIGN                          0
#define PLL_PLLCONTROL_PLLFORCEPASS_BITS                           1
#define PLL_PLLCONTROL_PLLFORCEPASS_SHIFT                          5

/* PLL :: pllControl :: PllForceCapDone_en [04:04] */
#define PLL_PLLCONTROL_PLLFORCECAPDONE_EN_MASK                     0x0010
#define PLL_PLLCONTROL_PLLFORCECAPDONE_EN_ALIGN                    0
#define PLL_PLLCONTROL_PLLFORCECAPDONE_EN_BITS                     1
#define PLL_PLLCONTROL_PLLFORCECAPDONE_EN_SHIFT                    4

/* PLL :: pllControl :: PllForceCapDone [03:03] */
#define PLL_PLLCONTROL_PLLFORCECAPDONE_MASK                        0x0008
#define PLL_PLLCONTROL_PLLFORCECAPDONE_ALIGN                       0
#define PLL_PLLCONTROL_PLLFORCECAPDONE_BITS                        1
#define PLL_PLLCONTROL_PLLFORCECAPDONE_SHIFT                       3

/* PLL :: pllControl :: PllForceCapPass_en [02:02] */
#define PLL_PLLCONTROL_PLLFORCECAPPASS_EN_MASK                     0x0004
#define PLL_PLLCONTROL_PLLFORCECAPPASS_EN_ALIGN                    0
#define PLL_PLLCONTROL_PLLFORCECAPPASS_EN_BITS                     1
#define PLL_PLLCONTROL_PLLFORCECAPPASS_EN_SHIFT                    2

/* PLL :: pllControl :: PllForceCapPass [01:01] */
#define PLL_PLLCONTROL_PLLFORCECAPPASS_MASK                        0x0002
#define PLL_PLLCONTROL_PLLFORCECAPPASS_ALIGN                       0
#define PLL_PLLCONTROL_PLLFORCECAPPASS_BITS                        1
#define PLL_PLLCONTROL_PLLFORCECAPPASS_SHIFT                       1

/* PLL :: pllControl :: PllForcePllLock [00:00] */
#define PLL_PLLCONTROL_PLLFORCEPLLLOCK_MASK                        0x0001
#define PLL_PLLCONTROL_PLLFORCEPLLLOCK_ALIGN                       0
#define PLL_PLLCONTROL_PLLFORCEPLLLOCK_BITS                        1
#define PLL_PLLCONTROL_PLLFORCEPLLLOCK_SHIFT                       0


/****************************************************************************
 * PLL :: pllTimer1
 ***************************************************************************/
/* PLL :: pllTimer1 :: VcoStepTime [15:08] */
#define PLL_PLLTIMER1_VCOSTEPTIME_MASK                             0xff00
#define PLL_PLLTIMER1_VCOSTEPTIME_ALIGN                            0
#define PLL_PLLTIMER1_VCOSTEPTIME_BITS                             8
#define PLL_PLLTIMER1_VCOSTEPTIME_SHIFT                            8

/* PLL :: pllTimer1 :: VcoStartTime [07:00] */
#define PLL_PLLTIMER1_VCOSTARTTIME_MASK                            0x00ff
#define PLL_PLLTIMER1_VCOSTARTTIME_ALIGN                           0
#define PLL_PLLTIMER1_VCOSTARTTIME_BITS                            8
#define PLL_PLLTIMER1_VCOSTARTTIME_SHIFT                           0


/****************************************************************************
 * PLL :: pllTimer2
 ***************************************************************************/
/* PLL :: pllTimer2 :: reserved0 [15:15] */
#define PLL_PLLTIMER2_RESERVED0_MASK                               0x8000
#define PLL_PLLTIMER2_RESERVED0_ALIGN                              0
#define PLL_PLLTIMER2_RESERVED0_BITS                               1
#define PLL_PLLTIMER2_RESERVED0_SHIFT                              15

/* PLL :: pllTimer2 :: lfckSingleStep_en [14:14] */
#define PLL_PLLTIMER2_LFCKSINGLESTEP_EN_MASK                       0x4000
#define PLL_PLLTIMER2_LFCKSINGLESTEP_EN_ALIGN                      0
#define PLL_PLLTIMER2_LFCKSINGLESTEP_EN_BITS                       1
#define PLL_PLLTIMER2_LFCKSINGLESTEP_EN_SHIFT                      14

/* PLL :: pllTimer2 :: lfckSingleStep [13:13] */
#define PLL_PLLTIMER2_LFCKSINGLESTEP_MASK                          0x2000
#define PLL_PLLTIMER2_LFCKSINGLESTEP_ALIGN                         0
#define PLL_PLLTIMER2_LFCKSINGLESTEP_BITS                          1
#define PLL_PLLTIMER2_LFCKSINGLESTEP_SHIFT                         13

/* PLL :: pllTimer2 :: testMuxSel [12:08] */
#define PLL_PLLTIMER2_TESTMUXSEL_MASK                              0x1f00
#define PLL_PLLTIMER2_TESTMUXSEL_ALIGN                             0
#define PLL_PLLTIMER2_TESTMUXSEL_BITS                              5
#define PLL_PLLTIMER2_TESTMUXSEL_SHIFT                             8

/* PLL :: pllTimer2 :: retryTime [07:00] */
#define PLL_PLLTIMER2_RETRYTIME_MASK                               0x00ff
#define PLL_PLLTIMER2_RETRYTIME_ALIGN                              0
#define PLL_PLLTIMER2_RETRYTIME_BITS                               8
#define PLL_PLLTIMER2_RETRYTIME_SHIFT                              0


/****************************************************************************
 * PLL :: pllTimer3
 ***************************************************************************/
/* PLL :: pllTimer3 :: reserved0 [15:08] */
#define PLL_PLLTIMER3_RESERVED0_MASK                               0xff00
#define PLL_PLLTIMER3_RESERVED0_ALIGN                              0
#define PLL_PLLTIMER3_RESERVED0_BITS                               8
#define PLL_PLLTIMER3_RESERVED0_SHIFT                              8

/* PLL :: pllTimer3 :: freqDetTime [07:00] */
#define PLL_PLLTIMER3_FREQDETTIME_MASK                             0x00ff
#define PLL_PLLTIMER3_FREQDETTIME_ALIGN                            0
#define PLL_PLLTIMER3_FREQDETTIME_BITS                             8
#define PLL_PLLTIMER3_FREQDETTIME_SHIFT                            0


/****************************************************************************
 * PLL :: capControl
 ***************************************************************************/
/* PLL :: capControl :: StatusControl [15:15] */
#define PLL_CAPCONTROL_STATUSCONTROL_MASK                          0x8000
#define PLL_CAPCONTROL_STATUSCONTROL_ALIGN                         0
#define PLL_CAPCONTROL_STATUSCONTROL_BITS                          1
#define PLL_CAPCONTROL_STATUSCONTROL_SHIFT                         15

/* PLL :: capControl :: capRestart [14:14] */
#define PLL_CAPCONTROL_CAPRESTART_MASK                             0x4000
#define PLL_CAPCONTROL_CAPRESTART_ALIGN                            0
#define PLL_CAPCONTROL_CAPRESTART_BITS                             1
#define PLL_CAPCONTROL_CAPRESTART_SHIFT                            14

/* PLL :: capControl :: capSelectM_en [13:13] */
#define PLL_CAPCONTROL_CAPSELECTM_EN_MASK                          0x2000
#define PLL_CAPCONTROL_CAPSELECTM_EN_ALIGN                         0
#define PLL_CAPCONTROL_CAPSELECTM_EN_BITS                          1
#define PLL_CAPCONTROL_CAPSELECTM_EN_SHIFT                         13

/* PLL :: capControl :: capForceSlowdn_en [12:12] */
#define PLL_CAPCONTROL_CAPFORCESLOWDN_EN_MASK                      0x1000
#define PLL_CAPCONTROL_CAPFORCESLOWDN_EN_ALIGN                     0
#define PLL_CAPCONTROL_CAPFORCESLOWDN_EN_BITS                      1
#define PLL_CAPCONTROL_CAPFORCESLOWDN_EN_SHIFT                     12

/* PLL :: capControl :: reserved0 [11:10] */
#define PLL_CAPCONTROL_RESERVED0_MASK                              0x0c00
#define PLL_CAPCONTROL_RESERVED0_ALIGN                             0
#define PLL_CAPCONTROL_RESERVED0_BITS                              2
#define PLL_CAPCONTROL_RESERVED0_SHIFT                             10

/* PLL :: capControl :: slowdn_xor [09:09] */
#define PLL_CAPCONTROL_SLOWDN_XOR_MASK                             0x0200
#define PLL_CAPCONTROL_SLOWDN_XOR_ALIGN                            0
#define PLL_CAPCONTROL_SLOWDN_XOR_BITS                             1
#define PLL_CAPCONTROL_SLOWDN_XOR_SHIFT                            9

/* union - case Status [08:00] */
/* PLL :: capControl :: Slowdn [08:08] */
#define PLL_CAPCONTROL_STATUS_SLOWDN_MASK                          0x0100
#define PLL_CAPCONTROL_STATUS_SLOWDN_ALIGN                         0
#define PLL_CAPCONTROL_STATUS_SLOWDN_BITS                          1
#define PLL_CAPCONTROL_STATUS_SLOWDN_SHIFT                         8

/* PLL :: capControl :: reserved0 [07:07] */
#define PLL_CAPCONTROL_STATUS_RESERVED0_MASK                       0x0080
#define PLL_CAPCONTROL_STATUS_RESERVED0_ALIGN                      0
#define PLL_CAPCONTROL_STATUS_RESERVED0_BITS                       1
#define PLL_CAPCONTROL_STATUS_RESERVED0_SHIFT                      7

/* PLL :: capControl :: capSelect [06:00] */
#define PLL_CAPCONTROL_STATUS_CAPSELECT_MASK                       0x007f
#define PLL_CAPCONTROL_STATUS_CAPSELECT_ALIGN                      0
#define PLL_CAPCONTROL_STATUS_CAPSELECT_BITS                       7
#define PLL_CAPCONTROL_STATUS_CAPSELECT_SHIFT                      0


/* union - case Control [08:00] */
/* PLL :: capControl :: capForceSlowdn [08:08] */
#define PLL_CAPCONTROL_CONTROL_CAPFORCESLOWDN_MASK                 0x0100
#define PLL_CAPCONTROL_CONTROL_CAPFORCESLOWDN_ALIGN                0
#define PLL_CAPCONTROL_CONTROL_CAPFORCESLOWDN_BITS                 1
#define PLL_CAPCONTROL_CONTROL_CAPFORCESLOWDN_SHIFT                8

/* PLL :: capControl :: reserved0 [07:07] */
#define PLL_CAPCONTROL_CONTROL_RESERVED0_MASK                      0x0080
#define PLL_CAPCONTROL_CONTROL_RESERVED0_ALIGN                     0
#define PLL_CAPCONTROL_CONTROL_RESERVED0_BITS                      1
#define PLL_CAPCONTROL_CONTROL_RESERVED0_SHIFT                     7

/* PLL :: capControl :: capSelectM [06:00] */
#define PLL_CAPCONTROL_CONTROL_CAPSELECTM_MASK                     0x007f
#define PLL_CAPCONTROL_CONTROL_CAPSELECTM_ALIGN                    0
#define PLL_CAPCONTROL_CONTROL_CAPSELECTM_BITS                     7
#define PLL_CAPCONTROL_CONTROL_CAPSELECTM_SHIFT                    0



/****************************************************************************
 * PLL :: ampControl
 ***************************************************************************/
/* PLL :: ampControl :: StatusControl [15:15] */
#define PLL_AMPCONTROL_STATUSCONTROL_MASK                          0x8000
#define PLL_AMPCONTROL_STATUSCONTROL_ALIGN                         0
#define PLL_AMPCONTROL_STATUSCONTROL_BITS                          1
#define PLL_AMPCONTROL_STATUSCONTROL_SHIFT                         15

/* PLL :: ampControl :: ampRestart [14:14] */
#define PLL_AMPCONTROL_AMPRESTART_MASK                             0x4000
#define PLL_AMPCONTROL_AMPRESTART_ALIGN                            0
#define PLL_AMPCONTROL_AMPRESTART_BITS                             1
#define PLL_AMPCONTROL_AMPRESTART_SHIFT                            14

/* PLL :: ampControl :: ampSelectM_en [13:13] */
#define PLL_AMPCONTROL_AMPSELECTM_EN_MASK                          0x2000
#define PLL_AMPCONTROL_AMPSELECTM_EN_ALIGN                         0
#define PLL_AMPCONTROL_AMPSELECTM_EN_BITS                          1
#define PLL_AMPCONTROL_AMPSELECTM_EN_SHIFT                         13

/* PLL :: ampControl :: ampForceBvddAvss_en [12:12] */
#define PLL_AMPCONTROL_AMPFORCEBVDDAVSS_EN_MASK                    0x1000
#define PLL_AMPCONTROL_AMPFORCEBVDDAVSS_EN_ALIGN                   0
#define PLL_AMPCONTROL_AMPFORCEBVDDAVSS_EN_BITS                    1
#define PLL_AMPCONTROL_AMPFORCEBVDDAVSS_EN_SHIFT                   12

/* PLL :: ampControl :: ampIgnoreFailure [11:11] */
#define PLL_AMPCONTROL_AMPIGNOREFAILURE_MASK                       0x0800
#define PLL_AMPCONTROL_AMPIGNOREFAILURE_ALIGN                      0
#define PLL_AMPCONTROL_AMPIGNOREFAILURE_BITS                       1
#define PLL_AMPCONTROL_AMPIGNOREFAILURE_SHIFT                      11

/* PLL :: ampControl :: getVcoLatch [10:10] */
#define PLL_AMPCONTROL_GETVCOLATCH_MASK                            0x0400
#define PLL_AMPCONTROL_GETVCOLATCH_ALIGN                           0
#define PLL_AMPCONTROL_GETVCOLATCH_BITS                            1
#define PLL_AMPCONTROL_GETVCOLATCH_SHIFT                           10

/* PLL :: ampControl :: reserved0 [09:06] */
#define PLL_AMPCONTROL_RESERVED0_MASK                              0x03c0
#define PLL_AMPCONTROL_RESERVED0_ALIGN                             0
#define PLL_AMPCONTROL_RESERVED0_BITS                              4
#define PLL_AMPCONTROL_RESERVED0_SHIFT                             6

/* union - case Status [05:00] */
/* PLL :: ampControl :: belowVdd [05:05] */
#define PLL_AMPCONTROL_STATUS_BELOWVDD_MASK                        0x0020
#define PLL_AMPCONTROL_STATUS_BELOWVDD_ALIGN                       0
#define PLL_AMPCONTROL_STATUS_BELOWVDD_BITS                        1
#define PLL_AMPCONTROL_STATUS_BELOWVDD_SHIFT                       5

/* PLL :: ampControl :: aboveVss [04:04] */
#define PLL_AMPCONTROL_STATUS_ABOVEVSS_MASK                        0x0010
#define PLL_AMPCONTROL_STATUS_ABOVEVSS_ALIGN                       0
#define PLL_AMPCONTROL_STATUS_ABOVEVSS_BITS                        1
#define PLL_AMPCONTROL_STATUS_ABOVEVSS_SHIFT                       4

/* PLL :: ampControl :: reserved0 [03:03] */
#define PLL_AMPCONTROL_STATUS_RESERVED0_MASK                       0x0008
#define PLL_AMPCONTROL_STATUS_RESERVED0_ALIGN                      0
#define PLL_AMPCONTROL_STATUS_RESERVED0_BITS                       1
#define PLL_AMPCONTROL_STATUS_RESERVED0_SHIFT                      3

/* PLL :: ampControl :: selectM [02:00] */
#define PLL_AMPCONTROL_STATUS_SELECTM_MASK                         0x0007
#define PLL_AMPCONTROL_STATUS_SELECTM_ALIGN                        0
#define PLL_AMPCONTROL_STATUS_SELECTM_BITS                         3
#define PLL_AMPCONTROL_STATUS_SELECTM_SHIFT                        0


/* union - case Control [05:00] */
/* PLL :: ampControl :: ampForceBelowVdd [05:05] */
#define PLL_AMPCONTROL_CONTROL_AMPFORCEBELOWVDD_MASK               0x0020
#define PLL_AMPCONTROL_CONTROL_AMPFORCEBELOWVDD_ALIGN              0
#define PLL_AMPCONTROL_CONTROL_AMPFORCEBELOWVDD_BITS               1
#define PLL_AMPCONTROL_CONTROL_AMPFORCEBELOWVDD_SHIFT              5

/* PLL :: ampControl :: ampForceAboveVss [04:04] */
#define PLL_AMPCONTROL_CONTROL_AMPFORCEABOVEVSS_MASK               0x0010
#define PLL_AMPCONTROL_CONTROL_AMPFORCEABOVEVSS_ALIGN              0
#define PLL_AMPCONTROL_CONTROL_AMPFORCEABOVEVSS_BITS               1
#define PLL_AMPCONTROL_CONTROL_AMPFORCEABOVEVSS_SHIFT              4

/* PLL :: ampControl :: reserved0 [03:03] */
#define PLL_AMPCONTROL_CONTROL_RESERVED0_MASK                      0x0008
#define PLL_AMPCONTROL_CONTROL_RESERVED0_ALIGN                     0
#define PLL_AMPCONTROL_CONTROL_RESERVED0_BITS                      1
#define PLL_AMPCONTROL_CONTROL_RESERVED0_SHIFT                     3

/* PLL :: ampControl :: ampForceSelectM [02:00] */
#define PLL_AMPCONTROL_CONTROL_AMPFORCESELECTM_MASK                0x0007
#define PLL_AMPCONTROL_CONTROL_AMPFORCESELECTM_ALIGN               0
#define PLL_AMPCONTROL_CONTROL_AMPFORCESELECTM_BITS                3
#define PLL_AMPCONTROL_CONTROL_AMPFORCESELECTM_SHIFT               0



/****************************************************************************
 * PLL :: freqDetCounter
 ***************************************************************************/
/* PLL :: freqDetCounter :: resolution [15:08] */
#define PLL_FREQDETCOUNTER_RESOLUTION_MASK                         0xff00
#define PLL_FREQDETCOUNTER_RESOLUTION_ALIGN                        0
#define PLL_FREQDETCOUNTER_RESOLUTION_BITS                         8
#define PLL_FREQDETCOUNTER_RESOLUTION_SHIFT                        8

/* PLL :: freqDetCounter :: window [07:00] */
#define PLL_FREQDETCOUNTER_WINDOW_MASK                             0x00ff
#define PLL_FREQDETCOUNTER_WINDOW_ALIGN                            0
#define PLL_FREQDETCOUNTER_WINDOW_BITS                             8
#define PLL_FREQDETCOUNTER_WINDOW_SHIFT                            0


/****************************************************************************
 * PLL :: pllAstatus1
 ***************************************************************************/
/* PLL :: pllAstatus1 :: reserved0 [15:14] */
#define PLL_PLLASTATUS1_RESERVED0_MASK                             0xc000
#define PLL_PLLASTATUS1_RESERVED0_ALIGN                            0
#define PLL_PLLASTATUS1_RESERVED0_BITS                             2
#define PLL_PLLASTATUS1_RESERVED0_SHIFT                            14

/* PLL :: pllAstatus1 :: kvh [13:12] */
#define PLL_PLLASTATUS1_KVH_MASK                                   0x3000
#define PLL_PLLASTATUS1_KVH_ALIGN                                  0
#define PLL_PLLASTATUS1_KVH_BITS                                   2
#define PLL_PLLASTATUS1_KVH_SHIFT                                  12

/* PLL :: pllAstatus1 :: pll_range [11:08] */
#define PLL_PLLASTATUS1_PLL_RANGE_MASK                             0x0f00
#define PLL_PLLASTATUS1_PLL_RANGE_ALIGN                            0
#define PLL_PLLASTATUS1_PLL_RANGE_BITS                             4
#define PLL_PLLASTATUS1_PLL_RANGE_SHIFT                            8

/* PLL :: pllAstatus1 :: pll_low [07:07] */
#define PLL_PLLASTATUS1_PLL_LOW_MASK                               0x0080
#define PLL_PLLASTATUS1_PLL_LOW_ALIGN                              0
#define PLL_PLLASTATUS1_PLL_LOW_BITS                               1
#define PLL_PLLASTATUS1_PLL_LOW_SHIFT                              7

/* PLL :: pllAstatus1 :: reserved1 [06:04] */
#define PLL_PLLASTATUS1_RESERVED1_MASK                             0x0070
#define PLL_PLLASTATUS1_RESERVED1_ALIGN                            0
#define PLL_PLLASTATUS1_RESERVED1_BITS                             3
#define PLL_PLLASTATUS1_RESERVED1_SHIFT                            4

/* PLL :: pllAstatus1 :: pll_Ndiv [03:00] */
#define PLL_PLLASTATUS1_PLL_NDIV_MASK                              0x000f
#define PLL_PLLASTATUS1_PLL_NDIV_ALIGN                             0
#define PLL_PLLASTATUS1_PLL_NDIV_BITS                              4
#define PLL_PLLASTATUS1_PLL_NDIV_SHIFT                             0


/****************************************************************************
 * PLL :: pllClockGen
 ***************************************************************************/
/* PLL :: pllClockGen :: refl_clken [15:15] */
#define PLL_PLLCLOCKGEN_REFL_CLKEN_MASK                            0x8000
#define PLL_PLLCLOCKGEN_REFL_CLKEN_ALIGN                           0
#define PLL_PLLCLOCKGEN_REFL_CLKEN_BITS                            1
#define PLL_PLLCLOCKGEN_REFL_CLKEN_SHIFT                           15

/* PLL :: pllClockGen :: iclkidrv1 [14:12] */
#define PLL_PLLCLOCKGEN_ICLKIDRV1_MASK                             0x7000
#define PLL_PLLCLOCKGEN_ICLKIDRV1_ALIGN                            0
#define PLL_PLLCLOCKGEN_ICLKIDRV1_BITS                             3
#define PLL_PLLCLOCKGEN_ICLKIDRV1_SHIFT                            12

/* PLL :: pllClockGen :: iclkodrv1 [11:09] */
#define PLL_PLLCLOCKGEN_ICLKODRV1_MASK                             0x0e00
#define PLL_PLLCLOCKGEN_ICLKODRV1_ALIGN                            0
#define PLL_PLLCLOCKGEN_ICLKODRV1_BITS                             3
#define PLL_PLLCLOCKGEN_ICLKODRV1_SHIFT                            9

/* PLL :: pllClockGen :: iclkodrv2 [08:06] */
#define PLL_PLLCLOCKGEN_ICLKODRV2_MASK                             0x01c0
#define PLL_PLLCLOCKGEN_ICLKODRV2_ALIGN                            0
#define PLL_PLLCLOCKGEN_ICLKODRV2_BITS                             3
#define PLL_PLLCLOCKGEN_ICLKODRV2_SHIFT                            6

/* PLL :: pllClockGen :: iclkidrv2 [05:03] */
#define PLL_PLLCLOCKGEN_ICLKIDRV2_MASK                             0x0038
#define PLL_PLLCLOCKGEN_ICLKIDRV2_ALIGN                            0
#define PLL_PLLCLOCKGEN_ICLKIDRV2_BITS                             3
#define PLL_PLLCLOCKGEN_ICLKIDRV2_SHIFT                            3

/* PLL :: pllClockGen :: reserved0 [02:02] */
#define PLL_PLLCLOCKGEN_RESERVED0_MASK                             0x0004
#define PLL_PLLCLOCKGEN_RESERVED0_ALIGN                            0
#define PLL_PLLCLOCKGEN_RESERVED0_BITS                             1
#define PLL_PLLCLOCKGEN_RESERVED0_SHIFT                            2

/* PLL :: pllClockGen :: vddr_bgb [01:01] */
#define PLL_PLLCLOCKGEN_VDDR_BGB_MASK                              0x0002
#define PLL_PLLCLOCKGEN_VDDR_BGB_ALIGN                             0
#define PLL_PLLCLOCKGEN_VDDR_BGB_BITS                              1
#define PLL_PLLCLOCKGEN_VDDR_BGB_SHIFT                             1

/* PLL :: pllClockGen :: clksel_halfrate [00:00] */
#define PLL_PLLCLOCKGEN_CLKSEL_HALFRATE_MASK                       0x0001
#define PLL_PLLCLOCKGEN_CLKSEL_HALFRATE_ALIGN                      0
#define PLL_PLLCLOCKGEN_CLKSEL_HALFRATE_BITS                       1
#define PLL_PLLCLOCKGEN_CLKSEL_HALFRATE_SHIFT                      0


/****************************************************************************
 * PLL :: pllNdiv
 ***************************************************************************/
/* PLL :: pllNdiv :: kvhce [15:15] */
#define PLL_PLLNDIV_KVHCE_MASK                                     0x8000
#define PLL_PLLNDIV_KVHCE_ALIGN                                    0
#define PLL_PLLNDIV_KVHCE_BITS                                     1
#define PLL_PLLNDIV_KVHCE_SHIFT                                    15

/* PLL :: pllNdiv :: reserved0 [14:11] */
#define PLL_PLLNDIV_RESERVED0_MASK                                 0x7800
#define PLL_PLLNDIV_RESERVED0_ALIGN                                0
#define PLL_PLLNDIV_RESERVED0_BITS                                 4
#define PLL_PLLNDIV_RESERVED0_SHIFT                                11

/* PLL :: pllNdiv :: iclkibuf4 [10:08] */
#define PLL_PLLNDIV_ICLKIBUF4_MASK                                 0x0700
#define PLL_PLLNDIV_ICLKIBUF4_ALIGN                                0
#define PLL_PLLNDIV_ICLKIBUF4_BITS                                 3
#define PLL_PLLNDIV_ICLKIBUF4_SHIFT                                8

/* PLL :: pllNdiv :: ibias_all [07:05] */
#define PLL_PLLNDIV_IBIAS_ALL_MASK                                 0x00e0
#define PLL_PLLNDIV_IBIAS_ALL_ALIGN                                0
#define PLL_PLLNDIV_IBIAS_ALL_BITS                                 3
#define PLL_PLLNDIV_IBIAS_ALL_SHIFT                                5

/* PLL :: pllNdiv :: refout_en [04:04] */
#define PLL_PLLNDIV_REFOUT_EN_MASK                                 0x0010
#define PLL_PLLNDIV_REFOUT_EN_ALIGN                                0
#define PLL_PLLNDIV_REFOUT_EN_BITS                                 1
#define PLL_PLLNDIV_REFOUT_EN_SHIFT                                4

/* PLL :: pllNdiv :: refin_en [03:03] */
#define PLL_PLLNDIV_REFIN_EN_MASK                                  0x0008
#define PLL_PLLNDIV_REFIN_EN_ALIGN                                 0
#define PLL_PLLNDIV_REFIN_EN_BITS                                  1
#define PLL_PLLNDIV_REFIN_EN_SHIFT                                 3

/* PLL :: pllNdiv :: pll2rx_clkbw [02:01] */
#define PLL_PLLNDIV_PLL2RX_CLKBW_MASK                              0x0006
#define PLL_PLLNDIV_PLL2RX_CLKBW_ALIGN                             0
#define PLL_PLLNDIV_PLL2RX_CLKBW_BITS                              2
#define PLL_PLLNDIV_PLL2RX_CLKBW_SHIFT                             1

/* PLL :: pllNdiv :: refh_clkgen [00:00] */
#define PLL_PLLNDIV_REFH_CLKGEN_MASK                               0x0001
#define PLL_PLLNDIV_REFH_CLKGEN_ALIGN                              0
#define PLL_PLLNDIV_REFH_CLKGEN_BITS                               1
#define PLL_PLLNDIV_REFH_CLKGEN_SHIFT                              0


/****************************************************************************
 * PLL :: pllBglqp
 ***************************************************************************/
/* PLL :: pllBglqp :: ick2 [15:15] */
#define PLL_PLLBGLQP_ICK2_MASK                                     0x8000
#define PLL_PLLBGLQP_ICK2_ALIGN                                    0
#define PLL_PLLBGLQP_ICK2_BITS                                     1
#define PLL_PLLBGLQP_ICK2_SHIFT                                    15

/* PLL :: pllBglqp :: ick0 [14:14] */
#define PLL_PLLBGLQP_ICK0_MASK                                     0x4000
#define PLL_PLLBGLQP_ICK0_ALIGN                                    0
#define PLL_PLLBGLQP_ICK0_BITS                                     1
#define PLL_PLLBGLQP_ICK0_SHIFT                                    14

/* PLL :: pllBglqp :: ick1 [13:13] */
#define PLL_PLLBGLQP_ICK1_MASK                                     0x2000
#define PLL_PLLBGLQP_ICK1_ALIGN                                    0
#define PLL_PLLBGLQP_ICK1_BITS                                     1
#define PLL_PLLBGLQP_ICK1_SHIFT                                    13

/* PLL :: pllBglqp :: icp2 [12:12] */
#define PLL_PLLBGLQP_ICP2_MASK                                     0x1000
#define PLL_PLLBGLQP_ICP2_ALIGN                                    0
#define PLL_PLLBGLQP_ICP2_BITS                                     1
#define PLL_PLLBGLQP_ICP2_SHIFT                                    12

/* PLL :: pllBglqp :: icp0 [11:11] */
#define PLL_PLLBGLQP_ICP0_MASK                                     0x0800
#define PLL_PLLBGLQP_ICP0_ALIGN                                    0
#define PLL_PLLBGLQP_ICP0_BITS                                     1
#define PLL_PLLBGLQP_ICP0_SHIFT                                    11

/* PLL :: pllBglqp :: icp1 [10:10] */
#define PLL_PLLBGLQP_ICP1_MASK                                     0x0400
#define PLL_PLLBGLQP_ICP1_ALIGN                                    0
#define PLL_PLLBGLQP_ICP1_BITS                                     1
#define PLL_PLLBGLQP_ICP1_SHIFT                                    10

/* PLL :: pllBglqp :: ibmax [09:09] */
#define PLL_PLLBGLQP_IBMAX_MASK                                    0x0200
#define PLL_PLLBGLQP_IBMAX_ALIGN                                   0
#define PLL_PLLBGLQP_IBMAX_BITS                                    1
#define PLL_PLLBGLQP_IBMAX_SHIFT                                   9

/* PLL :: pllBglqp :: ibmode [08:08] */
#define PLL_PLLBGLQP_IBMODE_MASK                                   0x0100
#define PLL_PLLBGLQP_IBMODE_ALIGN                                  0
#define PLL_PLLBGLQP_IBMODE_BITS                                   1
#define PLL_PLLBGLQP_IBMODE_SHIFT                                  8

/* PLL :: pllBglqp :: ibmin [07:07] */
#define PLL_PLLBGLQP_IBMIN_MASK                                    0x0080
#define PLL_PLLBGLQP_IBMIN_ALIGN                                   0
#define PLL_PLLBGLQP_IBMIN_BITS                                    1
#define PLL_PLLBGLQP_IBMIN_SHIFT                                   7

/* PLL :: pllBglqp :: refh_pll [06:06] */
#define PLL_PLLBGLQP_REFH_PLL_MASK                                 0x0040
#define PLL_PLLBGLQP_REFH_PLL_ALIGN                                0
#define PLL_PLLBGLQP_REFH_PLL_BITS                                 1
#define PLL_PLLBGLQP_REFH_PLL_SHIFT                                6

/* PLL :: pllBglqp :: refl_pll [05:05] */
#define PLL_PLLBGLQP_REFL_PLL_MASK                                 0x0020
#define PLL_PLLBGLQP_REFL_PLL_ALIGN                                0
#define PLL_PLLBGLQP_REFL_PLL_BITS                                 1
#define PLL_PLLBGLQP_REFL_PLL_SHIFT                                5

/* PLL :: pllBglqp :: iqp [04:02] */
#define PLL_PLLBGLQP_IQP_MASK                                      0x001c
#define PLL_PLLBGLQP_IQP_ALIGN                                     0
#define PLL_PLLBGLQP_IQP_BITS                                      3
#define PLL_PLLBGLQP_IQP_SHIFT                                     2

/* PLL :: pllBglqp :: en_p3 [01:01] */
#define PLL_PLLBGLQP_EN_P3_MASK                                    0x0002
#define PLL_PLLBGLQP_EN_P3_ALIGN                                   0
#define PLL_PLLBGLQP_EN_P3_BITS                                    1
#define PLL_PLLBGLQP_EN_P3_SHIFT                                   1

/* PLL :: pllBglqp :: enable_ftune [00:00] */
#define PLL_PLLBGLQP_ENABLE_FTUNE_MASK                             0x0001
#define PLL_PLLBGLQP_ENABLE_FTUNE_ALIGN                            0
#define PLL_PLLBGLQP_ENABLE_FTUNE_BITS                             1
#define PLL_PLLBGLQP_ENABLE_FTUNE_SHIFT                            0


/****************************************************************************
 * PLL :: pllTestKvh
 ***************************************************************************/
/* PLL :: pllTestKvh :: test_rx [15:15] */
#define PLL_PLLTESTKVH_TEST_RX_MASK                                0x8000
#define PLL_PLLTESTKVH_TEST_RX_ALIGN                               0
#define PLL_PLLTESTKVH_TEST_RX_BITS                                1
#define PLL_PLLTESTKVH_TEST_RX_SHIFT                               15

/* PLL :: pllTestKvh :: test_pll [14:14] */
#define PLL_PLLTESTKVH_TEST_PLL_MASK                               0x4000
#define PLL_PLLTESTKVH_TEST_PLL_ALIGN                              0
#define PLL_PLLTESTKVH_TEST_PLL_BITS                               1
#define PLL_PLLTESTKVH_TEST_PLL_SHIFT                              14

/* PLL :: pllTestKvh :: test_vc [13:13] */
#define PLL_PLLTESTKVH_TEST_VC_MASK                                0x2000
#define PLL_PLLTESTKVH_TEST_VC_ALIGN                               0
#define PLL_PLLTESTKVH_TEST_VC_BITS                                1
#define PLL_PLLTESTKVH_TEST_VC_SHIFT                               13

/* PLL :: pllTestKvh :: test_vref [12:12] */
#define PLL_PLLTESTKVH_TEST_VREF_MASK                              0x1000
#define PLL_PLLTESTKVH_TEST_VREF_ALIGN                             0
#define PLL_PLLTESTKVH_TEST_VREF_BITS                              1
#define PLL_PLLTESTKVH_TEST_VREF_SHIFT                             12

/* PLL :: pllTestKvh :: iop2 [11:11] */
#define PLL_PLLTESTKVH_IOP2_MASK                                   0x0800
#define PLL_PLLTESTKVH_IOP2_ALIGN                                  0
#define PLL_PLLTESTKVH_IOP2_BITS                                   1
#define PLL_PLLTESTKVH_IOP2_SHIFT                                  11

/* PLL :: pllTestKvh :: iop0 [10:10] */
#define PLL_PLLTESTKVH_IOP0_MASK                                   0x0400
#define PLL_PLLTESTKVH_IOP0_ALIGN                                  0
#define PLL_PLLTESTKVH_IOP0_BITS                                   1
#define PLL_PLLTESTKVH_IOP0_SHIFT                                  10

/* PLL :: pllTestKvh :: iop1 [09:09] */
#define PLL_PLLTESTKVH_IOP1_MASK                                   0x0200
#define PLL_PLLTESTKVH_IOP1_ALIGN                                  0
#define PLL_PLLTESTKVH_IOP1_BITS                                   1
#define PLL_PLLTESTKVH_IOP1_SHIFT                                  9

/* PLL :: pllTestKvh :: icomp2 [08:08] */
#define PLL_PLLTESTKVH_ICOMP2_MASK                                 0x0100
#define PLL_PLLTESTKVH_ICOMP2_ALIGN                                0
#define PLL_PLLTESTKVH_ICOMP2_BITS                                 1
#define PLL_PLLTESTKVH_ICOMP2_SHIFT                                8

/* PLL :: pllTestKvh :: icomp0 [07:07] */
#define PLL_PLLTESTKVH_ICOMP0_MASK                                 0x0080
#define PLL_PLLTESTKVH_ICOMP0_ALIGN                                0
#define PLL_PLLTESTKVH_ICOMP0_BITS                                 1
#define PLL_PLLTESTKVH_ICOMP0_SHIFT                                7

/* PLL :: pllTestKvh :: icomp1 [06:06] */
#define PLL_PLLTESTKVH_ICOMP1_MASK                                 0x0040
#define PLL_PLLTESTKVH_ICOMP1_ALIGN                                0
#define PLL_PLLTESTKVH_ICOMP1_BITS                                 1
#define PLL_PLLTESTKVH_ICOMP1_SHIFT                                6

/* PLL :: pllTestKvh :: icml2 [05:05] */
#define PLL_PLLTESTKVH_ICML2_MASK                                  0x0020
#define PLL_PLLTESTKVH_ICML2_ALIGN                                 0
#define PLL_PLLTESTKVH_ICML2_BITS                                  1
#define PLL_PLLTESTKVH_ICML2_SHIFT                                 5

/* PLL :: pllTestKvh :: icml0 [04:04] */
#define PLL_PLLTESTKVH_ICML0_MASK                                  0x0010
#define PLL_PLLTESTKVH_ICML0_ALIGN                                 0
#define PLL_PLLTESTKVH_ICML0_BITS                                  1
#define PLL_PLLTESTKVH_ICML0_SHIFT                                 4

/* PLL :: pllTestKvh :: icml1 [03:03] */
#define PLL_PLLTESTKVH_ICML1_MASK                                  0x0008
#define PLL_PLLTESTKVH_ICML1_ALIGN                                 0
#define PLL_PLLTESTKVH_ICML1_BITS                                  1
#define PLL_PLLTESTKVH_ICML1_SHIFT                                 3

/* PLL :: pllTestKvh :: ivco2 [02:02] */
#define PLL_PLLTESTKVH_IVCO2_MASK                                  0x0004
#define PLL_PLLTESTKVH_IVCO2_ALIGN                                 0
#define PLL_PLLTESTKVH_IVCO2_BITS                                  1
#define PLL_PLLTESTKVH_IVCO2_SHIFT                                 2

/* PLL :: pllTestKvh :: ivco0 [01:01] */
#define PLL_PLLTESTKVH_IVCO0_MASK                                  0x0002
#define PLL_PLLTESTKVH_IVCO0_ALIGN                                 0
#define PLL_PLLTESTKVH_IVCO0_BITS                                  1
#define PLL_PLLTESTKVH_IVCO0_SHIFT                                 1

/* PLL :: pllTestKvh :: ivco1 [00:00] */
#define PLL_PLLTESTKVH_IVCO1_MASK                                  0x0001
#define PLL_PLLTESTKVH_IVCO1_ALIGN                                 0
#define PLL_PLLTESTKVH_IVCO1_BITS                                  1
#define PLL_PLLTESTKVH_IVCO1_SHIFT                                 0


/****************************************************************************
 * PLL :: pllAcontrol5
 ***************************************************************************/
/* PLL :: pllAcontrol5 :: en65G [15:15] */
#define PLL_PLLACONTROL5_EN65G_MASK                                0x8000
#define PLL_PLLACONTROL5_EN65G_ALIGN                               0
#define PLL_PLLACONTROL5_EN65G_BITS                                1
#define PLL_PLLACONTROL5_EN65G_SHIFT                               15

/* PLL :: pllAcontrol5 :: reserved0 [14:12] */
#define PLL_PLLACONTROL5_RESERVED0_MASK                            0x7000
#define PLL_PLLACONTROL5_RESERVED0_ALIGN                           0
#define PLL_PLLACONTROL5_RESERVED0_BITS                            3
#define PLL_PLLACONTROL5_RESERVED0_SHIFT                           12

/* PLL :: pllAcontrol5 :: vddr_bgb [11:11] */
#define PLL_PLLACONTROL5_VDDR_BGB_MASK                             0x0800
#define PLL_PLLACONTROL5_VDDR_BGB_ALIGN                            0
#define PLL_PLLACONTROL5_VDDR_BGB_BITS                             1
#define PLL_PLLACONTROL5_VDDR_BGB_SHIFT                            11

/* PLL :: pllAcontrol5 :: comp_vth [10:10] */
#define PLL_PLLACONTROL5_COMP_VTH_MASK                             0x0400
#define PLL_PLLACONTROL5_COMP_VTH_ALIGN                            0
#define PLL_PLLACONTROL5_COMP_VTH_BITS                             1
#define PLL_PLLACONTROL5_COMP_VTH_SHIFT                            10

/* PLL :: pllAcontrol5 :: actrl [09:08] */
#define PLL_PLLACONTROL5_ACTRL_MASK                                0x0300
#define PLL_PLLACONTROL5_ACTRL_ALIGN                               0
#define PLL_PLLACONTROL5_ACTRL_BITS                                2
#define PLL_PLLACONTROL5_ACTRL_SHIFT                               8

/* PLL :: pllAcontrol5 :: ctatadj [07:04] */
#define PLL_PLLACONTROL5_CTATADJ_MASK                              0x00f0
#define PLL_PLLACONTROL5_CTATADJ_ALIGN                             0
#define PLL_PLLACONTROL5_CTATADJ_BITS                              4
#define PLL_PLLACONTROL5_CTATADJ_SHIFT                             4

/* PLL :: pllAcontrol5 :: ptatadj [03:00] */
#define PLL_PLLACONTROL5_PTATADJ_MASK                              0x000f
#define PLL_PLLACONTROL5_PTATADJ_ALIGN                             0
#define PLL_PLLACONTROL5_PTATADJ_BITS                              4
#define PLL_PLLACONTROL5_PTATADJ_SHIFT                             0


/****************************************************************************
 * XGXS16G_USER_TX0
 ***************************************************************************/
/****************************************************************************
 * TX0 :: Tx_AStatus0
 ***************************************************************************/
/* TX0 :: Tx_AStatus0 :: reserved0 [15:03] */
#define TX0_TX_ASTATUS0_RESERVED0_MASK                             0xfff8
#define TX0_TX_ASTATUS0_RESERVED0_ALIGN                            0
#define TX0_TX_ASTATUS0_RESERVED0_BITS                             13
#define TX0_TX_ASTATUS0_RESERVED0_SHIFT                            3

/* TX0 :: Tx_AStatus0 :: tx_gloopback [02:02] */
#define TX0_TX_ASTATUS0_TX_GLOOPBACK_MASK                          0x0004
#define TX0_TX_ASTATUS0_TX_GLOOPBACK_ALIGN                         0
#define TX0_TX_ASTATUS0_TX_GLOOPBACK_BITS                          1
#define TX0_TX_ASTATUS0_TX_GLOOPBACK_SHIFT                         2

/* TX0 :: Tx_AStatus0 :: rltxferr [01:01] */
#define TX0_TX_ASTATUS0_RLTXFERR_MASK                              0x0002
#define TX0_TX_ASTATUS0_RLTXFERR_ALIGN                             0
#define TX0_TX_ASTATUS0_RLTXFERR_BITS                              1
#define TX0_TX_ASTATUS0_RLTXFERR_SHIFT                             1

/* TX0 :: Tx_AStatus0 :: txferr [00:00] */
#define TX0_TX_ASTATUS0_TXFERR_MASK                                0x0001
#define TX0_TX_ASTATUS0_TXFERR_ALIGN                               0
#define TX0_TX_ASTATUS0_TXFERR_BITS                                1
#define TX0_TX_ASTATUS0_TXFERR_SHIFT                               0


/****************************************************************************
 * TX0 :: Tx_AControl0
 ***************************************************************************/
/* TX0 :: Tx_AControl0 :: reserved0 [15:15] */
#define TX0_TX_ACONTROL0_RESERVED0_MASK                            0x8000
#define TX0_TX_ACONTROL0_RESERVED0_ALIGN                           0
#define TX0_TX_ACONTROL0_RESERVED0_BITS                            1
#define TX0_TX_ACONTROL0_RESERVED0_SHIFT                           15

/* TX0 :: Tx_AControl0 :: force_txclk [14:14] */
#define TX0_TX_ACONTROL0_FORCE_TXCLK_MASK                          0x4000
#define TX0_TX_ACONTROL0_FORCE_TXCLK_ALIGN                         0
#define TX0_TX_ACONTROL0_FORCE_TXCLK_BITS                          1
#define TX0_TX_ACONTROL0_FORCE_TXCLK_SHIFT                         14

/* TX0 :: Tx_AControl0 :: tx1g_fifo_rst [13:13] */
#define TX0_TX_ACONTROL0_TX1G_FIFO_RST_MASK                        0x2000
#define TX0_TX_ACONTROL0_TX1G_FIFO_RST_ALIGN                       0
#define TX0_TX_ACONTROL0_TX1G_FIFO_RST_BITS                        1
#define TX0_TX_ACONTROL0_TX1G_FIFO_RST_SHIFT                       13

/* TX0 :: Tx_AControl0 :: gloopOutEn [12:12] */
#define TX0_TX_ACONTROL0_GLOOPOUTEN_MASK                           0x1000
#define TX0_TX_ACONTROL0_GLOOPOUTEN_ALIGN                          0
#define TX0_TX_ACONTROL0_GLOOPOUTEN_BITS                           1
#define TX0_TX_ACONTROL0_GLOOPOUTEN_SHIFT                          12

/* TX0 :: Tx_AControl0 :: reserved1 [11:09] */
#define TX0_TX_ACONTROL0_RESERVED1_MASK                            0x0e00
#define TX0_TX_ACONTROL0_RESERVED1_ALIGN                           0
#define TX0_TX_ACONTROL0_RESERVED1_BITS                            3
#define TX0_TX_ACONTROL0_RESERVED1_SHIFT                           9

/* TX0 :: Tx_AControl0 :: prbs_en [08:08] */
#define TX0_TX_ACONTROL0_PRBS_EN_MASK                              0x0100
#define TX0_TX_ACONTROL0_PRBS_EN_ALIGN                             0
#define TX0_TX_ACONTROL0_PRBS_EN_BITS                              1
#define TX0_TX_ACONTROL0_PRBS_EN_SHIFT                             8

/* TX0 :: Tx_AControl0 :: pckt_en [07:07] */
#define TX0_TX_ACONTROL0_PCKT_EN_MASK                              0x0080
#define TX0_TX_ACONTROL0_PCKT_EN_ALIGN                             0
#define TX0_TX_ACONTROL0_PCKT_EN_BITS                              1
#define TX0_TX_ACONTROL0_PCKT_EN_SHIFT                             7

/* TX0 :: Tx_AControl0 :: pckt_strt [06:06] */
#define TX0_TX_ACONTROL0_PCKT_STRT_MASK                            0x0040
#define TX0_TX_ACONTROL0_PCKT_STRT_ALIGN                           0
#define TX0_TX_ACONTROL0_PCKT_STRT_BITS                            1
#define TX0_TX_ACONTROL0_PCKT_STRT_SHIFT                           6

/* TX0 :: Tx_AControl0 :: txpol_flip [05:05] */
#define TX0_TX_ACONTROL0_TXPOL_FLIP_MASK                           0x0020
#define TX0_TX_ACONTROL0_TXPOL_FLIP_ALIGN                          0
#define TX0_TX_ACONTROL0_TXPOL_FLIP_BITS                           1
#define TX0_TX_ACONTROL0_TXPOL_FLIP_SHIFT                          5

/* TX0 :: Tx_AControl0 :: rtbi_flip [04:04] */
#define TX0_TX_ACONTROL0_RTBI_FLIP_MASK                            0x0010
#define TX0_TX_ACONTROL0_RTBI_FLIP_ALIGN                           0
#define TX0_TX_ACONTROL0_RTBI_FLIP_BITS                            1
#define TX0_TX_ACONTROL0_RTBI_FLIP_SHIFT                           4

/* TX0 :: Tx_AControl0 :: eden_r [03:03] */
#define TX0_TX_ACONTROL0_EDEN_R_MASK                               0x0008
#define TX0_TX_ACONTROL0_EDEN_R_ALIGN                              0
#define TX0_TX_ACONTROL0_EDEN_R_BITS                               1
#define TX0_TX_ACONTROL0_EDEN_R_SHIFT                              3

/* TX0 :: Tx_AControl0 :: eden_force_r [02:02] */
#define TX0_TX_ACONTROL0_EDEN_FORCE_R_MASK                         0x0004
#define TX0_TX_ACONTROL0_EDEN_FORCE_R_ALIGN                        0
#define TX0_TX_ACONTROL0_EDEN_FORCE_R_BITS                         1
#define TX0_TX_ACONTROL0_EDEN_FORCE_R_SHIFT                        2

/* TX0 :: Tx_AControl0 :: txpat_en [01:01] */
#define TX0_TX_ACONTROL0_TXPAT_EN_MASK                             0x0002
#define TX0_TX_ACONTROL0_TXPAT_EN_ALIGN                            0
#define TX0_TX_ACONTROL0_TXPAT_EN_BITS                             1
#define TX0_TX_ACONTROL0_TXPAT_EN_SHIFT                            1

/* TX0 :: Tx_AControl0 :: tx_mdata_en [00:00] */
#define TX0_TX_ACONTROL0_TX_MDATA_EN_MASK                          0x0001
#define TX0_TX_ACONTROL0_TX_MDATA_EN_ALIGN                         0
#define TX0_TX_ACONTROL0_TX_MDATA_EN_BITS                          1
#define TX0_TX_ACONTROL0_TX_MDATA_EN_SHIFT                         0


/****************************************************************************
 * TX0 :: Tx_mdata0
 ***************************************************************************/
/* TX0 :: Tx_mdata0 :: txTestMuxSel [15:13] */
#define TX0_TX_MDATA0_TXTESTMUXSEL_MASK                            0xe000
#define TX0_TX_MDATA0_TXTESTMUXSEL_ALIGN                           0
#define TX0_TX_MDATA0_TXTESTMUXSEL_BITS                            3
#define TX0_TX_MDATA0_TXTESTMUXSEL_SHIFT                           13

/* TX0 :: Tx_mdata0 :: rlfifo_tstsel [12:10] */
#define TX0_TX_MDATA0_RLFIFO_TSTSEL_MASK                           0x1c00
#define TX0_TX_MDATA0_RLFIFO_TSTSEL_ALIGN                          0
#define TX0_TX_MDATA0_RLFIFO_TSTSEL_BITS                           3
#define TX0_TX_MDATA0_RLFIFO_TSTSEL_SHIFT                          10

/* TX0 :: Tx_mdata0 :: TxMdioTstDataL [09:00] */
#define TX0_TX_MDATA0_TXMDIOTSTDATAL_MASK                          0x03ff
#define TX0_TX_MDATA0_TXMDIOTSTDATAL_ALIGN                         0
#define TX0_TX_MDATA0_TXMDIOTSTDATAL_BITS                          10
#define TX0_TX_MDATA0_TXMDIOTSTDATAL_SHIFT                         0


/****************************************************************************
 * TX0 :: Tx_mdata1
 ***************************************************************************/
/* TX0 :: Tx_mdata1 :: reserved0 [15:10] */
#define TX0_TX_MDATA1_RESERVED0_MASK                               0xfc00
#define TX0_TX_MDATA1_RESERVED0_ALIGN                              0
#define TX0_TX_MDATA1_RESERVED0_BITS                               6
#define TX0_TX_MDATA1_RESERVED0_SHIFT                              10

/* TX0 :: Tx_mdata1 :: TxMdioTstDataH [09:00] */
#define TX0_TX_MDATA1_TXMDIOTSTDATAH_MASK                          0x03ff
#define TX0_TX_MDATA1_TXMDIOTSTDATAH_ALIGN                         0
#define TX0_TX_MDATA1_TXMDIOTSTDATAH_BITS                          10
#define TX0_TX_MDATA1_TXMDIOTSTDATAH_SHIFT                         0


/****************************************************************************
 * TX0 :: Tx_AStatus1
 ***************************************************************************/
/* TX0 :: Tx_AStatus1 :: tx_id [15:14] */
#define TX0_TX_ASTATUS1_TX_ID_MASK                                 0xc000
#define TX0_TX_ASTATUS1_TX_ID_ALIGN                                0
#define TX0_TX_ASTATUS1_TX_ID_BITS                                 2
#define TX0_TX_ASTATUS1_TX_ID_SHIFT                                14

/* TX0 :: Tx_AStatus1 :: reserved0 [13:00] */
#define TX0_TX_ASTATUS1_RESERVED0_MASK                             0x3fff
#define TX0_TX_ASTATUS1_RESERVED0_ALIGN                            0
#define TX0_TX_ASTATUS1_RESERVED0_BITS                             14
#define TX0_TX_ASTATUS1_RESERVED0_SHIFT                            0


/****************************************************************************
 * TX0 :: Tx_BgVcm
 ***************************************************************************/
/* TX0 :: Tx_BgVcm :: id2c [15:13] */
#define TX0_TX_BGVCM_ID2C_MASK                                     0xe000
#define TX0_TX_BGVCM_ID2C_ALIGN                                    0
#define TX0_TX_BGVCM_ID2C_BITS                                     3
#define TX0_TX_BGVCM_ID2C_SHIFT                                    13

/* TX0 :: Tx_BgVcm :: refl_tx [12:12] */
#define TX0_TX_BGVCM_REFL_TX_MASK                                  0x1000
#define TX0_TX_BGVCM_REFL_TX_ALIGN                                 0
#define TX0_TX_BGVCM_REFL_TX_BITS                                  1
#define TX0_TX_BGVCM_REFL_TX_SHIFT                                 12

/* TX0 :: Tx_BgVcm :: refh_tx [11:11] */
#define TX0_TX_BGVCM_REFH_TX_MASK                                  0x0800
#define TX0_TX_BGVCM_REFH_TX_ALIGN                                 0
#define TX0_TX_BGVCM_REFH_TX_BITS                                  1
#define TX0_TX_BGVCM_REFH_TX_SHIFT                                 11

/* TX0 :: Tx_BgVcm :: newbias_en [10:10] */
#define TX0_TX_BGVCM_NEWBIAS_EN_MASK                               0x0400
#define TX0_TX_BGVCM_NEWBIAS_EN_ALIGN                              0
#define TX0_TX_BGVCM_NEWBIAS_EN_BITS                               1
#define TX0_TX_BGVCM_NEWBIAS_EN_SHIFT                              10

/* TX0 :: Tx_BgVcm :: drivermode [09:09] */
#define TX0_TX_BGVCM_DRIVERMODE_MASK                               0x0200
#define TX0_TX_BGVCM_DRIVERMODE_ALIGN                              0
#define TX0_TX_BGVCM_DRIVERMODE_BITS                               1
#define TX0_TX_BGVCM_DRIVERMODE_SHIFT                              9

/* TX0 :: Tx_BgVcm :: bddr_bgb [08:08] */
#define TX0_TX_BGVCM_BDDR_BGB_MASK                                 0x0100
#define TX0_TX_BGVCM_BDDR_BGB_ALIGN                                0
#define TX0_TX_BGVCM_BDDR_BGB_BITS                                 1
#define TX0_TX_BGVCM_BDDR_BGB_SHIFT                                8

/* TX0 :: Tx_BgVcm :: ticksel [07:06] */
#define TX0_TX_BGVCM_TICKSEL_MASK                                  0x00c0
#define TX0_TX_BGVCM_TICKSEL_ALIGN                                 0
#define TX0_TX_BGVCM_TICKSEL_BITS                                  2
#define TX0_TX_BGVCM_TICKSEL_SHIFT                                 6

/* TX0 :: Tx_BgVcm :: driver_vcm [05:04] */
#define TX0_TX_BGVCM_DRIVER_VCM_MASK                               0x0030
#define TX0_TX_BGVCM_DRIVER_VCM_ALIGN                              0
#define TX0_TX_BGVCM_DRIVER_VCM_BITS                               2
#define TX0_TX_BGVCM_DRIVER_VCM_SHIFT                              4

/* TX0 :: Tx_BgVcm :: tx_sel_halfrate [03:03] */
#define TX0_TX_BGVCM_TX_SEL_HALFRATE_MASK                          0x0008
#define TX0_TX_BGVCM_TX_SEL_HALFRATE_ALIGN                         0
#define TX0_TX_BGVCM_TX_SEL_HALFRATE_BITS                          1
#define TX0_TX_BGVCM_TX_SEL_HALFRATE_SHIFT                         3

/* TX0 :: Tx_BgVcm :: ifullspd [02:00] */
#define TX0_TX_BGVCM_IFULLSPD_MASK                                 0x0007
#define TX0_TX_BGVCM_IFULLSPD_ALIGN                                0
#define TX0_TX_BGVCM_IFULLSPD_BITS                                 3
#define TX0_TX_BGVCM_IFULLSPD_SHIFT                                0


/****************************************************************************
 * TX0 :: Tx_ibuff_1T2T
 ***************************************************************************/
/* TX0 :: Tx_ibuff_1T2T :: icbuf1t [15:14] */
#define TX0_TX_IBUFF_1T2T_ICBUF1T_MASK                             0xc000
#define TX0_TX_IBUFF_1T2T_ICBUF1T_ALIGN                            0
#define TX0_TX_IBUFF_1T2T_ICBUF1T_BITS                             2
#define TX0_TX_IBUFF_1T2T_ICBUF1T_SHIFT                            14

/* TX0 :: Tx_ibuff_1T2T :: icbuf2t [13:11] */
#define TX0_TX_IBUFF_1T2T_ICBUF2T_MASK                             0x3800
#define TX0_TX_IBUFF_1T2T_ICBUF2T_ALIGN                            0
#define TX0_TX_IBUFF_1T2T_ICBUF2T_BITS                             3
#define TX0_TX_IBUFF_1T2T_ICBUF2T_SHIFT                            11

/* TX0 :: Tx_ibuff_1T2T :: imin_predrv [10:10] */
#define TX0_TX_IBUFF_1T2T_IMIN_PREDRV_MASK                         0x0400
#define TX0_TX_IBUFF_1T2T_IMIN_PREDRV_ALIGN                        0
#define TX0_TX_IBUFF_1T2T_IMIN_PREDRV_BITS                         1
#define TX0_TX_IBUFF_1T2T_IMIN_PREDRV_SHIFT                        10

/* TX0 :: Tx_ibuff_1T2T :: imax_predrv [09:09] */
#define TX0_TX_IBUFF_1T2T_IMAX_PREDRV_MASK                         0x0200
#define TX0_TX_IBUFF_1T2T_IMAX_PREDRV_ALIGN                        0
#define TX0_TX_IBUFF_1T2T_IMAX_PREDRV_BITS                         1
#define TX0_TX_IBUFF_1T2T_IMAX_PREDRV_SHIFT                        9

/* TX0 :: Tx_ibuff_1T2T :: imode_predrv [08:08] */
#define TX0_TX_IBUFF_1T2T_IMODE_PREDRV_MASK                        0x0100
#define TX0_TX_IBUFF_1T2T_IMODE_PREDRV_ALIGN                       0
#define TX0_TX_IBUFF_1T2T_IMODE_PREDRV_BITS                        1
#define TX0_TX_IBUFF_1T2T_IMODE_PREDRV_SHIFT                       8

/* TX0 :: Tx_ibuff_1T2T :: i21mux [07:05] */
#define TX0_TX_IBUFF_1T2T_I21MUX_MASK                              0x00e0
#define TX0_TX_IBUFF_1T2T_I21MUX_ALIGN                             0
#define TX0_TX_IBUFF_1T2T_I21MUX_BITS                              3
#define TX0_TX_IBUFF_1T2T_I21MUX_SHIFT                             5

/* TX0 :: Tx_ibuff_1T2T :: imin_drvr [04:04] */
#define TX0_TX_IBUFF_1T2T_IMIN_DRVR_MASK                           0x0010
#define TX0_TX_IBUFF_1T2T_IMIN_DRVR_ALIGN                          0
#define TX0_TX_IBUFF_1T2T_IMIN_DRVR_BITS                           1
#define TX0_TX_IBUFF_1T2T_IMIN_DRVR_SHIFT                          4

/* TX0 :: Tx_ibuff_1T2T :: imax_drvr [03:03] */
#define TX0_TX_IBUFF_1T2T_IMAX_DRVR_MASK                           0x0008
#define TX0_TX_IBUFF_1T2T_IMAX_DRVR_ALIGN                          0
#define TX0_TX_IBUFF_1T2T_IMAX_DRVR_BITS                           1
#define TX0_TX_IBUFF_1T2T_IMAX_DRVR_SHIFT                          3

/* TX0 :: Tx_ibuff_1T2T :: imode_drvr [02:02] */
#define TX0_TX_IBUFF_1T2T_IMODE_DRVR_MASK                          0x0004
#define TX0_TX_IBUFF_1T2T_IMODE_DRVR_ALIGN                         0
#define TX0_TX_IBUFF_1T2T_IMODE_DRVR_BITS                          1
#define TX0_TX_IBUFF_1T2T_IMODE_DRVR_SHIFT                         2

/* TX0 :: Tx_ibuff_1T2T :: reserved0 [01:00] */
#define TX0_TX_IBUFF_1T2T_RESERVED0_MASK                           0x0003
#define TX0_TX_IBUFF_1T2T_RESERVED0_ALIGN                          0
#define TX0_TX_IBUFF_1T2T_RESERVED0_BITS                           2
#define TX0_TX_IBUFF_1T2T_RESERVED0_SHIFT                          0


/****************************************************************************
 * TX0 :: Tx_Driver
 ***************************************************************************/
/* TX0 :: Tx_Driver :: preemphasis_post [15:12] */
#define TX0_TX_DRIVER_PREEMPHASIS_POST_MASK                        0xf000
#define TX0_TX_DRIVER_PREEMPHASIS_POST_ALIGN                       0
#define TX0_TX_DRIVER_PREEMPHASIS_POST_BITS                        4
#define TX0_TX_DRIVER_PREEMPHASIS_POST_SHIFT                       12

/* TX0 :: Tx_Driver :: Idriver [11:08] */
#define TX0_TX_DRIVER_IDRIVER_MASK                                 0x0f00
#define TX0_TX_DRIVER_IDRIVER_ALIGN                                0
#define TX0_TX_DRIVER_IDRIVER_BITS                                 4
#define TX0_TX_DRIVER_IDRIVER_SHIFT                                8

/* TX0 :: Tx_Driver :: Ipredriver [07:04] */
#define TX0_TX_DRIVER_IPREDRIVER_MASK                              0x00f0
#define TX0_TX_DRIVER_IPREDRIVER_ALIGN                             0
#define TX0_TX_DRIVER_IPREDRIVER_BITS                              4
#define TX0_TX_DRIVER_IPREDRIVER_SHIFT                             4

/* TX0 :: Tx_Driver :: preemphasis_pre [03:01] */
#define TX0_TX_DRIVER_PREEMPHASIS_PRE_MASK                         0x000e
#define TX0_TX_DRIVER_PREEMPHASIS_PRE_ALIGN                        0
#define TX0_TX_DRIVER_PREEMPHASIS_PRE_BITS                         3
#define TX0_TX_DRIVER_PREEMPHASIS_PRE_SHIFT                        1

/* TX0 :: Tx_Driver :: icbuf1t0 [00:00] */
#define TX0_TX_DRIVER_ICBUF1T0_MASK                                0x0001
#define TX0_TX_DRIVER_ICBUF1T0_ALIGN                               0
#define TX0_TX_DRIVER_ICBUF1T0_BITS                                1
#define TX0_TX_DRIVER_ICBUF1T0_SHIFT                               0


/****************************************************************************
 * XGXS16G_USER_TX1
 ***************************************************************************/
/****************************************************************************
 * TX1 :: Tx_AStatus0
 ***************************************************************************/
/* TX1 :: Tx_AStatus0 :: reserved0 [15:03] */
#define TX1_TX_ASTATUS0_RESERVED0_MASK                             0xfff8
#define TX1_TX_ASTATUS0_RESERVED0_ALIGN                            0
#define TX1_TX_ASTATUS0_RESERVED0_BITS                             13
#define TX1_TX_ASTATUS0_RESERVED0_SHIFT                            3

/* TX1 :: Tx_AStatus0 :: tx_gloopback [02:02] */
#define TX1_TX_ASTATUS0_TX_GLOOPBACK_MASK                          0x0004
#define TX1_TX_ASTATUS0_TX_GLOOPBACK_ALIGN                         0
#define TX1_TX_ASTATUS0_TX_GLOOPBACK_BITS                          1
#define TX1_TX_ASTATUS0_TX_GLOOPBACK_SHIFT                         2

/* TX1 :: Tx_AStatus0 :: rltxferr [01:01] */
#define TX1_TX_ASTATUS0_RLTXFERR_MASK                              0x0002
#define TX1_TX_ASTATUS0_RLTXFERR_ALIGN                             0
#define TX1_TX_ASTATUS0_RLTXFERR_BITS                              1
#define TX1_TX_ASTATUS0_RLTXFERR_SHIFT                             1

/* TX1 :: Tx_AStatus0 :: txferr [00:00] */
#define TX1_TX_ASTATUS0_TXFERR_MASK                                0x0001
#define TX1_TX_ASTATUS0_TXFERR_ALIGN                               0
#define TX1_TX_ASTATUS0_TXFERR_BITS                                1
#define TX1_TX_ASTATUS0_TXFERR_SHIFT                               0


/****************************************************************************
 * TX1 :: Tx_AControl0
 ***************************************************************************/
/* TX1 :: Tx_AControl0 :: reserved0 [15:15] */
#define TX1_TX_ACONTROL0_RESERVED0_MASK                            0x8000
#define TX1_TX_ACONTROL0_RESERVED0_ALIGN                           0
#define TX1_TX_ACONTROL0_RESERVED0_BITS                            1
#define TX1_TX_ACONTROL0_RESERVED0_SHIFT                           15

/* TX1 :: Tx_AControl0 :: force_txclk [14:14] */
#define TX1_TX_ACONTROL0_FORCE_TXCLK_MASK                          0x4000
#define TX1_TX_ACONTROL0_FORCE_TXCLK_ALIGN                         0
#define TX1_TX_ACONTROL0_FORCE_TXCLK_BITS                          1
#define TX1_TX_ACONTROL0_FORCE_TXCLK_SHIFT                         14

/* TX1 :: Tx_AControl0 :: tx1g_fifo_rst [13:13] */
#define TX1_TX_ACONTROL0_TX1G_FIFO_RST_MASK                        0x2000
#define TX1_TX_ACONTROL0_TX1G_FIFO_RST_ALIGN                       0
#define TX1_TX_ACONTROL0_TX1G_FIFO_RST_BITS                        1
#define TX1_TX_ACONTROL0_TX1G_FIFO_RST_SHIFT                       13

/* TX1 :: Tx_AControl0 :: gloopOutEn [12:12] */
#define TX1_TX_ACONTROL0_GLOOPOUTEN_MASK                           0x1000
#define TX1_TX_ACONTROL0_GLOOPOUTEN_ALIGN                          0
#define TX1_TX_ACONTROL0_GLOOPOUTEN_BITS                           1
#define TX1_TX_ACONTROL0_GLOOPOUTEN_SHIFT                          12

/* TX1 :: Tx_AControl0 :: reserved1 [11:09] */
#define TX1_TX_ACONTROL0_RESERVED1_MASK                            0x0e00
#define TX1_TX_ACONTROL0_RESERVED1_ALIGN                           0
#define TX1_TX_ACONTROL0_RESERVED1_BITS                            3
#define TX1_TX_ACONTROL0_RESERVED1_SHIFT                           9

/* TX1 :: Tx_AControl0 :: prbs_en [08:08] */
#define TX1_TX_ACONTROL0_PRBS_EN_MASK                              0x0100
#define TX1_TX_ACONTROL0_PRBS_EN_ALIGN                             0
#define TX1_TX_ACONTROL0_PRBS_EN_BITS                              1
#define TX1_TX_ACONTROL0_PRBS_EN_SHIFT                             8

/* TX1 :: Tx_AControl0 :: pckt_en [07:07] */
#define TX1_TX_ACONTROL0_PCKT_EN_MASK                              0x0080
#define TX1_TX_ACONTROL0_PCKT_EN_ALIGN                             0
#define TX1_TX_ACONTROL0_PCKT_EN_BITS                              1
#define TX1_TX_ACONTROL0_PCKT_EN_SHIFT                             7

/* TX1 :: Tx_AControl0 :: pckt_strt [06:06] */
#define TX1_TX_ACONTROL0_PCKT_STRT_MASK                            0x0040
#define TX1_TX_ACONTROL0_PCKT_STRT_ALIGN                           0
#define TX1_TX_ACONTROL0_PCKT_STRT_BITS                            1
#define TX1_TX_ACONTROL0_PCKT_STRT_SHIFT                           6

/* TX1 :: Tx_AControl0 :: txpol_flip [05:05] */
#define TX1_TX_ACONTROL0_TXPOL_FLIP_MASK                           0x0020
#define TX1_TX_ACONTROL0_TXPOL_FLIP_ALIGN                          0
#define TX1_TX_ACONTROL0_TXPOL_FLIP_BITS                           1
#define TX1_TX_ACONTROL0_TXPOL_FLIP_SHIFT                          5

/* TX1 :: Tx_AControl0 :: rtbi_flip [04:04] */
#define TX1_TX_ACONTROL0_RTBI_FLIP_MASK                            0x0010
#define TX1_TX_ACONTROL0_RTBI_FLIP_ALIGN                           0
#define TX1_TX_ACONTROL0_RTBI_FLIP_BITS                            1
#define TX1_TX_ACONTROL0_RTBI_FLIP_SHIFT                           4

/* TX1 :: Tx_AControl0 :: eden_r [03:03] */
#define TX1_TX_ACONTROL0_EDEN_R_MASK                               0x0008
#define TX1_TX_ACONTROL0_EDEN_R_ALIGN                              0
#define TX1_TX_ACONTROL0_EDEN_R_BITS                               1
#define TX1_TX_ACONTROL0_EDEN_R_SHIFT                              3

/* TX1 :: Tx_AControl0 :: eden_force_r [02:02] */
#define TX1_TX_ACONTROL0_EDEN_FORCE_R_MASK                         0x0004
#define TX1_TX_ACONTROL0_EDEN_FORCE_R_ALIGN                        0
#define TX1_TX_ACONTROL0_EDEN_FORCE_R_BITS                         1
#define TX1_TX_ACONTROL0_EDEN_FORCE_R_SHIFT                        2

/* TX1 :: Tx_AControl0 :: txpat_en [01:01] */
#define TX1_TX_ACONTROL0_TXPAT_EN_MASK                             0x0002
#define TX1_TX_ACONTROL0_TXPAT_EN_ALIGN                            0
#define TX1_TX_ACONTROL0_TXPAT_EN_BITS                             1
#define TX1_TX_ACONTROL0_TXPAT_EN_SHIFT                            1

/* TX1 :: Tx_AControl0 :: tx_mdata_en [00:00] */
#define TX1_TX_ACONTROL0_TX_MDATA_EN_MASK                          0x0001
#define TX1_TX_ACONTROL0_TX_MDATA_EN_ALIGN                         0
#define TX1_TX_ACONTROL0_TX_MDATA_EN_BITS                          1
#define TX1_TX_ACONTROL0_TX_MDATA_EN_SHIFT                         0


/****************************************************************************
 * TX1 :: Tx_mdata0
 ***************************************************************************/
/* TX1 :: Tx_mdata0 :: txTestMuxSel [15:13] */
#define TX1_TX_MDATA0_TXTESTMUXSEL_MASK                            0xe000
#define TX1_TX_MDATA0_TXTESTMUXSEL_ALIGN                           0
#define TX1_TX_MDATA0_TXTESTMUXSEL_BITS                            3
#define TX1_TX_MDATA0_TXTESTMUXSEL_SHIFT                           13

/* TX1 :: Tx_mdata0 :: rlfifo_tstsel [12:10] */
#define TX1_TX_MDATA0_RLFIFO_TSTSEL_MASK                           0x1c00
#define TX1_TX_MDATA0_RLFIFO_TSTSEL_ALIGN                          0
#define TX1_TX_MDATA0_RLFIFO_TSTSEL_BITS                           3
#define TX1_TX_MDATA0_RLFIFO_TSTSEL_SHIFT                          10

/* TX1 :: Tx_mdata0 :: TxMdioTstDataL [09:00] */
#define TX1_TX_MDATA0_TXMDIOTSTDATAL_MASK                          0x03ff
#define TX1_TX_MDATA0_TXMDIOTSTDATAL_ALIGN                         0
#define TX1_TX_MDATA0_TXMDIOTSTDATAL_BITS                          10
#define TX1_TX_MDATA0_TXMDIOTSTDATAL_SHIFT                         0


/****************************************************************************
 * TX1 :: Tx_mdata1
 ***************************************************************************/
/* TX1 :: Tx_mdata1 :: reserved0 [15:10] */
#define TX1_TX_MDATA1_RESERVED0_MASK                               0xfc00
#define TX1_TX_MDATA1_RESERVED0_ALIGN                              0
#define TX1_TX_MDATA1_RESERVED0_BITS                               6
#define TX1_TX_MDATA1_RESERVED0_SHIFT                              10

/* TX1 :: Tx_mdata1 :: TxMdioTstDataH [09:00] */
#define TX1_TX_MDATA1_TXMDIOTSTDATAH_MASK                          0x03ff
#define TX1_TX_MDATA1_TXMDIOTSTDATAH_ALIGN                         0
#define TX1_TX_MDATA1_TXMDIOTSTDATAH_BITS                          10
#define TX1_TX_MDATA1_TXMDIOTSTDATAH_SHIFT                         0


/****************************************************************************
 * TX1 :: Tx_AStatus1
 ***************************************************************************/
/* TX1 :: Tx_AStatus1 :: tx_id [15:14] */
#define TX1_TX_ASTATUS1_TX_ID_MASK                                 0xc000
#define TX1_TX_ASTATUS1_TX_ID_ALIGN                                0
#define TX1_TX_ASTATUS1_TX_ID_BITS                                 2
#define TX1_TX_ASTATUS1_TX_ID_SHIFT                                14

/* TX1 :: Tx_AStatus1 :: reserved0 [13:00] */
#define TX1_TX_ASTATUS1_RESERVED0_MASK                             0x3fff
#define TX1_TX_ASTATUS1_RESERVED0_ALIGN                            0
#define TX1_TX_ASTATUS1_RESERVED0_BITS                             14
#define TX1_TX_ASTATUS1_RESERVED0_SHIFT                            0


/****************************************************************************
 * TX1 :: Tx_BgVcm
 ***************************************************************************/
/* TX1 :: Tx_BgVcm :: id2c [15:13] */
#define TX1_TX_BGVCM_ID2C_MASK                                     0xe000
#define TX1_TX_BGVCM_ID2C_ALIGN                                    0
#define TX1_TX_BGVCM_ID2C_BITS                                     3
#define TX1_TX_BGVCM_ID2C_SHIFT                                    13

/* TX1 :: Tx_BgVcm :: refl_tx [12:12] */
#define TX1_TX_BGVCM_REFL_TX_MASK                                  0x1000
#define TX1_TX_BGVCM_REFL_TX_ALIGN                                 0
#define TX1_TX_BGVCM_REFL_TX_BITS                                  1
#define TX1_TX_BGVCM_REFL_TX_SHIFT                                 12

/* TX1 :: Tx_BgVcm :: refh_tx [11:11] */
#define TX1_TX_BGVCM_REFH_TX_MASK                                  0x0800
#define TX1_TX_BGVCM_REFH_TX_ALIGN                                 0
#define TX1_TX_BGVCM_REFH_TX_BITS                                  1
#define TX1_TX_BGVCM_REFH_TX_SHIFT                                 11

/* TX1 :: Tx_BgVcm :: newbias_en [10:10] */
#define TX1_TX_BGVCM_NEWBIAS_EN_MASK                               0x0400
#define TX1_TX_BGVCM_NEWBIAS_EN_ALIGN                              0
#define TX1_TX_BGVCM_NEWBIAS_EN_BITS                               1
#define TX1_TX_BGVCM_NEWBIAS_EN_SHIFT                              10

/* TX1 :: Tx_BgVcm :: drivermode [09:09] */
#define TX1_TX_BGVCM_DRIVERMODE_MASK                               0x0200
#define TX1_TX_BGVCM_DRIVERMODE_ALIGN                              0
#define TX1_TX_BGVCM_DRIVERMODE_BITS                               1
#define TX1_TX_BGVCM_DRIVERMODE_SHIFT                              9

/* TX1 :: Tx_BgVcm :: bddr_bgb [08:08] */
#define TX1_TX_BGVCM_BDDR_BGB_MASK                                 0x0100
#define TX1_TX_BGVCM_BDDR_BGB_ALIGN                                0
#define TX1_TX_BGVCM_BDDR_BGB_BITS                                 1
#define TX1_TX_BGVCM_BDDR_BGB_SHIFT                                8

/* TX1 :: Tx_BgVcm :: ticksel [07:06] */
#define TX1_TX_BGVCM_TICKSEL_MASK                                  0x00c0
#define TX1_TX_BGVCM_TICKSEL_ALIGN                                 0
#define TX1_TX_BGVCM_TICKSEL_BITS                                  2
#define TX1_TX_BGVCM_TICKSEL_SHIFT                                 6

/* TX1 :: Tx_BgVcm :: driver_vcm [05:04] */
#define TX1_TX_BGVCM_DRIVER_VCM_MASK                               0x0030
#define TX1_TX_BGVCM_DRIVER_VCM_ALIGN                              0
#define TX1_TX_BGVCM_DRIVER_VCM_BITS                               2
#define TX1_TX_BGVCM_DRIVER_VCM_SHIFT                              4

/* TX1 :: Tx_BgVcm :: tx_sel_halfrate [03:03] */
#define TX1_TX_BGVCM_TX_SEL_HALFRATE_MASK                          0x0008
#define TX1_TX_BGVCM_TX_SEL_HALFRATE_ALIGN                         0
#define TX1_TX_BGVCM_TX_SEL_HALFRATE_BITS                          1
#define TX1_TX_BGVCM_TX_SEL_HALFRATE_SHIFT                         3

/* TX1 :: Tx_BgVcm :: ifullspd [02:00] */
#define TX1_TX_BGVCM_IFULLSPD_MASK                                 0x0007
#define TX1_TX_BGVCM_IFULLSPD_ALIGN                                0
#define TX1_TX_BGVCM_IFULLSPD_BITS                                 3
#define TX1_TX_BGVCM_IFULLSPD_SHIFT                                0


/****************************************************************************
 * TX1 :: Tx_ibuff_1T2T
 ***************************************************************************/
/* TX1 :: Tx_ibuff_1T2T :: icbuf1t [15:14] */
#define TX1_TX_IBUFF_1T2T_ICBUF1T_MASK                             0xc000
#define TX1_TX_IBUFF_1T2T_ICBUF1T_ALIGN                            0
#define TX1_TX_IBUFF_1T2T_ICBUF1T_BITS                             2
#define TX1_TX_IBUFF_1T2T_ICBUF1T_SHIFT                            14

/* TX1 :: Tx_ibuff_1T2T :: icbuf2t [13:11] */
#define TX1_TX_IBUFF_1T2T_ICBUF2T_MASK                             0x3800
#define TX1_TX_IBUFF_1T2T_ICBUF2T_ALIGN                            0
#define TX1_TX_IBUFF_1T2T_ICBUF2T_BITS                             3
#define TX1_TX_IBUFF_1T2T_ICBUF2T_SHIFT                            11

/* TX1 :: Tx_ibuff_1T2T :: imin_predrv [10:10] */
#define TX1_TX_IBUFF_1T2T_IMIN_PREDRV_MASK                         0x0400
#define TX1_TX_IBUFF_1T2T_IMIN_PREDRV_ALIGN                        0
#define TX1_TX_IBUFF_1T2T_IMIN_PREDRV_BITS                         1
#define TX1_TX_IBUFF_1T2T_IMIN_PREDRV_SHIFT                        10

/* TX1 :: Tx_ibuff_1T2T :: imax_predrv [09:09] */
#define TX1_TX_IBUFF_1T2T_IMAX_PREDRV_MASK                         0x0200
#define TX1_TX_IBUFF_1T2T_IMAX_PREDRV_ALIGN                        0
#define TX1_TX_IBUFF_1T2T_IMAX_PREDRV_BITS                         1
#define TX1_TX_IBUFF_1T2T_IMAX_PREDRV_SHIFT                        9

/* TX1 :: Tx_ibuff_1T2T :: imode_predrv [08:08] */
#define TX1_TX_IBUFF_1T2T_IMODE_PREDRV_MASK                        0x0100
#define TX1_TX_IBUFF_1T2T_IMODE_PREDRV_ALIGN                       0
#define TX1_TX_IBUFF_1T2T_IMODE_PREDRV_BITS                        1
#define TX1_TX_IBUFF_1T2T_IMODE_PREDRV_SHIFT                       8

/* TX1 :: Tx_ibuff_1T2T :: i21mux [07:05] */
#define TX1_TX_IBUFF_1T2T_I21MUX_MASK                              0x00e0
#define TX1_TX_IBUFF_1T2T_I21MUX_ALIGN                             0
#define TX1_TX_IBUFF_1T2T_I21MUX_BITS                              3
#define TX1_TX_IBUFF_1T2T_I21MUX_SHIFT                             5

/* TX1 :: Tx_ibuff_1T2T :: imin_drvr [04:04] */
#define TX1_TX_IBUFF_1T2T_IMIN_DRVR_MASK                           0x0010
#define TX1_TX_IBUFF_1T2T_IMIN_DRVR_ALIGN                          0
#define TX1_TX_IBUFF_1T2T_IMIN_DRVR_BITS                           1
#define TX1_TX_IBUFF_1T2T_IMIN_DRVR_SHIFT                          4

/* TX1 :: Tx_ibuff_1T2T :: imax_drvr [03:03] */
#define TX1_TX_IBUFF_1T2T_IMAX_DRVR_MASK                           0x0008
#define TX1_TX_IBUFF_1T2T_IMAX_DRVR_ALIGN                          0
#define TX1_TX_IBUFF_1T2T_IMAX_DRVR_BITS                           1
#define TX1_TX_IBUFF_1T2T_IMAX_DRVR_SHIFT                          3

/* TX1 :: Tx_ibuff_1T2T :: imode_drvr [02:02] */
#define TX1_TX_IBUFF_1T2T_IMODE_DRVR_MASK                          0x0004
#define TX1_TX_IBUFF_1T2T_IMODE_DRVR_ALIGN                         0
#define TX1_TX_IBUFF_1T2T_IMODE_DRVR_BITS                          1
#define TX1_TX_IBUFF_1T2T_IMODE_DRVR_SHIFT                         2

/* TX1 :: Tx_ibuff_1T2T :: reserved0 [01:00] */
#define TX1_TX_IBUFF_1T2T_RESERVED0_MASK                           0x0003
#define TX1_TX_IBUFF_1T2T_RESERVED0_ALIGN                          0
#define TX1_TX_IBUFF_1T2T_RESERVED0_BITS                           2
#define TX1_TX_IBUFF_1T2T_RESERVED0_SHIFT                          0


/****************************************************************************
 * TX1 :: Tx_Driver
 ***************************************************************************/
/* TX1 :: Tx_Driver :: preemphasis_post [15:12] */
#define TX1_TX_DRIVER_PREEMPHASIS_POST_MASK                        0xf000
#define TX1_TX_DRIVER_PREEMPHASIS_POST_ALIGN                       0
#define TX1_TX_DRIVER_PREEMPHASIS_POST_BITS                        4
#define TX1_TX_DRIVER_PREEMPHASIS_POST_SHIFT                       12

/* TX1 :: Tx_Driver :: Idriver [11:08] */
#define TX1_TX_DRIVER_IDRIVER_MASK                                 0x0f00
#define TX1_TX_DRIVER_IDRIVER_ALIGN                                0
#define TX1_TX_DRIVER_IDRIVER_BITS                                 4
#define TX1_TX_DRIVER_IDRIVER_SHIFT                                8

/* TX1 :: Tx_Driver :: Ipredriver [07:04] */
#define TX1_TX_DRIVER_IPREDRIVER_MASK                              0x00f0
#define TX1_TX_DRIVER_IPREDRIVER_ALIGN                             0
#define TX1_TX_DRIVER_IPREDRIVER_BITS                              4
#define TX1_TX_DRIVER_IPREDRIVER_SHIFT                             4

/* TX1 :: Tx_Driver :: preemphasis_pre [03:01] */
#define TX1_TX_DRIVER_PREEMPHASIS_PRE_MASK                         0x000e
#define TX1_TX_DRIVER_PREEMPHASIS_PRE_ALIGN                        0
#define TX1_TX_DRIVER_PREEMPHASIS_PRE_BITS                         3
#define TX1_TX_DRIVER_PREEMPHASIS_PRE_SHIFT                        1

/* TX1 :: Tx_Driver :: icbuf1t0 [00:00] */
#define TX1_TX_DRIVER_ICBUF1T0_MASK                                0x0001
#define TX1_TX_DRIVER_ICBUF1T0_ALIGN                               0
#define TX1_TX_DRIVER_ICBUF1T0_BITS                                1
#define TX1_TX_DRIVER_ICBUF1T0_SHIFT                               0


/****************************************************************************
 * XGXS16G_USER_TX2
 ***************************************************************************/
/****************************************************************************
 * TX2 :: Tx_AStatus0
 ***************************************************************************/
/* TX2 :: Tx_AStatus0 :: reserved0 [15:03] */
#define TX2_TX_ASTATUS0_RESERVED0_MASK                             0xfff8
#define TX2_TX_ASTATUS0_RESERVED0_ALIGN                            0
#define TX2_TX_ASTATUS0_RESERVED0_BITS                             13
#define TX2_TX_ASTATUS0_RESERVED0_SHIFT                            3

/* TX2 :: Tx_AStatus0 :: tx_gloopback [02:02] */
#define TX2_TX_ASTATUS0_TX_GLOOPBACK_MASK                          0x0004
#define TX2_TX_ASTATUS0_TX_GLOOPBACK_ALIGN                         0
#define TX2_TX_ASTATUS0_TX_GLOOPBACK_BITS                          1
#define TX2_TX_ASTATUS0_TX_GLOOPBACK_SHIFT                         2

/* TX2 :: Tx_AStatus0 :: rltxferr [01:01] */
#define TX2_TX_ASTATUS0_RLTXFERR_MASK                              0x0002
#define TX2_TX_ASTATUS0_RLTXFERR_ALIGN                             0
#define TX2_TX_ASTATUS0_RLTXFERR_BITS                              1
#define TX2_TX_ASTATUS0_RLTXFERR_SHIFT                             1

/* TX2 :: Tx_AStatus0 :: txferr [00:00] */
#define TX2_TX_ASTATUS0_TXFERR_MASK                                0x0001
#define TX2_TX_ASTATUS0_TXFERR_ALIGN                               0
#define TX2_TX_ASTATUS0_TXFERR_BITS                                1
#define TX2_TX_ASTATUS0_TXFERR_SHIFT                               0


/****************************************************************************
 * TX2 :: Tx_AControl0
 ***************************************************************************/
/* TX2 :: Tx_AControl0 :: reserved0 [15:15] */
#define TX2_TX_ACONTROL0_RESERVED0_MASK                            0x8000
#define TX2_TX_ACONTROL0_RESERVED0_ALIGN                           0
#define TX2_TX_ACONTROL0_RESERVED0_BITS                            1
#define TX2_TX_ACONTROL0_RESERVED0_SHIFT                           15

/* TX2 :: Tx_AControl0 :: force_txclk [14:14] */
#define TX2_TX_ACONTROL0_FORCE_TXCLK_MASK                          0x4000
#define TX2_TX_ACONTROL0_FORCE_TXCLK_ALIGN                         0
#define TX2_TX_ACONTROL0_FORCE_TXCLK_BITS                          1
#define TX2_TX_ACONTROL0_FORCE_TXCLK_SHIFT                         14

/* TX2 :: Tx_AControl0 :: tx1g_fifo_rst [13:13] */
#define TX2_TX_ACONTROL0_TX1G_FIFO_RST_MASK                        0x2000
#define TX2_TX_ACONTROL0_TX1G_FIFO_RST_ALIGN                       0
#define TX2_TX_ACONTROL0_TX1G_FIFO_RST_BITS                        1
#define TX2_TX_ACONTROL0_TX1G_FIFO_RST_SHIFT                       13

/* TX2 :: Tx_AControl0 :: gloopOutEn [12:12] */
#define TX2_TX_ACONTROL0_GLOOPOUTEN_MASK                           0x1000
#define TX2_TX_ACONTROL0_GLOOPOUTEN_ALIGN                          0
#define TX2_TX_ACONTROL0_GLOOPOUTEN_BITS                           1
#define TX2_TX_ACONTROL0_GLOOPOUTEN_SHIFT                          12

/* TX2 :: Tx_AControl0 :: reserved1 [11:09] */
#define TX2_TX_ACONTROL0_RESERVED1_MASK                            0x0e00
#define TX2_TX_ACONTROL0_RESERVED1_ALIGN                           0
#define TX2_TX_ACONTROL0_RESERVED1_BITS                            3
#define TX2_TX_ACONTROL0_RESERVED1_SHIFT                           9

/* TX2 :: Tx_AControl0 :: prbs_en [08:08] */
#define TX2_TX_ACONTROL0_PRBS_EN_MASK                              0x0100
#define TX2_TX_ACONTROL0_PRBS_EN_ALIGN                             0
#define TX2_TX_ACONTROL0_PRBS_EN_BITS                              1
#define TX2_TX_ACONTROL0_PRBS_EN_SHIFT                             8

/* TX2 :: Tx_AControl0 :: pckt_en [07:07] */
#define TX2_TX_ACONTROL0_PCKT_EN_MASK                              0x0080
#define TX2_TX_ACONTROL0_PCKT_EN_ALIGN                             0
#define TX2_TX_ACONTROL0_PCKT_EN_BITS                              1
#define TX2_TX_ACONTROL0_PCKT_EN_SHIFT                             7

/* TX2 :: Tx_AControl0 :: pckt_strt [06:06] */
#define TX2_TX_ACONTROL0_PCKT_STRT_MASK                            0x0040
#define TX2_TX_ACONTROL0_PCKT_STRT_ALIGN                           0
#define TX2_TX_ACONTROL0_PCKT_STRT_BITS                            1
#define TX2_TX_ACONTROL0_PCKT_STRT_SHIFT                           6

/* TX2 :: Tx_AControl0 :: txpol_flip [05:05] */
#define TX2_TX_ACONTROL0_TXPOL_FLIP_MASK                           0x0020
#define TX2_TX_ACONTROL0_TXPOL_FLIP_ALIGN                          0
#define TX2_TX_ACONTROL0_TXPOL_FLIP_BITS                           1
#define TX2_TX_ACONTROL0_TXPOL_FLIP_SHIFT                          5

/* TX2 :: Tx_AControl0 :: rtbi_flip [04:04] */
#define TX2_TX_ACONTROL0_RTBI_FLIP_MASK                            0x0010
#define TX2_TX_ACONTROL0_RTBI_FLIP_ALIGN                           0
#define TX2_TX_ACONTROL0_RTBI_FLIP_BITS                            1
#define TX2_TX_ACONTROL0_RTBI_FLIP_SHIFT                           4

/* TX2 :: Tx_AControl0 :: eden_r [03:03] */
#define TX2_TX_ACONTROL0_EDEN_R_MASK                               0x0008
#define TX2_TX_ACONTROL0_EDEN_R_ALIGN                              0
#define TX2_TX_ACONTROL0_EDEN_R_BITS                               1
#define TX2_TX_ACONTROL0_EDEN_R_SHIFT                              3

/* TX2 :: Tx_AControl0 :: eden_force_r [02:02] */
#define TX2_TX_ACONTROL0_EDEN_FORCE_R_MASK                         0x0004
#define TX2_TX_ACONTROL0_EDEN_FORCE_R_ALIGN                        0
#define TX2_TX_ACONTROL0_EDEN_FORCE_R_BITS                         1
#define TX2_TX_ACONTROL0_EDEN_FORCE_R_SHIFT                        2

/* TX2 :: Tx_AControl0 :: txpat_en [01:01] */
#define TX2_TX_ACONTROL0_TXPAT_EN_MASK                             0x0002
#define TX2_TX_ACONTROL0_TXPAT_EN_ALIGN                            0
#define TX2_TX_ACONTROL0_TXPAT_EN_BITS                             1
#define TX2_TX_ACONTROL0_TXPAT_EN_SHIFT                            1

/* TX2 :: Tx_AControl0 :: tx_mdata_en [00:00] */
#define TX2_TX_ACONTROL0_TX_MDATA_EN_MASK                          0x0001
#define TX2_TX_ACONTROL0_TX_MDATA_EN_ALIGN                         0
#define TX2_TX_ACONTROL0_TX_MDATA_EN_BITS                          1
#define TX2_TX_ACONTROL0_TX_MDATA_EN_SHIFT                         0


/****************************************************************************
 * TX2 :: Tx_mdata0
 ***************************************************************************/
/* TX2 :: Tx_mdata0 :: txTestMuxSel [15:13] */
#define TX2_TX_MDATA0_TXTESTMUXSEL_MASK                            0xe000
#define TX2_TX_MDATA0_TXTESTMUXSEL_ALIGN                           0
#define TX2_TX_MDATA0_TXTESTMUXSEL_BITS                            3
#define TX2_TX_MDATA0_TXTESTMUXSEL_SHIFT                           13

/* TX2 :: Tx_mdata0 :: rlfifo_tstsel [12:10] */
#define TX2_TX_MDATA0_RLFIFO_TSTSEL_MASK                           0x1c00
#define TX2_TX_MDATA0_RLFIFO_TSTSEL_ALIGN                          0
#define TX2_TX_MDATA0_RLFIFO_TSTSEL_BITS                           3
#define TX2_TX_MDATA0_RLFIFO_TSTSEL_SHIFT                          10

/* TX2 :: Tx_mdata0 :: TxMdioTstDataL [09:00] */
#define TX2_TX_MDATA0_TXMDIOTSTDATAL_MASK                          0x03ff
#define TX2_TX_MDATA0_TXMDIOTSTDATAL_ALIGN                         0
#define TX2_TX_MDATA0_TXMDIOTSTDATAL_BITS                          10
#define TX2_TX_MDATA0_TXMDIOTSTDATAL_SHIFT                         0


/****************************************************************************
 * TX2 :: Tx_mdata1
 ***************************************************************************/
/* TX2 :: Tx_mdata1 :: reserved0 [15:10] */
#define TX2_TX_MDATA1_RESERVED0_MASK                               0xfc00
#define TX2_TX_MDATA1_RESERVED0_ALIGN                              0
#define TX2_TX_MDATA1_RESERVED0_BITS                               6
#define TX2_TX_MDATA1_RESERVED0_SHIFT                              10

/* TX2 :: Tx_mdata1 :: TxMdioTstDataH [09:00] */
#define TX2_TX_MDATA1_TXMDIOTSTDATAH_MASK                          0x03ff
#define TX2_TX_MDATA1_TXMDIOTSTDATAH_ALIGN                         0
#define TX2_TX_MDATA1_TXMDIOTSTDATAH_BITS                          10
#define TX2_TX_MDATA1_TXMDIOTSTDATAH_SHIFT                         0


/****************************************************************************
 * TX2 :: Tx_AStatus1
 ***************************************************************************/
/* TX2 :: Tx_AStatus1 :: tx_id [15:14] */
#define TX2_TX_ASTATUS1_TX_ID_MASK                                 0xc000
#define TX2_TX_ASTATUS1_TX_ID_ALIGN                                0
#define TX2_TX_ASTATUS1_TX_ID_BITS                                 2
#define TX2_TX_ASTATUS1_TX_ID_SHIFT                                14

/* TX2 :: Tx_AStatus1 :: reserved0 [13:00] */
#define TX2_TX_ASTATUS1_RESERVED0_MASK                             0x3fff
#define TX2_TX_ASTATUS1_RESERVED0_ALIGN                            0
#define TX2_TX_ASTATUS1_RESERVED0_BITS                             14
#define TX2_TX_ASTATUS1_RESERVED0_SHIFT                            0


/****************************************************************************
 * TX2 :: Tx_BgVcm
 ***************************************************************************/
/* TX2 :: Tx_BgVcm :: id2c [15:13] */
#define TX2_TX_BGVCM_ID2C_MASK                                     0xe000
#define TX2_TX_BGVCM_ID2C_ALIGN                                    0
#define TX2_TX_BGVCM_ID2C_BITS                                     3
#define TX2_TX_BGVCM_ID2C_SHIFT                                    13

/* TX2 :: Tx_BgVcm :: refl_tx [12:12] */
#define TX2_TX_BGVCM_REFL_TX_MASK                                  0x1000
#define TX2_TX_BGVCM_REFL_TX_ALIGN                                 0
#define TX2_TX_BGVCM_REFL_TX_BITS                                  1
#define TX2_TX_BGVCM_REFL_TX_SHIFT                                 12

/* TX2 :: Tx_BgVcm :: refh_tx [11:11] */
#define TX2_TX_BGVCM_REFH_TX_MASK                                  0x0800
#define TX2_TX_BGVCM_REFH_TX_ALIGN                                 0
#define TX2_TX_BGVCM_REFH_TX_BITS                                  1
#define TX2_TX_BGVCM_REFH_TX_SHIFT                                 11

/* TX2 :: Tx_BgVcm :: newbias_en [10:10] */
#define TX2_TX_BGVCM_NEWBIAS_EN_MASK                               0x0400
#define TX2_TX_BGVCM_NEWBIAS_EN_ALIGN                              0
#define TX2_TX_BGVCM_NEWBIAS_EN_BITS                               1
#define TX2_TX_BGVCM_NEWBIAS_EN_SHIFT                              10

/* TX2 :: Tx_BgVcm :: drivermode [09:09] */
#define TX2_TX_BGVCM_DRIVERMODE_MASK                               0x0200
#define TX2_TX_BGVCM_DRIVERMODE_ALIGN                              0
#define TX2_TX_BGVCM_DRIVERMODE_BITS                               1
#define TX2_TX_BGVCM_DRIVERMODE_SHIFT                              9

/* TX2 :: Tx_BgVcm :: bddr_bgb [08:08] */
#define TX2_TX_BGVCM_BDDR_BGB_MASK                                 0x0100
#define TX2_TX_BGVCM_BDDR_BGB_ALIGN                                0
#define TX2_TX_BGVCM_BDDR_BGB_BITS                                 1
#define TX2_TX_BGVCM_BDDR_BGB_SHIFT                                8

/* TX2 :: Tx_BgVcm :: ticksel [07:06] */
#define TX2_TX_BGVCM_TICKSEL_MASK                                  0x00c0
#define TX2_TX_BGVCM_TICKSEL_ALIGN                                 0
#define TX2_TX_BGVCM_TICKSEL_BITS                                  2
#define TX2_TX_BGVCM_TICKSEL_SHIFT                                 6

/* TX2 :: Tx_BgVcm :: driver_vcm [05:04] */
#define TX2_TX_BGVCM_DRIVER_VCM_MASK                               0x0030
#define TX2_TX_BGVCM_DRIVER_VCM_ALIGN                              0
#define TX2_TX_BGVCM_DRIVER_VCM_BITS                               2
#define TX2_TX_BGVCM_DRIVER_VCM_SHIFT                              4

/* TX2 :: Tx_BgVcm :: tx_sel_halfrate [03:03] */
#define TX2_TX_BGVCM_TX_SEL_HALFRATE_MASK                          0x0008
#define TX2_TX_BGVCM_TX_SEL_HALFRATE_ALIGN                         0
#define TX2_TX_BGVCM_TX_SEL_HALFRATE_BITS                          1
#define TX2_TX_BGVCM_TX_SEL_HALFRATE_SHIFT                         3

/* TX2 :: Tx_BgVcm :: ifullspd [02:00] */
#define TX2_TX_BGVCM_IFULLSPD_MASK                                 0x0007
#define TX2_TX_BGVCM_IFULLSPD_ALIGN                                0
#define TX2_TX_BGVCM_IFULLSPD_BITS                                 3
#define TX2_TX_BGVCM_IFULLSPD_SHIFT                                0


/****************************************************************************
 * TX2 :: Tx_ibuff_1T2T
 ***************************************************************************/
/* TX2 :: Tx_ibuff_1T2T :: icbuf1t [15:14] */
#define TX2_TX_IBUFF_1T2T_ICBUF1T_MASK                             0xc000
#define TX2_TX_IBUFF_1T2T_ICBUF1T_ALIGN                            0
#define TX2_TX_IBUFF_1T2T_ICBUF1T_BITS                             2
#define TX2_TX_IBUFF_1T2T_ICBUF1T_SHIFT                            14

/* TX2 :: Tx_ibuff_1T2T :: icbuf2t [13:11] */
#define TX2_TX_IBUFF_1T2T_ICBUF2T_MASK                             0x3800
#define TX2_TX_IBUFF_1T2T_ICBUF2T_ALIGN                            0
#define TX2_TX_IBUFF_1T2T_ICBUF2T_BITS                             3
#define TX2_TX_IBUFF_1T2T_ICBUF2T_SHIFT                            11

/* TX2 :: Tx_ibuff_1T2T :: imin_predrv [10:10] */
#define TX2_TX_IBUFF_1T2T_IMIN_PREDRV_MASK                         0x0400
#define TX2_TX_IBUFF_1T2T_IMIN_PREDRV_ALIGN                        0
#define TX2_TX_IBUFF_1T2T_IMIN_PREDRV_BITS                         1
#define TX2_TX_IBUFF_1T2T_IMIN_PREDRV_SHIFT                        10

/* TX2 :: Tx_ibuff_1T2T :: imax_predrv [09:09] */
#define TX2_TX_IBUFF_1T2T_IMAX_PREDRV_MASK                         0x0200
#define TX2_TX_IBUFF_1T2T_IMAX_PREDRV_ALIGN                        0
#define TX2_TX_IBUFF_1T2T_IMAX_PREDRV_BITS                         1
#define TX2_TX_IBUFF_1T2T_IMAX_PREDRV_SHIFT                        9

/* TX2 :: Tx_ibuff_1T2T :: imode_predrv [08:08] */
#define TX2_TX_IBUFF_1T2T_IMODE_PREDRV_MASK                        0x0100
#define TX2_TX_IBUFF_1T2T_IMODE_PREDRV_ALIGN                       0
#define TX2_TX_IBUFF_1T2T_IMODE_PREDRV_BITS                        1
#define TX2_TX_IBUFF_1T2T_IMODE_PREDRV_SHIFT                       8

/* TX2 :: Tx_ibuff_1T2T :: i21mux [07:05] */
#define TX2_TX_IBUFF_1T2T_I21MUX_MASK                              0x00e0
#define TX2_TX_IBUFF_1T2T_I21MUX_ALIGN                             0
#define TX2_TX_IBUFF_1T2T_I21MUX_BITS                              3
#define TX2_TX_IBUFF_1T2T_I21MUX_SHIFT                             5

/* TX2 :: Tx_ibuff_1T2T :: imin_drvr [04:04] */
#define TX2_TX_IBUFF_1T2T_IMIN_DRVR_MASK                           0x0010
#define TX2_TX_IBUFF_1T2T_IMIN_DRVR_ALIGN                          0
#define TX2_TX_IBUFF_1T2T_IMIN_DRVR_BITS                           1
#define TX2_TX_IBUFF_1T2T_IMIN_DRVR_SHIFT                          4

/* TX2 :: Tx_ibuff_1T2T :: imax_drvr [03:03] */
#define TX2_TX_IBUFF_1T2T_IMAX_DRVR_MASK                           0x0008
#define TX2_TX_IBUFF_1T2T_IMAX_DRVR_ALIGN                          0
#define TX2_TX_IBUFF_1T2T_IMAX_DRVR_BITS                           1
#define TX2_TX_IBUFF_1T2T_IMAX_DRVR_SHIFT                          3

/* TX2 :: Tx_ibuff_1T2T :: imode_drvr [02:02] */
#define TX2_TX_IBUFF_1T2T_IMODE_DRVR_MASK                          0x0004
#define TX2_TX_IBUFF_1T2T_IMODE_DRVR_ALIGN                         0
#define TX2_TX_IBUFF_1T2T_IMODE_DRVR_BITS                          1
#define TX2_TX_IBUFF_1T2T_IMODE_DRVR_SHIFT                         2

/* TX2 :: Tx_ibuff_1T2T :: reserved0 [01:00] */
#define TX2_TX_IBUFF_1T2T_RESERVED0_MASK                           0x0003
#define TX2_TX_IBUFF_1T2T_RESERVED0_ALIGN                          0
#define TX2_TX_IBUFF_1T2T_RESERVED0_BITS                           2
#define TX2_TX_IBUFF_1T2T_RESERVED0_SHIFT                          0


/****************************************************************************
 * TX2 :: Tx_Driver
 ***************************************************************************/
/* TX2 :: Tx_Driver :: preemphasis_post [15:12] */
#define TX2_TX_DRIVER_PREEMPHASIS_POST_MASK                        0xf000
#define TX2_TX_DRIVER_PREEMPHASIS_POST_ALIGN                       0
#define TX2_TX_DRIVER_PREEMPHASIS_POST_BITS                        4
#define TX2_TX_DRIVER_PREEMPHASIS_POST_SHIFT                       12

/* TX2 :: Tx_Driver :: Idriver [11:08] */
#define TX2_TX_DRIVER_IDRIVER_MASK                                 0x0f00
#define TX2_TX_DRIVER_IDRIVER_ALIGN                                0
#define TX2_TX_DRIVER_IDRIVER_BITS                                 4
#define TX2_TX_DRIVER_IDRIVER_SHIFT                                8

/* TX2 :: Tx_Driver :: Ipredriver [07:04] */
#define TX2_TX_DRIVER_IPREDRIVER_MASK                              0x00f0
#define TX2_TX_DRIVER_IPREDRIVER_ALIGN                             0
#define TX2_TX_DRIVER_IPREDRIVER_BITS                              4
#define TX2_TX_DRIVER_IPREDRIVER_SHIFT                             4

/* TX2 :: Tx_Driver :: preemphasis_pre [03:01] */
#define TX2_TX_DRIVER_PREEMPHASIS_PRE_MASK                         0x000e
#define TX2_TX_DRIVER_PREEMPHASIS_PRE_ALIGN                        0
#define TX2_TX_DRIVER_PREEMPHASIS_PRE_BITS                         3
#define TX2_TX_DRIVER_PREEMPHASIS_PRE_SHIFT                        1

/* TX2 :: Tx_Driver :: icbuf1t0 [00:00] */
#define TX2_TX_DRIVER_ICBUF1T0_MASK                                0x0001
#define TX2_TX_DRIVER_ICBUF1T0_ALIGN                               0
#define TX2_TX_DRIVER_ICBUF1T0_BITS                                1
#define TX2_TX_DRIVER_ICBUF1T0_SHIFT                               0


/****************************************************************************
 * XGXS16G_USER_TX3
 ***************************************************************************/
/****************************************************************************
 * TX3 :: Tx_AStatus0
 ***************************************************************************/
/* TX3 :: Tx_AStatus0 :: reserved0 [15:03] */
#define TX3_TX_ASTATUS0_RESERVED0_MASK                             0xfff8
#define TX3_TX_ASTATUS0_RESERVED0_ALIGN                            0
#define TX3_TX_ASTATUS0_RESERVED0_BITS                             13
#define TX3_TX_ASTATUS0_RESERVED0_SHIFT                            3

/* TX3 :: Tx_AStatus0 :: tx_gloopback [02:02] */
#define TX3_TX_ASTATUS0_TX_GLOOPBACK_MASK                          0x0004
#define TX3_TX_ASTATUS0_TX_GLOOPBACK_ALIGN                         0
#define TX3_TX_ASTATUS0_TX_GLOOPBACK_BITS                          1
#define TX3_TX_ASTATUS0_TX_GLOOPBACK_SHIFT                         2

/* TX3 :: Tx_AStatus0 :: rltxferr [01:01] */
#define TX3_TX_ASTATUS0_RLTXFERR_MASK                              0x0002
#define TX3_TX_ASTATUS0_RLTXFERR_ALIGN                             0
#define TX3_TX_ASTATUS0_RLTXFERR_BITS                              1
#define TX3_TX_ASTATUS0_RLTXFERR_SHIFT                             1

/* TX3 :: Tx_AStatus0 :: txferr [00:00] */
#define TX3_TX_ASTATUS0_TXFERR_MASK                                0x0001
#define TX3_TX_ASTATUS0_TXFERR_ALIGN                               0
#define TX3_TX_ASTATUS0_TXFERR_BITS                                1
#define TX3_TX_ASTATUS0_TXFERR_SHIFT                               0


/****************************************************************************
 * TX3 :: Tx_AControl0
 ***************************************************************************/
/* TX3 :: Tx_AControl0 :: reserved0 [15:15] */
#define TX3_TX_ACONTROL0_RESERVED0_MASK                            0x8000
#define TX3_TX_ACONTROL0_RESERVED0_ALIGN                           0
#define TX3_TX_ACONTROL0_RESERVED0_BITS                            1
#define TX3_TX_ACONTROL0_RESERVED0_SHIFT                           15

/* TX3 :: Tx_AControl0 :: force_txclk [14:14] */
#define TX3_TX_ACONTROL0_FORCE_TXCLK_MASK                          0x4000
#define TX3_TX_ACONTROL0_FORCE_TXCLK_ALIGN                         0
#define TX3_TX_ACONTROL0_FORCE_TXCLK_BITS                          1
#define TX3_TX_ACONTROL0_FORCE_TXCLK_SHIFT                         14

/* TX3 :: Tx_AControl0 :: tx1g_fifo_rst [13:13] */
#define TX3_TX_ACONTROL0_TX1G_FIFO_RST_MASK                        0x2000
#define TX3_TX_ACONTROL0_TX1G_FIFO_RST_ALIGN                       0
#define TX3_TX_ACONTROL0_TX1G_FIFO_RST_BITS                        1
#define TX3_TX_ACONTROL0_TX1G_FIFO_RST_SHIFT                       13

/* TX3 :: Tx_AControl0 :: gloopOutEn [12:12] */
#define TX3_TX_ACONTROL0_GLOOPOUTEN_MASK                           0x1000
#define TX3_TX_ACONTROL0_GLOOPOUTEN_ALIGN                          0
#define TX3_TX_ACONTROL0_GLOOPOUTEN_BITS                           1
#define TX3_TX_ACONTROL0_GLOOPOUTEN_SHIFT                          12

/* TX3 :: Tx_AControl0 :: reserved1 [11:09] */
#define TX3_TX_ACONTROL0_RESERVED1_MASK                            0x0e00
#define TX3_TX_ACONTROL0_RESERVED1_ALIGN                           0
#define TX3_TX_ACONTROL0_RESERVED1_BITS                            3
#define TX3_TX_ACONTROL0_RESERVED1_SHIFT                           9

/* TX3 :: Tx_AControl0 :: prbs_en [08:08] */
#define TX3_TX_ACONTROL0_PRBS_EN_MASK                              0x0100
#define TX3_TX_ACONTROL0_PRBS_EN_ALIGN                             0
#define TX3_TX_ACONTROL0_PRBS_EN_BITS                              1
#define TX3_TX_ACONTROL0_PRBS_EN_SHIFT                             8

/* TX3 :: Tx_AControl0 :: pckt_en [07:07] */
#define TX3_TX_ACONTROL0_PCKT_EN_MASK                              0x0080
#define TX3_TX_ACONTROL0_PCKT_EN_ALIGN                             0
#define TX3_TX_ACONTROL0_PCKT_EN_BITS                              1
#define TX3_TX_ACONTROL0_PCKT_EN_SHIFT                             7

/* TX3 :: Tx_AControl0 :: pckt_strt [06:06] */
#define TX3_TX_ACONTROL0_PCKT_STRT_MASK                            0x0040
#define TX3_TX_ACONTROL0_PCKT_STRT_ALIGN                           0
#define TX3_TX_ACONTROL0_PCKT_STRT_BITS                            1
#define TX3_TX_ACONTROL0_PCKT_STRT_SHIFT                           6

/* TX3 :: Tx_AControl0 :: txpol_flip [05:05] */
#define TX3_TX_ACONTROL0_TXPOL_FLIP_MASK                           0x0020
#define TX3_TX_ACONTROL0_TXPOL_FLIP_ALIGN                          0
#define TX3_TX_ACONTROL0_TXPOL_FLIP_BITS                           1
#define TX3_TX_ACONTROL0_TXPOL_FLIP_SHIFT                          5

/* TX3 :: Tx_AControl0 :: rtbi_flip [04:04] */
#define TX3_TX_ACONTROL0_RTBI_FLIP_MASK                            0x0010
#define TX3_TX_ACONTROL0_RTBI_FLIP_ALIGN                           0
#define TX3_TX_ACONTROL0_RTBI_FLIP_BITS                            1
#define TX3_TX_ACONTROL0_RTBI_FLIP_SHIFT                           4

/* TX3 :: Tx_AControl0 :: eden_r [03:03] */
#define TX3_TX_ACONTROL0_EDEN_R_MASK                               0x0008
#define TX3_TX_ACONTROL0_EDEN_R_ALIGN                              0
#define TX3_TX_ACONTROL0_EDEN_R_BITS                               1
#define TX3_TX_ACONTROL0_EDEN_R_SHIFT                              3

/* TX3 :: Tx_AControl0 :: eden_force_r [02:02] */
#define TX3_TX_ACONTROL0_EDEN_FORCE_R_MASK                         0x0004
#define TX3_TX_ACONTROL0_EDEN_FORCE_R_ALIGN                        0
#define TX3_TX_ACONTROL0_EDEN_FORCE_R_BITS                         1
#define TX3_TX_ACONTROL0_EDEN_FORCE_R_SHIFT                        2

/* TX3 :: Tx_AControl0 :: txpat_en [01:01] */
#define TX3_TX_ACONTROL0_TXPAT_EN_MASK                             0x0002
#define TX3_TX_ACONTROL0_TXPAT_EN_ALIGN                            0
#define TX3_TX_ACONTROL0_TXPAT_EN_BITS                             1
#define TX3_TX_ACONTROL0_TXPAT_EN_SHIFT                            1

/* TX3 :: Tx_AControl0 :: tx_mdata_en [00:00] */
#define TX3_TX_ACONTROL0_TX_MDATA_EN_MASK                          0x0001
#define TX3_TX_ACONTROL0_TX_MDATA_EN_ALIGN                         0
#define TX3_TX_ACONTROL0_TX_MDATA_EN_BITS                          1
#define TX3_TX_ACONTROL0_TX_MDATA_EN_SHIFT                         0


/****************************************************************************
 * TX3 :: Tx_mdata0
 ***************************************************************************/
/* TX3 :: Tx_mdata0 :: txTestMuxSel [15:13] */
#define TX3_TX_MDATA0_TXTESTMUXSEL_MASK                            0xe000
#define TX3_TX_MDATA0_TXTESTMUXSEL_ALIGN                           0
#define TX3_TX_MDATA0_TXTESTMUXSEL_BITS                            3
#define TX3_TX_MDATA0_TXTESTMUXSEL_SHIFT                           13

/* TX3 :: Tx_mdata0 :: rlfifo_tstsel [12:10] */
#define TX3_TX_MDATA0_RLFIFO_TSTSEL_MASK                           0x1c00
#define TX3_TX_MDATA0_RLFIFO_TSTSEL_ALIGN                          0
#define TX3_TX_MDATA0_RLFIFO_TSTSEL_BITS                           3
#define TX3_TX_MDATA0_RLFIFO_TSTSEL_SHIFT                          10

/* TX3 :: Tx_mdata0 :: TxMdioTstDataL [09:00] */
#define TX3_TX_MDATA0_TXMDIOTSTDATAL_MASK                          0x03ff
#define TX3_TX_MDATA0_TXMDIOTSTDATAL_ALIGN                         0
#define TX3_TX_MDATA0_TXMDIOTSTDATAL_BITS                          10
#define TX3_TX_MDATA0_TXMDIOTSTDATAL_SHIFT                         0


/****************************************************************************
 * TX3 :: Tx_mdata1
 ***************************************************************************/
/* TX3 :: Tx_mdata1 :: reserved0 [15:10] */
#define TX3_TX_MDATA1_RESERVED0_MASK                               0xfc00
#define TX3_TX_MDATA1_RESERVED0_ALIGN                              0
#define TX3_TX_MDATA1_RESERVED0_BITS                               6
#define TX3_TX_MDATA1_RESERVED0_SHIFT                              10

/* TX3 :: Tx_mdata1 :: TxMdioTstDataH [09:00] */
#define TX3_TX_MDATA1_TXMDIOTSTDATAH_MASK                          0x03ff
#define TX3_TX_MDATA1_TXMDIOTSTDATAH_ALIGN                         0
#define TX3_TX_MDATA1_TXMDIOTSTDATAH_BITS                          10
#define TX3_TX_MDATA1_TXMDIOTSTDATAH_SHIFT                         0


/****************************************************************************
 * TX3 :: Tx_AStatus1
 ***************************************************************************/
/* TX3 :: Tx_AStatus1 :: tx_id [15:14] */
#define TX3_TX_ASTATUS1_TX_ID_MASK                                 0xc000
#define TX3_TX_ASTATUS1_TX_ID_ALIGN                                0
#define TX3_TX_ASTATUS1_TX_ID_BITS                                 2
#define TX3_TX_ASTATUS1_TX_ID_SHIFT                                14

/* TX3 :: Tx_AStatus1 :: reserved0 [13:00] */
#define TX3_TX_ASTATUS1_RESERVED0_MASK                             0x3fff
#define TX3_TX_ASTATUS1_RESERVED0_ALIGN                            0
#define TX3_TX_ASTATUS1_RESERVED0_BITS                             14
#define TX3_TX_ASTATUS1_RESERVED0_SHIFT                            0


/****************************************************************************
 * TX3 :: Tx_BgVcm
 ***************************************************************************/
/* TX3 :: Tx_BgVcm :: id2c [15:13] */
#define TX3_TX_BGVCM_ID2C_MASK                                     0xe000
#define TX3_TX_BGVCM_ID2C_ALIGN                                    0
#define TX3_TX_BGVCM_ID2C_BITS                                     3
#define TX3_TX_BGVCM_ID2C_SHIFT                                    13

/* TX3 :: Tx_BgVcm :: refl_tx [12:12] */
#define TX3_TX_BGVCM_REFL_TX_MASK                                  0x1000
#define TX3_TX_BGVCM_REFL_TX_ALIGN                                 0
#define TX3_TX_BGVCM_REFL_TX_BITS                                  1
#define TX3_TX_BGVCM_REFL_TX_SHIFT                                 12

/* TX3 :: Tx_BgVcm :: refh_tx [11:11] */
#define TX3_TX_BGVCM_REFH_TX_MASK                                  0x0800
#define TX3_TX_BGVCM_REFH_TX_ALIGN                                 0
#define TX3_TX_BGVCM_REFH_TX_BITS                                  1
#define TX3_TX_BGVCM_REFH_TX_SHIFT                                 11

/* TX3 :: Tx_BgVcm :: newbias_en [10:10] */
#define TX3_TX_BGVCM_NEWBIAS_EN_MASK                               0x0400
#define TX3_TX_BGVCM_NEWBIAS_EN_ALIGN                              0
#define TX3_TX_BGVCM_NEWBIAS_EN_BITS                               1
#define TX3_TX_BGVCM_NEWBIAS_EN_SHIFT                              10

/* TX3 :: Tx_BgVcm :: drivermode [09:09] */
#define TX3_TX_BGVCM_DRIVERMODE_MASK                               0x0200
#define TX3_TX_BGVCM_DRIVERMODE_ALIGN                              0
#define TX3_TX_BGVCM_DRIVERMODE_BITS                               1
#define TX3_TX_BGVCM_DRIVERMODE_SHIFT                              9

/* TX3 :: Tx_BgVcm :: bddr_bgb [08:08] */
#define TX3_TX_BGVCM_BDDR_BGB_MASK                                 0x0100
#define TX3_TX_BGVCM_BDDR_BGB_ALIGN                                0
#define TX3_TX_BGVCM_BDDR_BGB_BITS                                 1
#define TX3_TX_BGVCM_BDDR_BGB_SHIFT                                8

/* TX3 :: Tx_BgVcm :: ticksel [07:06] */
#define TX3_TX_BGVCM_TICKSEL_MASK                                  0x00c0
#define TX3_TX_BGVCM_TICKSEL_ALIGN                                 0
#define TX3_TX_BGVCM_TICKSEL_BITS                                  2
#define TX3_TX_BGVCM_TICKSEL_SHIFT                                 6

/* TX3 :: Tx_BgVcm :: driver_vcm [05:04] */
#define TX3_TX_BGVCM_DRIVER_VCM_MASK                               0x0030
#define TX3_TX_BGVCM_DRIVER_VCM_ALIGN                              0
#define TX3_TX_BGVCM_DRIVER_VCM_BITS                               2
#define TX3_TX_BGVCM_DRIVER_VCM_SHIFT                              4

/* TX3 :: Tx_BgVcm :: tx_sel_halfrate [03:03] */
#define TX3_TX_BGVCM_TX_SEL_HALFRATE_MASK                          0x0008
#define TX3_TX_BGVCM_TX_SEL_HALFRATE_ALIGN                         0
#define TX3_TX_BGVCM_TX_SEL_HALFRATE_BITS                          1
#define TX3_TX_BGVCM_TX_SEL_HALFRATE_SHIFT                         3

/* TX3 :: Tx_BgVcm :: ifullspd [02:00] */
#define TX3_TX_BGVCM_IFULLSPD_MASK                                 0x0007
#define TX3_TX_BGVCM_IFULLSPD_ALIGN                                0
#define TX3_TX_BGVCM_IFULLSPD_BITS                                 3
#define TX3_TX_BGVCM_IFULLSPD_SHIFT                                0


/****************************************************************************
 * TX3 :: Tx_ibuff_1T2T
 ***************************************************************************/
/* TX3 :: Tx_ibuff_1T2T :: icbuf1t [15:14] */
#define TX3_TX_IBUFF_1T2T_ICBUF1T_MASK                             0xc000
#define TX3_TX_IBUFF_1T2T_ICBUF1T_ALIGN                            0
#define TX3_TX_IBUFF_1T2T_ICBUF1T_BITS                             2
#define TX3_TX_IBUFF_1T2T_ICBUF1T_SHIFT                            14

/* TX3 :: Tx_ibuff_1T2T :: icbuf2t [13:11] */
#define TX3_TX_IBUFF_1T2T_ICBUF2T_MASK                             0x3800
#define TX3_TX_IBUFF_1T2T_ICBUF2T_ALIGN                            0
#define TX3_TX_IBUFF_1T2T_ICBUF2T_BITS                             3
#define TX3_TX_IBUFF_1T2T_ICBUF2T_SHIFT                            11

/* TX3 :: Tx_ibuff_1T2T :: imin_predrv [10:10] */
#define TX3_TX_IBUFF_1T2T_IMIN_PREDRV_MASK                         0x0400
#define TX3_TX_IBUFF_1T2T_IMIN_PREDRV_ALIGN                        0
#define TX3_TX_IBUFF_1T2T_IMIN_PREDRV_BITS                         1
#define TX3_TX_IBUFF_1T2T_IMIN_PREDRV_SHIFT                        10

/* TX3 :: Tx_ibuff_1T2T :: imax_predrv [09:09] */
#define TX3_TX_IBUFF_1T2T_IMAX_PREDRV_MASK                         0x0200
#define TX3_TX_IBUFF_1T2T_IMAX_PREDRV_ALIGN                        0
#define TX3_TX_IBUFF_1T2T_IMAX_PREDRV_BITS                         1
#define TX3_TX_IBUFF_1T2T_IMAX_PREDRV_SHIFT                        9

/* TX3 :: Tx_ibuff_1T2T :: imode_predrv [08:08] */
#define TX3_TX_IBUFF_1T2T_IMODE_PREDRV_MASK                        0x0100
#define TX3_TX_IBUFF_1T2T_IMODE_PREDRV_ALIGN                       0
#define TX3_TX_IBUFF_1T2T_IMODE_PREDRV_BITS                        1
#define TX3_TX_IBUFF_1T2T_IMODE_PREDRV_SHIFT                       8

/* TX3 :: Tx_ibuff_1T2T :: i21mux [07:05] */
#define TX3_TX_IBUFF_1T2T_I21MUX_MASK                              0x00e0
#define TX3_TX_IBUFF_1T2T_I21MUX_ALIGN                             0
#define TX3_TX_IBUFF_1T2T_I21MUX_BITS                              3
#define TX3_TX_IBUFF_1T2T_I21MUX_SHIFT                             5

/* TX3 :: Tx_ibuff_1T2T :: imin_drvr [04:04] */
#define TX3_TX_IBUFF_1T2T_IMIN_DRVR_MASK                           0x0010
#define TX3_TX_IBUFF_1T2T_IMIN_DRVR_ALIGN                          0
#define TX3_TX_IBUFF_1T2T_IMIN_DRVR_BITS                           1
#define TX3_TX_IBUFF_1T2T_IMIN_DRVR_SHIFT                          4

/* TX3 :: Tx_ibuff_1T2T :: imax_drvr [03:03] */
#define TX3_TX_IBUFF_1T2T_IMAX_DRVR_MASK                           0x0008
#define TX3_TX_IBUFF_1T2T_IMAX_DRVR_ALIGN                          0
#define TX3_TX_IBUFF_1T2T_IMAX_DRVR_BITS                           1
#define TX3_TX_IBUFF_1T2T_IMAX_DRVR_SHIFT                          3

/* TX3 :: Tx_ibuff_1T2T :: imode_drvr [02:02] */
#define TX3_TX_IBUFF_1T2T_IMODE_DRVR_MASK                          0x0004
#define TX3_TX_IBUFF_1T2T_IMODE_DRVR_ALIGN                         0
#define TX3_TX_IBUFF_1T2T_IMODE_DRVR_BITS                          1
#define TX3_TX_IBUFF_1T2T_IMODE_DRVR_SHIFT                         2

/* TX3 :: Tx_ibuff_1T2T :: reserved0 [01:00] */
#define TX3_TX_IBUFF_1T2T_RESERVED0_MASK                           0x0003
#define TX3_TX_IBUFF_1T2T_RESERVED0_ALIGN                          0
#define TX3_TX_IBUFF_1T2T_RESERVED0_BITS                           2
#define TX3_TX_IBUFF_1T2T_RESERVED0_SHIFT                          0


/****************************************************************************
 * TX3 :: Tx_Driver
 ***************************************************************************/
/* TX3 :: Tx_Driver :: preemphasis_post [15:12] */
#define TX3_TX_DRIVER_PREEMPHASIS_POST_MASK                        0xf000
#define TX3_TX_DRIVER_PREEMPHASIS_POST_ALIGN                       0
#define TX3_TX_DRIVER_PREEMPHASIS_POST_BITS                        4
#define TX3_TX_DRIVER_PREEMPHASIS_POST_SHIFT                       12

/* TX3 :: Tx_Driver :: Idriver [11:08] */
#define TX3_TX_DRIVER_IDRIVER_MASK                                 0x0f00
#define TX3_TX_DRIVER_IDRIVER_ALIGN                                0
#define TX3_TX_DRIVER_IDRIVER_BITS                                 4
#define TX3_TX_DRIVER_IDRIVER_SHIFT                                8

/* TX3 :: Tx_Driver :: Ipredriver [07:04] */
#define TX3_TX_DRIVER_IPREDRIVER_MASK                              0x00f0
#define TX3_TX_DRIVER_IPREDRIVER_ALIGN                             0
#define TX3_TX_DRIVER_IPREDRIVER_BITS                              4
#define TX3_TX_DRIVER_IPREDRIVER_SHIFT                             4

/* TX3 :: Tx_Driver :: preemphasis_pre [03:01] */
#define TX3_TX_DRIVER_PREEMPHASIS_PRE_MASK                         0x000e
#define TX3_TX_DRIVER_PREEMPHASIS_PRE_ALIGN                        0
#define TX3_TX_DRIVER_PREEMPHASIS_PRE_BITS                         3
#define TX3_TX_DRIVER_PREEMPHASIS_PRE_SHIFT                        1

/* TX3 :: Tx_Driver :: icbuf1t0 [00:00] */
#define TX3_TX_DRIVER_ICBUF1T0_MASK                                0x0001
#define TX3_TX_DRIVER_ICBUF1T0_ALIGN                               0
#define TX3_TX_DRIVER_ICBUF1T0_BITS                                1
#define TX3_TX_DRIVER_ICBUF1T0_SHIFT                               0


/****************************************************************************
 * XGXS16G_USER_TX_All
 ***************************************************************************/
/****************************************************************************
 * TX_All :: Tx_AStatus0
 ***************************************************************************/
/* TX_All :: Tx_AStatus0 :: reserved0 [15:03] */
#define TX_ALL_TX_ASTATUS0_RESERVED0_MASK                          0xfff8
#define TX_ALL_TX_ASTATUS0_RESERVED0_ALIGN                         0
#define TX_ALL_TX_ASTATUS0_RESERVED0_BITS                          13
#define TX_ALL_TX_ASTATUS0_RESERVED0_SHIFT                         3

/* TX_All :: Tx_AStatus0 :: tx_gloopback [02:02] */
#define TX_ALL_TX_ASTATUS0_TX_GLOOPBACK_MASK                       0x0004
#define TX_ALL_TX_ASTATUS0_TX_GLOOPBACK_ALIGN                      0
#define TX_ALL_TX_ASTATUS0_TX_GLOOPBACK_BITS                       1
#define TX_ALL_TX_ASTATUS0_TX_GLOOPBACK_SHIFT                      2

/* TX_All :: Tx_AStatus0 :: rltxferr [01:01] */
#define TX_ALL_TX_ASTATUS0_RLTXFERR_MASK                           0x0002
#define TX_ALL_TX_ASTATUS0_RLTXFERR_ALIGN                          0
#define TX_ALL_TX_ASTATUS0_RLTXFERR_BITS                           1
#define TX_ALL_TX_ASTATUS0_RLTXFERR_SHIFT                          1

/* TX_All :: Tx_AStatus0 :: txferr [00:00] */
#define TX_ALL_TX_ASTATUS0_TXFERR_MASK                             0x0001
#define TX_ALL_TX_ASTATUS0_TXFERR_ALIGN                            0
#define TX_ALL_TX_ASTATUS0_TXFERR_BITS                             1
#define TX_ALL_TX_ASTATUS0_TXFERR_SHIFT                            0


/****************************************************************************
 * TX_All :: Tx_AControl0
 ***************************************************************************/
/* TX_All :: Tx_AControl0 :: reserved0 [15:15] */
#define TX_ALL_TX_ACONTROL0_RESERVED0_MASK                         0x8000
#define TX_ALL_TX_ACONTROL0_RESERVED0_ALIGN                        0
#define TX_ALL_TX_ACONTROL0_RESERVED0_BITS                         1
#define TX_ALL_TX_ACONTROL0_RESERVED0_SHIFT                        15

/* TX_All :: Tx_AControl0 :: force_txclk [14:14] */
#define TX_ALL_TX_ACONTROL0_FORCE_TXCLK_MASK                       0x4000
#define TX_ALL_TX_ACONTROL0_FORCE_TXCLK_ALIGN                      0
#define TX_ALL_TX_ACONTROL0_FORCE_TXCLK_BITS                       1
#define TX_ALL_TX_ACONTROL0_FORCE_TXCLK_SHIFT                      14

/* TX_All :: Tx_AControl0 :: tx1g_fifo_rst [13:13] */
#define TX_ALL_TX_ACONTROL0_TX1G_FIFO_RST_MASK                     0x2000
#define TX_ALL_TX_ACONTROL0_TX1G_FIFO_RST_ALIGN                    0
#define TX_ALL_TX_ACONTROL0_TX1G_FIFO_RST_BITS                     1
#define TX_ALL_TX_ACONTROL0_TX1G_FIFO_RST_SHIFT                    13

/* TX_All :: Tx_AControl0 :: gloopOutEn [12:12] */
#define TX_ALL_TX_ACONTROL0_GLOOPOUTEN_MASK                        0x1000
#define TX_ALL_TX_ACONTROL0_GLOOPOUTEN_ALIGN                       0
#define TX_ALL_TX_ACONTROL0_GLOOPOUTEN_BITS                        1
#define TX_ALL_TX_ACONTROL0_GLOOPOUTEN_SHIFT                       12

/* TX_All :: Tx_AControl0 :: reserved1 [11:09] */
#define TX_ALL_TX_ACONTROL0_RESERVED1_MASK                         0x0e00
#define TX_ALL_TX_ACONTROL0_RESERVED1_ALIGN                        0
#define TX_ALL_TX_ACONTROL0_RESERVED1_BITS                         3
#define TX_ALL_TX_ACONTROL0_RESERVED1_SHIFT                        9

/* TX_All :: Tx_AControl0 :: prbs_en [08:08] */
#define TX_ALL_TX_ACONTROL0_PRBS_EN_MASK                           0x0100
#define TX_ALL_TX_ACONTROL0_PRBS_EN_ALIGN                          0
#define TX_ALL_TX_ACONTROL0_PRBS_EN_BITS                           1
#define TX_ALL_TX_ACONTROL0_PRBS_EN_SHIFT                          8

/* TX_All :: Tx_AControl0 :: pckt_en [07:07] */
#define TX_ALL_TX_ACONTROL0_PCKT_EN_MASK                           0x0080
#define TX_ALL_TX_ACONTROL0_PCKT_EN_ALIGN                          0
#define TX_ALL_TX_ACONTROL0_PCKT_EN_BITS                           1
#define TX_ALL_TX_ACONTROL0_PCKT_EN_SHIFT                          7

/* TX_All :: Tx_AControl0 :: pckt_strt [06:06] */
#define TX_ALL_TX_ACONTROL0_PCKT_STRT_MASK                         0x0040
#define TX_ALL_TX_ACONTROL0_PCKT_STRT_ALIGN                        0
#define TX_ALL_TX_ACONTROL0_PCKT_STRT_BITS                         1
#define TX_ALL_TX_ACONTROL0_PCKT_STRT_SHIFT                        6

/* TX_All :: Tx_AControl0 :: txpol_flip [05:05] */
#define TX_ALL_TX_ACONTROL0_TXPOL_FLIP_MASK                        0x0020
#define TX_ALL_TX_ACONTROL0_TXPOL_FLIP_ALIGN                       0
#define TX_ALL_TX_ACONTROL0_TXPOL_FLIP_BITS                        1
#define TX_ALL_TX_ACONTROL0_TXPOL_FLIP_SHIFT                       5

/* TX_All :: Tx_AControl0 :: rtbi_flip [04:04] */
#define TX_ALL_TX_ACONTROL0_RTBI_FLIP_MASK                         0x0010
#define TX_ALL_TX_ACONTROL0_RTBI_FLIP_ALIGN                        0
#define TX_ALL_TX_ACONTROL0_RTBI_FLIP_BITS                         1
#define TX_ALL_TX_ACONTROL0_RTBI_FLIP_SHIFT                        4

/* TX_All :: Tx_AControl0 :: eden_r [03:03] */
#define TX_ALL_TX_ACONTROL0_EDEN_R_MASK                            0x0008
#define TX_ALL_TX_ACONTROL0_EDEN_R_ALIGN                           0
#define TX_ALL_TX_ACONTROL0_EDEN_R_BITS                            1
#define TX_ALL_TX_ACONTROL0_EDEN_R_SHIFT                           3

/* TX_All :: Tx_AControl0 :: eden_force_r [02:02] */
#define TX_ALL_TX_ACONTROL0_EDEN_FORCE_R_MASK                      0x0004
#define TX_ALL_TX_ACONTROL0_EDEN_FORCE_R_ALIGN                     0
#define TX_ALL_TX_ACONTROL0_EDEN_FORCE_R_BITS                      1
#define TX_ALL_TX_ACONTROL0_EDEN_FORCE_R_SHIFT                     2

/* TX_All :: Tx_AControl0 :: txpat_en [01:01] */
#define TX_ALL_TX_ACONTROL0_TXPAT_EN_MASK                          0x0002
#define TX_ALL_TX_ACONTROL0_TXPAT_EN_ALIGN                         0
#define TX_ALL_TX_ACONTROL0_TXPAT_EN_BITS                          1
#define TX_ALL_TX_ACONTROL0_TXPAT_EN_SHIFT                         1

/* TX_All :: Tx_AControl0 :: tx_mdata_en [00:00] */
#define TX_ALL_TX_ACONTROL0_TX_MDATA_EN_MASK                       0x0001
#define TX_ALL_TX_ACONTROL0_TX_MDATA_EN_ALIGN                      0
#define TX_ALL_TX_ACONTROL0_TX_MDATA_EN_BITS                       1
#define TX_ALL_TX_ACONTROL0_TX_MDATA_EN_SHIFT                      0


/****************************************************************************
 * TX_All :: Tx_mdata0
 ***************************************************************************/
/* TX_All :: Tx_mdata0 :: txTestMuxSel [15:13] */
#define TX_ALL_TX_MDATA0_TXTESTMUXSEL_MASK                         0xe000
#define TX_ALL_TX_MDATA0_TXTESTMUXSEL_ALIGN                        0
#define TX_ALL_TX_MDATA0_TXTESTMUXSEL_BITS                         3
#define TX_ALL_TX_MDATA0_TXTESTMUXSEL_SHIFT                        13

/* TX_All :: Tx_mdata0 :: rlfifo_tstsel [12:10] */
#define TX_ALL_TX_MDATA0_RLFIFO_TSTSEL_MASK                        0x1c00
#define TX_ALL_TX_MDATA0_RLFIFO_TSTSEL_ALIGN                       0
#define TX_ALL_TX_MDATA0_RLFIFO_TSTSEL_BITS                        3
#define TX_ALL_TX_MDATA0_RLFIFO_TSTSEL_SHIFT                       10

/* TX_All :: Tx_mdata0 :: TxMdioTstDataL [09:00] */
#define TX_ALL_TX_MDATA0_TXMDIOTSTDATAL_MASK                       0x03ff
#define TX_ALL_TX_MDATA0_TXMDIOTSTDATAL_ALIGN                      0
#define TX_ALL_TX_MDATA0_TXMDIOTSTDATAL_BITS                       10
#define TX_ALL_TX_MDATA0_TXMDIOTSTDATAL_SHIFT                      0


/****************************************************************************
 * TX_All :: Tx_mdata1
 ***************************************************************************/
/* TX_All :: Tx_mdata1 :: reserved0 [15:10] */
#define TX_ALL_TX_MDATA1_RESERVED0_MASK                            0xfc00
#define TX_ALL_TX_MDATA1_RESERVED0_ALIGN                           0
#define TX_ALL_TX_MDATA1_RESERVED0_BITS                            6
#define TX_ALL_TX_MDATA1_RESERVED0_SHIFT                           10

/* TX_All :: Tx_mdata1 :: TxMdioTstDataH [09:00] */
#define TX_ALL_TX_MDATA1_TXMDIOTSTDATAH_MASK                       0x03ff
#define TX_ALL_TX_MDATA1_TXMDIOTSTDATAH_ALIGN                      0
#define TX_ALL_TX_MDATA1_TXMDIOTSTDATAH_BITS                       10
#define TX_ALL_TX_MDATA1_TXMDIOTSTDATAH_SHIFT                      0


/****************************************************************************
 * TX_All :: Tx_AStatus1
 ***************************************************************************/
/* TX_All :: Tx_AStatus1 :: tx_id [15:14] */
#define TX_ALL_TX_ASTATUS1_TX_ID_MASK                              0xc000
#define TX_ALL_TX_ASTATUS1_TX_ID_ALIGN                             0
#define TX_ALL_TX_ASTATUS1_TX_ID_BITS                              2
#define TX_ALL_TX_ASTATUS1_TX_ID_SHIFT                             14

/* TX_All :: Tx_AStatus1 :: reserved0 [13:00] */
#define TX_ALL_TX_ASTATUS1_RESERVED0_MASK                          0x3fff
#define TX_ALL_TX_ASTATUS1_RESERVED0_ALIGN                         0
#define TX_ALL_TX_ASTATUS1_RESERVED0_BITS                          14
#define TX_ALL_TX_ASTATUS1_RESERVED0_SHIFT                         0


/****************************************************************************
 * TX_All :: Tx_BgVcm
 ***************************************************************************/
/* TX_All :: Tx_BgVcm :: id2c [15:13] */
#define TX_ALL_TX_BGVCM_ID2C_MASK                                  0xe000
#define TX_ALL_TX_BGVCM_ID2C_ALIGN                                 0
#define TX_ALL_TX_BGVCM_ID2C_BITS                                  3
#define TX_ALL_TX_BGVCM_ID2C_SHIFT                                 13

/* TX_All :: Tx_BgVcm :: refl_tx [12:12] */
#define TX_ALL_TX_BGVCM_REFL_TX_MASK                               0x1000
#define TX_ALL_TX_BGVCM_REFL_TX_ALIGN                              0
#define TX_ALL_TX_BGVCM_REFL_TX_BITS                               1
#define TX_ALL_TX_BGVCM_REFL_TX_SHIFT                              12

/* TX_All :: Tx_BgVcm :: refh_tx [11:11] */
#define TX_ALL_TX_BGVCM_REFH_TX_MASK                               0x0800
#define TX_ALL_TX_BGVCM_REFH_TX_ALIGN                              0
#define TX_ALL_TX_BGVCM_REFH_TX_BITS                               1
#define TX_ALL_TX_BGVCM_REFH_TX_SHIFT                              11

/* TX_All :: Tx_BgVcm :: newbias_en [10:10] */
#define TX_ALL_TX_BGVCM_NEWBIAS_EN_MASK                            0x0400
#define TX_ALL_TX_BGVCM_NEWBIAS_EN_ALIGN                           0
#define TX_ALL_TX_BGVCM_NEWBIAS_EN_BITS                            1
#define TX_ALL_TX_BGVCM_NEWBIAS_EN_SHIFT                           10

/* TX_All :: Tx_BgVcm :: drivermode [09:09] */
#define TX_ALL_TX_BGVCM_DRIVERMODE_MASK                            0x0200
#define TX_ALL_TX_BGVCM_DRIVERMODE_ALIGN                           0
#define TX_ALL_TX_BGVCM_DRIVERMODE_BITS                            1
#define TX_ALL_TX_BGVCM_DRIVERMODE_SHIFT                           9

/* TX_All :: Tx_BgVcm :: bddr_bgb [08:08] */
#define TX_ALL_TX_BGVCM_BDDR_BGB_MASK                              0x0100
#define TX_ALL_TX_BGVCM_BDDR_BGB_ALIGN                             0
#define TX_ALL_TX_BGVCM_BDDR_BGB_BITS                              1
#define TX_ALL_TX_BGVCM_BDDR_BGB_SHIFT                             8

/* TX_All :: Tx_BgVcm :: ticksel [07:06] */
#define TX_ALL_TX_BGVCM_TICKSEL_MASK                               0x00c0
#define TX_ALL_TX_BGVCM_TICKSEL_ALIGN                              0
#define TX_ALL_TX_BGVCM_TICKSEL_BITS                               2
#define TX_ALL_TX_BGVCM_TICKSEL_SHIFT                              6

/* TX_All :: Tx_BgVcm :: driver_vcm [05:04] */
#define TX_ALL_TX_BGVCM_DRIVER_VCM_MASK                            0x0030
#define TX_ALL_TX_BGVCM_DRIVER_VCM_ALIGN                           0
#define TX_ALL_TX_BGVCM_DRIVER_VCM_BITS                            2
#define TX_ALL_TX_BGVCM_DRIVER_VCM_SHIFT                           4

/* TX_All :: Tx_BgVcm :: tx_sel_halfrate [03:03] */
#define TX_ALL_TX_BGVCM_TX_SEL_HALFRATE_MASK                       0x0008
#define TX_ALL_TX_BGVCM_TX_SEL_HALFRATE_ALIGN                      0
#define TX_ALL_TX_BGVCM_TX_SEL_HALFRATE_BITS                       1
#define TX_ALL_TX_BGVCM_TX_SEL_HALFRATE_SHIFT                      3

/* TX_All :: Tx_BgVcm :: ifullspd [02:00] */
#define TX_ALL_TX_BGVCM_IFULLSPD_MASK                              0x0007
#define TX_ALL_TX_BGVCM_IFULLSPD_ALIGN                             0
#define TX_ALL_TX_BGVCM_IFULLSPD_BITS                              3
#define TX_ALL_TX_BGVCM_IFULLSPD_SHIFT                             0


/****************************************************************************
 * TX_All :: Tx_ibuff_1T2T
 ***************************************************************************/
/* TX_All :: Tx_ibuff_1T2T :: icbuf1t [15:14] */
#define TX_ALL_TX_IBUFF_1T2T_ICBUF1T_MASK                          0xc000
#define TX_ALL_TX_IBUFF_1T2T_ICBUF1T_ALIGN                         0
#define TX_ALL_TX_IBUFF_1T2T_ICBUF1T_BITS                          2
#define TX_ALL_TX_IBUFF_1T2T_ICBUF1T_SHIFT                         14

/* TX_All :: Tx_ibuff_1T2T :: icbuf2t [13:11] */
#define TX_ALL_TX_IBUFF_1T2T_ICBUF2T_MASK                          0x3800
#define TX_ALL_TX_IBUFF_1T2T_ICBUF2T_ALIGN                         0
#define TX_ALL_TX_IBUFF_1T2T_ICBUF2T_BITS                          3
#define TX_ALL_TX_IBUFF_1T2T_ICBUF2T_SHIFT                         11

/* TX_All :: Tx_ibuff_1T2T :: imin_predrv [10:10] */
#define TX_ALL_TX_IBUFF_1T2T_IMIN_PREDRV_MASK                      0x0400
#define TX_ALL_TX_IBUFF_1T2T_IMIN_PREDRV_ALIGN                     0
#define TX_ALL_TX_IBUFF_1T2T_IMIN_PREDRV_BITS                      1
#define TX_ALL_TX_IBUFF_1T2T_IMIN_PREDRV_SHIFT                     10

/* TX_All :: Tx_ibuff_1T2T :: imax_predrv [09:09] */
#define TX_ALL_TX_IBUFF_1T2T_IMAX_PREDRV_MASK                      0x0200
#define TX_ALL_TX_IBUFF_1T2T_IMAX_PREDRV_ALIGN                     0
#define TX_ALL_TX_IBUFF_1T2T_IMAX_PREDRV_BITS                      1
#define TX_ALL_TX_IBUFF_1T2T_IMAX_PREDRV_SHIFT                     9

/* TX_All :: Tx_ibuff_1T2T :: imode_predrv [08:08] */
#define TX_ALL_TX_IBUFF_1T2T_IMODE_PREDRV_MASK                     0x0100
#define TX_ALL_TX_IBUFF_1T2T_IMODE_PREDRV_ALIGN                    0
#define TX_ALL_TX_IBUFF_1T2T_IMODE_PREDRV_BITS                     1
#define TX_ALL_TX_IBUFF_1T2T_IMODE_PREDRV_SHIFT                    8

/* TX_All :: Tx_ibuff_1T2T :: i21mux [07:05] */
#define TX_ALL_TX_IBUFF_1T2T_I21MUX_MASK                           0x00e0
#define TX_ALL_TX_IBUFF_1T2T_I21MUX_ALIGN                          0
#define TX_ALL_TX_IBUFF_1T2T_I21MUX_BITS                           3
#define TX_ALL_TX_IBUFF_1T2T_I21MUX_SHIFT                          5

/* TX_All :: Tx_ibuff_1T2T :: imin_drvr [04:04] */
#define TX_ALL_TX_IBUFF_1T2T_IMIN_DRVR_MASK                        0x0010
#define TX_ALL_TX_IBUFF_1T2T_IMIN_DRVR_ALIGN                       0
#define TX_ALL_TX_IBUFF_1T2T_IMIN_DRVR_BITS                        1
#define TX_ALL_TX_IBUFF_1T2T_IMIN_DRVR_SHIFT                       4

/* TX_All :: Tx_ibuff_1T2T :: imax_drvr [03:03] */
#define TX_ALL_TX_IBUFF_1T2T_IMAX_DRVR_MASK                        0x0008
#define TX_ALL_TX_IBUFF_1T2T_IMAX_DRVR_ALIGN                       0
#define TX_ALL_TX_IBUFF_1T2T_IMAX_DRVR_BITS                        1
#define TX_ALL_TX_IBUFF_1T2T_IMAX_DRVR_SHIFT                       3

/* TX_All :: Tx_ibuff_1T2T :: imode_drvr [02:02] */
#define TX_ALL_TX_IBUFF_1T2T_IMODE_DRVR_MASK                       0x0004
#define TX_ALL_TX_IBUFF_1T2T_IMODE_DRVR_ALIGN                      0
#define TX_ALL_TX_IBUFF_1T2T_IMODE_DRVR_BITS                       1
#define TX_ALL_TX_IBUFF_1T2T_IMODE_DRVR_SHIFT                      2

/* TX_All :: Tx_ibuff_1T2T :: reserved0 [01:00] */
#define TX_ALL_TX_IBUFF_1T2T_RESERVED0_MASK                        0x0003
#define TX_ALL_TX_IBUFF_1T2T_RESERVED0_ALIGN                       0
#define TX_ALL_TX_IBUFF_1T2T_RESERVED0_BITS                        2
#define TX_ALL_TX_IBUFF_1T2T_RESERVED0_SHIFT                       0


/****************************************************************************
 * TX_All :: Tx_Driver
 ***************************************************************************/
/* TX_All :: Tx_Driver :: preemphasis_post [15:12] */
#define TX_ALL_TX_DRIVER_PREEMPHASIS_MASK                          0xf000
#define TX_ALL_TX_DRIVER_PREEMPHASIS_ALIGN                         0
#define TX_ALL_TX_DRIVER_PREEMPHASIS_BITS                          4
#define TX_ALL_TX_DRIVER_PREEMPHASIS_SHIFT                         12

/* TX_All :: Tx_Driver :: Idriver [11:08] */
#define TX_ALL_TX_DRIVER_IDRIVER_MASK                              0x0f00
#define TX_ALL_TX_DRIVER_IDRIVER_ALIGN                             0
#define TX_ALL_TX_DRIVER_IDRIVER_BITS                              4
#define TX_ALL_TX_DRIVER_IDRIVER_SHIFT                             8

/* TX_All :: Tx_Driver :: Ipredriver [07:04] */
#define TX_ALL_TX_DRIVER_IPREDRIVER_MASK                           0x00f0
#define TX_ALL_TX_DRIVER_IPREDRIVER_ALIGN                          0
#define TX_ALL_TX_DRIVER_IPREDRIVER_BITS                           4
#define TX_ALL_TX_DRIVER_IPREDRIVER_SHIFT                          4

/* TX_All :: Tx_Driver :: ifull_spd [03:01] */
#define TX_ALL_TX_DRIVER_IFULLSPD_MASK                             0x000e
#define TX_ALL_TX_DRIVER_IFULLSPD_ALIGN                            0
#define TX_ALL_TX_DRIVER_IFULLSPD_BITS                             3
#define TX_ALL_TX_DRIVER_IFULLSPD_SHIFT                            1

/* TX_All :: Tx_Driver :: icbuf1t0 [00:00] */
#define TX_ALL_TX_DRIVER_ICBUF1T0_MASK                             0x0001
#define TX_ALL_TX_DRIVER_ICBUF1T0_ALIGN                            0
#define TX_ALL_TX_DRIVER_ICBUF1T0_BITS                             1
#define TX_ALL_TX_DRIVER_ICBUF1T0_SHIFT                            0


/****************************************************************************
 * XGXS16G_USER_RX0
 ***************************************************************************/
/****************************************************************************
 * RX0 :: Rx_Status
 ***************************************************************************/
/* union - case sigdet_Status [15:00] */
/* RX0 :: Rx_Status :: cx4_sigdet [15:15] */
#define RX0_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_MASK                0x8000
#define RX0_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_ALIGN               0
#define RX0_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_BITS                1
#define RX0_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_SHIFT               15

/* RX0 :: Rx_Status :: reserved0 [14:13] */
#define RX0_RX_STATUS_SIGDET_STATUS_RESERVED0_MASK                 0x6000
#define RX0_RX_STATUS_SIGDET_STATUS_RESERVED0_ALIGN                0
#define RX0_RX_STATUS_SIGDET_STATUS_RESERVED0_BITS                 2
#define RX0_RX_STATUS_SIGDET_STATUS_RESERVED0_SHIFT                13

/* RX0 :: Rx_Status :: rxSeqDone [12:12] */
#define RX0_RX_STATUS_SIGDET_STATUS_RXSEQDONE_MASK                 0x1000
#define RX0_RX_STATUS_SIGDET_STATUS_RXSEQDONE_ALIGN                0
#define RX0_RX_STATUS_SIGDET_STATUS_RXSEQDONE_BITS                 1
#define RX0_RX_STATUS_SIGDET_STATUS_RXSEQDONE_SHIFT                12

/* RX0 :: Rx_Status :: rx_sigdet_ll [11:11] */
#define RX0_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_MASK              0x0800
#define RX0_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_ALIGN             0
#define RX0_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_BITS              1
#define RX0_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_SHIFT             11

/* RX0 :: Rx_Status :: cs4_sigdet_ll [10:10] */
#define RX0_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_MASK             0x0400
#define RX0_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_ALIGN            0
#define RX0_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_BITS             1
#define RX0_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_SHIFT            10

/* RX0 :: Rx_Status :: rx_reset [09:09] */
#define RX0_RX_STATUS_SIGDET_STATUS_RX_RESET_MASK                  0x0200
#define RX0_RX_STATUS_SIGDET_STATUS_RX_RESET_ALIGN                 0
#define RX0_RX_STATUS_SIGDET_STATUS_RX_RESET_BITS                  1
#define RX0_RX_STATUS_SIGDET_STATUS_RX_RESET_SHIFT                 9

/* RX0 :: Rx_Status :: rx_pwrdn [08:08] */
#define RX0_RX_STATUS_SIGDET_STATUS_RX_PWRDN_MASK                  0x0100
#define RX0_RX_STATUS_SIGDET_STATUS_RX_PWRDN_ALIGN                 0
#define RX0_RX_STATUS_SIGDET_STATUS_RX_PWRDN_BITS                  1
#define RX0_RX_STATUS_SIGDET_STATUS_RX_PWRDN_SHIFT                 8

/* RX0 :: Rx_Status :: reserved1 [07:00] */
#define RX0_RX_STATUS_SIGDET_STATUS_RESERVED1_MASK                 0x00ff
#define RX0_RX_STATUS_SIGDET_STATUS_RESERVED1_ALIGN                0
#define RX0_RX_STATUS_SIGDET_STATUS_RESERVED1_BITS                 8
#define RX0_RX_STATUS_SIGDET_STATUS_RESERVED1_SHIFT                0


/* union - case sync_Status [15:00] */
/* RX0 :: Rx_Status :: reserved0 [15:11] */
#define RX0_RX_STATUS_SYNC_STATUS_RESERVED0_MASK                   0xf800
#define RX0_RX_STATUS_SYNC_STATUS_RESERVED0_ALIGN                  0
#define RX0_RX_STATUS_SYNC_STATUS_RESERVED0_BITS                   5
#define RX0_RX_STATUS_SYNC_STATUS_RESERVED0_SHIFT                  11

/* RX0 :: Rx_Status :: test_acq_en [10:10] */
#define RX0_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_MASK                 0x0400
#define RX0_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_ALIGN                0
#define RX0_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_BITS                 1
#define RX0_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_SHIFT                10

/* RX0 :: Rx_Status :: reserved1 [09:09] */
#define RX0_RX_STATUS_SYNC_STATUS_RESERVED1_MASK                   0x0200
#define RX0_RX_STATUS_SYNC_STATUS_RESERVED1_ALIGN                  0
#define RX0_RX_STATUS_SYNC_STATUS_RESERVED1_BITS                   1
#define RX0_RX_STATUS_SYNC_STATUS_RESERVED1_SHIFT                  9

/* RX0 :: Rx_Status :: rxSeqStart [08:08] */
#define RX0_RX_STATUS_SYNC_STATUS_RXSEQSTART_MASK                  0x0100
#define RX0_RX_STATUS_SYNC_STATUS_RXSEQSTART_ALIGN                 0
#define RX0_RX_STATUS_SYNC_STATUS_RXSEQSTART_BITS                  1
#define RX0_RX_STATUS_SYNC_STATUS_RXSEQSTART_SHIFT                 8

/* RX0 :: Rx_Status :: mux_comadj_sync_status [07:07] */
#define RX0_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_MASK      0x0080
#define RX0_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_ALIGN     0
#define RX0_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_BITS      1
#define RX0_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_SHIFT     7

/* RX0 :: Rx_Status :: sync_status [06:06] */
#define RX0_RX_STATUS_SYNC_STATUS_SYNC_STATUS_MASK                 0x0040
#define RX0_RX_STATUS_SYNC_STATUS_SYNC_STATUS_ALIGN                0
#define RX0_RX_STATUS_SYNC_STATUS_SYNC_STATUS_BITS                 1
#define RX0_RX_STATUS_SYNC_STATUS_SYNC_STATUS_SHIFT                6

/* RX0 :: Rx_Status :: rx_sigdet [05:05] */
#define RX0_RX_STATUS_SYNC_STATUS_RX_SIGDET_MASK                   0x0020
#define RX0_RX_STATUS_SYNC_STATUS_RX_SIGDET_ALIGN                  0
#define RX0_RX_STATUS_SYNC_STATUS_RX_SIGDET_BITS                   1
#define RX0_RX_STATUS_SYNC_STATUS_RX_SIGDET_SHIFT                  5

/* RX0 :: Rx_Status :: reserved2 [04:03] */
#define RX0_RX_STATUS_SYNC_STATUS_RESERVED2_MASK                   0x0018
#define RX0_RX_STATUS_SYNC_STATUS_RESERVED2_ALIGN                  0
#define RX0_RX_STATUS_SYNC_STATUS_RESERVED2_BITS                   2
#define RX0_RX_STATUS_SYNC_STATUS_RESERVED2_SHIFT                  3

/* RX0 :: Rx_Status :: saturate_status [02:02] */
#define RX0_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_MASK             0x0004
#define RX0_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_ALIGN            0
#define RX0_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_BITS             1
#define RX0_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_SHIFT            2

/* RX0 :: Rx_Status :: cx4_sigdet [01:01] */
#define RX0_RX_STATUS_SYNC_STATUS_CX4_SIGDET_MASK                  0x0002
#define RX0_RX_STATUS_SYNC_STATUS_CX4_SIGDET_ALIGN                 0
#define RX0_RX_STATUS_SYNC_STATUS_CX4_SIGDET_BITS                  1
#define RX0_RX_STATUS_SYNC_STATUS_CX4_SIGDET_SHIFT                 1

/* RX0 :: Rx_Status :: rxSeqDone [00:00] */
#define RX0_RX_STATUS_SYNC_STATUS_RXSEQDONE_MASK                   0x0001
#define RX0_RX_STATUS_SYNC_STATUS_RXSEQDONE_ALIGN                  0
#define RX0_RX_STATUS_SYNC_STATUS_RXSEQDONE_BITS                   1
#define RX0_RX_STATUS_SYNC_STATUS_RXSEQDONE_SHIFT                  0


/* union - case rxTestSel_0 [15:00] */
/* RX0 :: Rx_Status :: reserved0 [15:10] */
#define RX0_RX_STATUS_RXTESTSEL_0_RESERVED0_MASK                   0xfc00
#define RX0_RX_STATUS_RXTESTSEL_0_RESERVED0_ALIGN                  0
#define RX0_RX_STATUS_RXTESTSEL_0_RESERVED0_BITS                   6
#define RX0_RX_STATUS_RXTESTSEL_0_RESERVED0_SHIFT                  10

/* RX0 :: Rx_Status :: indck_mode_en [09:09] */
#define RX0_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_MASK               0x0200
#define RX0_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_ALIGN              0
#define RX0_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_BITS               1
#define RX0_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_SHIFT              9

/* RX0 :: Rx_Status :: pci_mode_en [08:08] */
#define RX0_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_MASK                 0x0100
#define RX0_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_ALIGN                0
#define RX0_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_BITS                 1
#define RX0_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_SHIFT                8

/* RX0 :: Rx_Status :: rx_polarity [07:07] */
#define RX0_RX_STATUS_RXTESTSEL_0_RX_POLARITY_MASK                 0x0080
#define RX0_RX_STATUS_RXTESTSEL_0_RX_POLARITY_ALIGN                0
#define RX0_RX_STATUS_RXTESTSEL_0_RX_POLARITY_BITS                 1
#define RX0_RX_STATUS_RXTESTSEL_0_RX_POLARITY_SHIFT                7

/* RX0 :: Rx_Status :: rxpol_flip [06:06] */
#define RX0_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_MASK                  0x0040
#define RX0_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_ALIGN                 0
#define RX0_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_BITS                  1
#define RX0_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_SHIFT                 6

/* RX0 :: Rx_Status :: comma_mask [05:05] */
#define RX0_RX_STATUS_RXTESTSEL_0_COMMA_MASK_MASK                  0x0020
#define RX0_RX_STATUS_RXTESTSEL_0_COMMA_MASK_ALIGN                 0
#define RX0_RX_STATUS_RXTESTSEL_0_COMMA_MASK_BITS                  1
#define RX0_RX_STATUS_RXTESTSEL_0_COMMA_MASK_SHIFT                 5

/* RX0 :: Rx_Status :: link_en_r [04:04] */
#define RX0_RX_STATUS_RXTESTSEL_0_LINK_EN_R_MASK                   0x0010
#define RX0_RX_STATUS_RXTESTSEL_0_LINK_EN_R_ALIGN                  0
#define RX0_RX_STATUS_RXTESTSEL_0_LINK_EN_R_BITS                   1
#define RX0_RX_STATUS_RXTESTSEL_0_LINK_EN_R_SHIFT                  4

/* RX0 :: Rx_Status :: comma_adj_en [03:03] */
#define RX0_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_MASK                0x0008
#define RX0_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_ALIGN               0
#define RX0_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_BITS                1
#define RX0_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_SHIFT               3

/* RX0 :: Rx_Status :: comma_adj_en_ext [02:02] */
#define RX0_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_MASK            0x0004
#define RX0_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_ALIGN           0
#define RX0_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_BITS            1
#define RX0_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_SHIFT           2

/* RX0 :: Rx_Status :: reserved1 [01:00] */
#define RX0_RX_STATUS_RXTESTSEL_0_RESERVED1_MASK                   0x0003
#define RX0_RX_STATUS_RXTESTSEL_0_RESERVED1_ALIGN                  0
#define RX0_RX_STATUS_RXTESTSEL_0_RESERVED1_BITS                   2
#define RX0_RX_STATUS_RXTESTSEL_0_RESERVED1_SHIFT                  0


/* union - case rxTestSel_1 [15:00] */
/* RX0 :: Rx_Status :: reserved0 [15:05] */
#define RX0_RX_STATUS_RXTESTSEL_1_RESERVED0_MASK                   0xffe0
#define RX0_RX_STATUS_RXTESTSEL_1_RESERVED0_ALIGN                  0
#define RX0_RX_STATUS_RXTESTSEL_1_RESERVED0_BITS                   11
#define RX0_RX_STATUS_RXTESTSEL_1_RESERVED0_SHIFT                  5

/* RX0 :: Rx_Status :: cdrAcqDone_r2 [04:04] */
#define RX0_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_MASK               0x0010
#define RX0_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_ALIGN              0
#define RX0_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_BITS               1
#define RX0_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_SHIFT              4

/* RX0 :: Rx_Status :: freq_sel_PC [03:03] */
#define RX0_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_MASK                 0x0008
#define RX0_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_ALIGN                0
#define RX0_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_BITS                 1
#define RX0_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_SHIFT                3

/* RX0 :: Rx_Status :: freq_sel_SM [02:02] */
#define RX0_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_MASK                 0x0004
#define RX0_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_ALIGN                0
#define RX0_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_BITS                 1
#define RX0_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_SHIFT                2

/* RX0 :: Rx_Status :: integ_mode_SM [01:00] */
#define RX0_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_MASK               0x0003
#define RX0_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_ALIGN              0
#define RX0_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_BITS               2
#define RX0_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_SHIFT              0


/* union - case scale_Status [15:00] */
/* RX0 :: Rx_Status :: prop_scale [15:12] */
#define RX0_RX_STATUS_SCALE_STATUS_PROP_SCALE_MASK                 0xf000
#define RX0_RX_STATUS_SCALE_STATUS_PROP_SCALE_ALIGN                0
#define RX0_RX_STATUS_SCALE_STATUS_PROP_SCALE_BITS                 4
#define RX0_RX_STATUS_SCALE_STATUS_PROP_SCALE_SHIFT                12

/* RX0 :: Rx_Status :: integ_scale [11:08] */
#define RX0_RX_STATUS_SCALE_STATUS_INTEG_SCALE_MASK                0x0f00
#define RX0_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ALIGN               0
#define RX0_RX_STATUS_SCALE_STATUS_INTEG_SCALE_BITS                4
#define RX0_RX_STATUS_SCALE_STATUS_INTEG_SCALE_SHIFT               8

/* RX0 :: Rx_Status :: prop_scale_acq [07:04] */
#define RX0_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_MASK             0x00f0
#define RX0_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_ALIGN            0
#define RX0_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_BITS             4
#define RX0_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_SHIFT            4

/* RX0 :: Rx_Status :: integ_scale_acq [03:00] */
#define RX0_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_MASK            0x000f
#define RX0_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_ALIGN           0
#define RX0_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_BITS            4
#define RX0_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_SHIFT           0


/* union - case adc_CdrStatus1 [15:00] */
/* RX0 :: Rx_Status :: reserved0 [15:07] */
#define RX0_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_MASK                0xff80
#define RX0_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_ALIGN               0
#define RX0_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_BITS                9
#define RX0_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_SHIFT               7

/* RX0 :: Rx_Status :: rxMuxCkSel [06:06] */
#define RX0_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_MASK               0x0040
#define RX0_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_ALIGN              0
#define RX0_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_BITS               1
#define RX0_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_SHIFT              6

/* RX0 :: Rx_Status :: glpbk_combo [05:05] */
#define RX0_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_MASK              0x0020
#define RX0_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_ALIGN             0
#define RX0_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_BITS              1
#define RX0_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_SHIFT             5

/* RX0 :: Rx_Status :: clockSwitchSel [04:04] */
#define RX0_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_MASK           0x0010
#define RX0_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_ALIGN          0
#define RX0_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_BITS           1
#define RX0_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_SHIFT          4

/* RX0 :: Rx_Status :: rxck_tst [03:03] */
#define RX0_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_MASK                 0x0008
#define RX0_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_ALIGN                0
#define RX0_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_BITS                 1
#define RX0_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_SHIFT                3

/* RX0 :: Rx_Status :: rxck_i [02:02] */
#define RX0_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_MASK                   0x0004
#define RX0_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_ALIGN                  0
#define RX0_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_BITS                   1
#define RX0_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_SHIFT                  2

/* RX0 :: Rx_Status :: refclk [01:01] */
#define RX0_RX_STATUS_ADC_CDRSTATUS1_REFCLK_MASK                   0x0002
#define RX0_RX_STATUS_ADC_CDRSTATUS1_REFCLK_ALIGN                  0
#define RX0_RX_STATUS_ADC_CDRSTATUS1_REFCLK_BITS                   1
#define RX0_RX_STATUS_ADC_CDRSTATUS1_REFCLK_SHIFT                  1

/* RX0 :: Rx_Status :: pll_bypass [00:00] */
#define RX0_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_MASK               0x0001
#define RX0_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_ALIGN              0
#define RX0_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_BITS               1
#define RX0_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_SHIFT              0


/* union - case adc_CdrStatus2 [15:00] */
/* RX0 :: Rx_Status :: reserved0 [15:06] */
#define RX0_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_MASK                0xffc0
#define RX0_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_ALIGN               0
#define RX0_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_BITS                10
#define RX0_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_SHIFT               6

/* RX0 :: Rx_Status :: rxMuxCkSel [05:05] */
#define RX0_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_MASK               0x0020
#define RX0_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_ALIGN              0
#define RX0_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_BITS               1
#define RX0_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_SHIFT              5

/* RX0 :: Rx_Status :: rxSeqStart [04:04] */
#define RX0_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_MASK               0x0010
#define RX0_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_ALIGN              0
#define RX0_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_BITS               1
#define RX0_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_SHIFT              4

/* RX0 :: Rx_Status :: reserved1 [03:01] */
#define RX0_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_MASK                0x000e
#define RX0_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_ALIGN               0
#define RX0_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_BITS                3
#define RX0_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_SHIFT               1

/* RX0 :: Rx_Status :: rxSeqDone [00:00] */
#define RX0_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_MASK                0x0001
#define RX0_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_ALIGN               0
#define RX0_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_BITS                1
#define RX0_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_SHIFT               0


/* union - case adc_CdrStatus3 [15:00] */
/* RX0 :: Rx_Status :: reserved0 [15:04] */
#define RX0_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_MASK                0xfff0
#define RX0_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_ALIGN               0
#define RX0_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_BITS                12
#define RX0_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_SHIFT               4

/* RX0 :: Rx_Status :: rxSeqStart [03:03] */
#define RX0_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_MASK               0x0008
#define RX0_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_ALIGN              0
#define RX0_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_BITS               1
#define RX0_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_SHIFT              3

/* RX0 :: Rx_Status :: reserved1 [02:01] */
#define RX0_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_MASK                0x0006
#define RX0_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_ALIGN               0
#define RX0_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_BITS                2
#define RX0_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_SHIFT               1

/* RX0 :: Rx_Status :: allow_increment_PC [00:00] */
#define RX0_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_MASK       0x0001
#define RX0_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_ALIGN      0
#define RX0_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_BITS       1
#define RX0_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_SHIFT      0


/* union - case adc_CdrStatus4 [15:00] */
/* RX0 :: Rx_Status :: reserved0 [15:08] */
#define RX0_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_MASK                0xff00
#define RX0_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_ALIGN               0
#define RX0_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_BITS                8
#define RX0_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_SHIFT               8

/* RX0 :: Rx_Status :: rx_pwrdn [07:07] */
#define RX0_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_MASK                 0x0080
#define RX0_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_ALIGN                0
#define RX0_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_BITS                 1
#define RX0_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_SHIFT                7

/* RX0 :: Rx_Status :: freq_sel [06:06] */
#define RX0_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_MASK                 0x0040
#define RX0_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_ALIGN                0
#define RX0_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_BITS                 1
#define RX0_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_SHIFT                6

/* RX0 :: Rx_Status :: pll_lock_rstb [05:05] */
#define RX0_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_MASK            0x0020
#define RX0_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_ALIGN           0
#define RX0_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_BITS            1
#define RX0_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_SHIFT           5

/* RX0 :: Rx_Status :: pwrdn [04:04] */
#define RX0_RX_STATUS_ADC_CDRSTATUS4_PWRDN_MASK                    0x0010
#define RX0_RX_STATUS_ADC_CDRSTATUS4_PWRDN_ALIGN                   0
#define RX0_RX_STATUS_ADC_CDRSTATUS4_PWRDN_BITS                    1
#define RX0_RX_STATUS_ADC_CDRSTATUS4_PWRDN_SHIFT                   4

/* RX0 :: Rx_Status :: reserved1 [03:00] */
#define RX0_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_MASK                0x000f
#define RX0_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_ALIGN               0
#define RX0_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_BITS                4
#define RX0_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_SHIFT               0


/* union - case adc_CdrStatus5 [15:00] */
/* RX0 :: Rx_Status :: reserved0 [15:00] */
#define RX0_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_MASK                0xffff
#define RX0_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_ALIGN               0
#define RX0_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_BITS                16
#define RX0_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_SHIFT               0


/* union - case adc_CdrStatus6 [15:00] */
/* RX0 :: Rx_Status :: reserved0 [15:05] */
#define RX0_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_MASK                0xffe0
#define RX0_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_ALIGN               0
#define RX0_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_BITS                11
#define RX0_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_SHIFT               5

/* RX0 :: Rx_Status :: rx_reset [04:04] */
#define RX0_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_MASK                 0x0010
#define RX0_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_ALIGN                0
#define RX0_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_BITS                 1
#define RX0_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_SHIFT                4

/* RX0 :: Rx_Status :: rx_pwrdn [03:03] */
#define RX0_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_MASK                 0x0008
#define RX0_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_ALIGN                0
#define RX0_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_BITS                 1
#define RX0_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_SHIFT                3

/* RX0 :: Rx_Status :: reset_anlg [02:02] */
#define RX0_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_MASK               0x0004
#define RX0_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_ALIGN              0
#define RX0_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_BITS               1
#define RX0_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_SHIFT              2

/* RX0 :: Rx_Status :: pwrdn_rx [01:01] */
#define RX0_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_MASK                 0x0002
#define RX0_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_ALIGN                0
#define RX0_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_BITS                 1
#define RX0_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_SHIFT                1

/* RX0 :: Rx_Status :: pwrdn_pll [00:00] */
#define RX0_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_MASK                0x0001
#define RX0_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_ALIGN               0
#define RX0_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_BITS                1
#define RX0_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_SHIFT               0


/* union - case adc_CdrStatus7e [15:00] */
/* RX0 :: Rx_Status :: reserved0 [15:05] */
#define RX0_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_MASK               0xffe0
#define RX0_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_ALIGN              0
#define RX0_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_BITS               11
#define RX0_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_SHIFT              5

/* RX0 :: Rx_Status :: rxck0_even [04:04] */
#define RX0_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_MASK              0x0010
#define RX0_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_ALIGN             0
#define RX0_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_BITS              1
#define RX0_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_SHIFT             4

/* RX0 :: Rx_Status :: rxck1_even [03:03] */
#define RX0_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_MASK              0x0008
#define RX0_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_ALIGN             0
#define RX0_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_BITS              1
#define RX0_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_SHIFT             3

/* RX0 :: Rx_Status :: comdet_even [02:02] */
#define RX0_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_MASK             0x0004
#define RX0_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_ALIGN            0
#define RX0_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_BITS             1
#define RX0_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_SHIFT            2

/* RX0 :: Rx_Status :: en_cdet_even [01:01] */
#define RX0_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_MASK            0x0002
#define RX0_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_ALIGN           0
#define RX0_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_BITS            1
#define RX0_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_SHIFT           1

/* RX0 :: Rx_Status :: comma_adj_en_even [00:00] */
#define RX0_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_MASK       0x0001
#define RX0_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_ALIGN      0
#define RX0_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_BITS       1
#define RX0_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_SHIFT      0


/* union - case adc_CdrStatus7o [15:00] */
/* RX0 :: Rx_Status :: reserved0 [15:05] */
#define RX0_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_MASK               0xffe0
#define RX0_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_ALIGN              0
#define RX0_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_BITS               11
#define RX0_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_SHIFT              5

/* RX0 :: Rx_Status :: rxck0_odd [04:04] */
#define RX0_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_MASK               0x0010
#define RX0_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_ALIGN              0
#define RX0_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_BITS               1
#define RX0_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_SHIFT              4

/* RX0 :: Rx_Status :: rxck1_odd [03:03] */
#define RX0_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_MASK               0x0008
#define RX0_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_ALIGN              0
#define RX0_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_BITS               1
#define RX0_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_SHIFT              3

/* RX0 :: Rx_Status :: comdet_odd [02:02] */
#define RX0_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_MASK              0x0004
#define RX0_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_ALIGN             0
#define RX0_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_BITS              1
#define RX0_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_SHIFT             2

/* RX0 :: Rx_Status :: en_cdet_odd [01:01] */
#define RX0_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_MASK             0x0002
#define RX0_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_ALIGN            0
#define RX0_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_BITS             1
#define RX0_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_SHIFT            1

/* RX0 :: Rx_Status :: comma_adj_en_odd [00:00] */
#define RX0_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_MASK        0x0001
#define RX0_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_ALIGN       0
#define RX0_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_BITS        1
#define RX0_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_SHIFT       0


/* union - case adc_CdrStatus8 [15:00] */
/* RX0 :: Rx_Status :: reserved0 [15:01] */
#define RX0_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_MASK                0xfffe
#define RX0_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_ALIGN               0
#define RX0_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_BITS                15
#define RX0_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_SHIFT               1

/* RX0 :: Rx_Status :: sigdet [00:00] */
#define RX0_RX_STATUS_ADC_CDRSTATUS8_SIGDET_MASK                   0x0001
#define RX0_RX_STATUS_ADC_CDRSTATUS8_SIGDET_ALIGN                  0
#define RX0_RX_STATUS_ADC_CDRSTATUS8_SIGDET_BITS                   1
#define RX0_RX_STATUS_ADC_CDRSTATUS8_SIGDET_SHIFT                  0


/* union - case adc_CdrStatus9 [15:00] */
/* RX0 :: Rx_Status :: reserved0 [15:00] */
#define RX0_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_MASK                0xffff
#define RX0_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_ALIGN               0
#define RX0_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_BITS                16
#define RX0_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_SHIFT               0


/* union - case adc_CdrStatus10 [15:00] */
/* RX0 :: Rx_Status :: reserved0 [15:07] */
#define RX0_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_MASK               0xff80
#define RX0_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_ALIGN              0
#define RX0_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_BITS               9
#define RX0_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_SHIFT              7

/* RX0 :: Rx_Status :: prbs_en [06:06] */
#define RX0_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_MASK                 0x0040
#define RX0_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_ALIGN                0
#define RX0_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_BITS                 1
#define RX0_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_SHIFT                6

/* RX0 :: Rx_Status :: rstb_tst [05:05] */
#define RX0_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_MASK                0x0020
#define RX0_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_ALIGN               0
#define RX0_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_BITS                1
#define RX0_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_SHIFT               5

/* RX0 :: Rx_Status :: reserved1 [04:04] */
#define RX0_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_MASK               0x0010
#define RX0_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_ALIGN              0
#define RX0_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_BITS               1
#define RX0_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_SHIFT              4

/* RX0 :: Rx_Status :: prbs_state [03:00] */
#define RX0_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_MASK              0x000f
#define RX0_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_ALIGN             0
#define RX0_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_BITS              4
#define RX0_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_SHIFT             0


/* union - case adc_CdrStatus11 [15:00] */
/* RX0 :: Rx_Status :: reserved0 [15:00] */
#define RX0_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_MASK               0xffff
#define RX0_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_ALIGN              0
#define RX0_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_BITS               16
#define RX0_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_SHIFT              0


/* union - case adc_CdrStatus12_1 [15:00] */
/* RX0 :: Rx_Status :: reserved0 [15:06] */
#define RX0_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_MASK             0xffc0
#define RX0_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_ALIGN            0
#define RX0_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_BITS             10
#define RX0_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_SHIFT            6

/* RX0 :: Rx_Status :: enable4 [05:05] */
#define RX0_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_MASK               0x0020
#define RX0_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_ALIGN              0
#define RX0_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_BITS               1
#define RX0_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_SHIFT              5

/* RX0 :: Rx_Status :: radr_test [04:00] */
#define RX0_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_MASK             0x001f
#define RX0_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_ALIGN            0
#define RX0_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_BITS             5
#define RX0_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_SHIFT            0


/* union - case adc_CdrStatus12_2 [15:00] */
/* RX0 :: Rx_Status :: reserved0 [15:05] */
#define RX0_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_MASK             0xffe0
#define RX0_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_ALIGN            0
#define RX0_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_BITS             11
#define RX0_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_SHIFT            5

/* RX0 :: Rx_Status :: wadr_test [04:00] */
#define RX0_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_MASK             0x001f
#define RX0_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_ALIGN            0
#define RX0_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_BITS             5
#define RX0_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_SHIFT            0


/* union - case adc_CdrStatus12_3 [15:00] */
/* RX0 :: Rx_Status :: reserved0 [15:06] */
#define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_MASK             0xffc0
#define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_ALIGN            0
#define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_BITS             10
#define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_SHIFT            6

/* RX0 :: Rx_Status :: rxck_66B_tmux [05:05] */
#define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_MASK         0x0020
#define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_ALIGN        0
#define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_BITS         1
#define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_SHIFT        5

/* RX0 :: Rx_Status :: rstb_66B [04:04] */
#define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_MASK              0x0010
#define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_ALIGN             0
#define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_BITS              1
#define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_SHIFT             4

/* RX0 :: Rx_Status :: prstb_66B_mux [03:03] */
#define RX0_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_MASK         0x0008
#define RX0_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_ALIGN        0
#define RX0_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_BITS         1
#define RX0_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_SHIFT        3

/* RX0 :: Rx_Status :: rxck_i66_tmux [02:02] */
#define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_MASK         0x0004
#define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_ALIGN        0
#define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_BITS         1
#define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_SHIFT        2

/* RX0 :: Rx_Status :: rstb_i66 [01:01] */
#define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_MASK              0x0002
#define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_ALIGN             0
#define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_BITS              1
#define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_SHIFT             1

/* RX0 :: Rx_Status :: prstb_i66_mux [00:00] */
#define RX0_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_MASK         0x0001
#define RX0_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_ALIGN        0
#define RX0_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_BITS         1
#define RX0_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_SHIFT        0


/* union - case adc_CdrStatus12_4 [15:00] */
/* RX0 :: Rx_Status :: reserved0 [15:04] */
#define RX0_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_MASK             0xfff0
#define RX0_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_ALIGN            0
#define RX0_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_BITS             12
#define RX0_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_SHIFT            4

/* RX0 :: Rx_Status :: rfifo_error_r [03:02] */
#define RX0_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_MASK         0x000c
#define RX0_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_ALIGN        0
#define RX0_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_BITS         2
#define RX0_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_SHIFT        2

/* RX0 :: Rx_Status :: rfifo_unflow [01:01] */
#define RX0_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_MASK          0x0002
#define RX0_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_ALIGN         0
#define RX0_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_BITS          1
#define RX0_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_SHIFT         1

/* RX0 :: Rx_Status :: rfifo_ovflow [00:00] */
#define RX0_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_MASK          0x0001
#define RX0_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_ALIGN         0
#define RX0_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_BITS          1
#define RX0_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_SHIFT         0


/* union - case integ_Status [15:00] */
/* RX0 :: Rx_Status :: integ_status [15:00] */
#define RX0_RX_STATUS_INTEG_STATUS_INTEG_STATUS_MASK               0xffff
#define RX0_RX_STATUS_INTEG_STATUS_INTEG_STATUS_ALIGN              0
#define RX0_RX_STATUS_INTEG_STATUS_INTEG_STATUS_BITS               16
#define RX0_RX_STATUS_INTEG_STATUS_INTEG_STATUS_SHIFT              0


/* union - case vco_Status [15:00] */
/* RX0 :: Rx_Status :: vco_status [15:00] */
#define RX0_RX_STATUS_VCO_STATUS_VCO_STATUS_MASK                   0xffff
#define RX0_RX_STATUS_VCO_STATUS_VCO_STATUS_ALIGN                  0
#define RX0_RX_STATUS_VCO_STATUS_VCO_STATUS_BITS                   16
#define RX0_RX_STATUS_VCO_STATUS_VCO_STATUS_SHIFT                  0


/* union - case prbs_Status [15:00] */
/* RX0 :: Rx_Status :: prbs_lock [15:15] */
#define RX0_RX_STATUS_PRBS_STATUS_PRBS_LOCK_MASK                   0x8000
#define RX0_RX_STATUS_PRBS_STATUS_PRBS_LOCK_ALIGN                  0
#define RX0_RX_STATUS_PRBS_STATUS_PRBS_LOCK_BITS                   1
#define RX0_RX_STATUS_PRBS_STATUS_PRBS_LOCK_SHIFT                  15

/* RX0 :: Rx_Status :: prbs_stky [14:14] */
#define RX0_RX_STATUS_PRBS_STATUS_PRBS_STKY_MASK                   0x4000
#define RX0_RX_STATUS_PRBS_STATUS_PRBS_STKY_ALIGN                  0
#define RX0_RX_STATUS_PRBS_STATUS_PRBS_STKY_BITS                   1
#define RX0_RX_STATUS_PRBS_STATUS_PRBS_STKY_SHIFT                  14

/* RX0 :: Rx_Status :: ptbs_errors [13:00] */
#define RX0_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_MASK                 0x3fff
#define RX0_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_ALIGN                0
#define RX0_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_BITS                 14
#define RX0_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_SHIFT                0



/****************************************************************************
 * RX0 :: Rx_Control
 ***************************************************************************/
/* RX0 :: Rx_Control :: reserved0 [15:03] */
#define RX0_RX_CONTROL_RESERVED0_MASK                              0xfff8
#define RX0_RX_CONTROL_RESERVED0_ALIGN                             0
#define RX0_RX_CONTROL_RESERVED0_BITS                              13
#define RX0_RX_CONTROL_RESERVED0_SHIFT                             3

/* RX0 :: Rx_Control :: status_sel [02:00] */
#define RX0_RX_CONTROL_STATUS_SEL_MASK                             0x0007
#define RX0_RX_CONTROL_STATUS_SEL_ALIGN                            0
#define RX0_RX_CONTROL_STATUS_SEL_BITS                             3
#define RX0_RX_CONTROL_STATUS_SEL_SHIFT                            0
#define RX0_RX_CONTROL_STATUS_SEL_sigdetStatus                     0
#define RX0_RX_CONTROL_STATUS_SEL_syncStatus                       1
#define RX0_RX_CONTROL_STATUS_SEL_rxTestSel                        2
#define RX0_RX_CONTROL_STATUS_SEL_scaleStatus                      3
#define RX0_RX_CONTROL_STATUS_SEL_adcCdrStatus                     4
#define RX0_RX_CONTROL_STATUS_SEL_integStatus                      5
#define RX0_RX_CONTROL_STATUS_SEL_vcoStatus                        6
#define RX0_RX_CONTROL_STATUS_SEL_prbsStatus                       7


/****************************************************************************
 * RX0 :: Rx_Test
 ***************************************************************************/
/* RX0 :: Rx_Test :: sigdet_mux_SM [15:12] */
#define RX0_RX_TEST_SIGDET_MUX_SM_MASK                             0xf000
#define RX0_RX_TEST_SIGDET_MUX_SM_ALIGN                            0
#define RX0_RX_TEST_SIGDET_MUX_SM_BITS                             4
#define RX0_RX_TEST_SIGDET_MUX_SM_SHIFT                            12

/* RX0 :: Rx_Test :: reserved0 [11:09] */
#define RX0_RX_TEST_RESERVED0_MASK                                 0x0e00
#define RX0_RX_TEST_RESERVED0_ALIGN                                0
#define RX0_RX_TEST_RESERVED0_BITS                                 3
#define RX0_RX_TEST_RESERVED0_SHIFT                                9

/* RX0 :: Rx_Test :: tpctrl_SM [08:04] */
#define RX0_RX_TEST_TPCTRL_SM_MASK                                 0x01f0
#define RX0_RX_TEST_TPCTRL_SM_ALIGN                                0
#define RX0_RX_TEST_TPCTRL_SM_BITS                                 5
#define RX0_RX_TEST_TPCTRL_SM_SHIFT                                4

/* RX0 :: Rx_Test :: testMuxSelect_SM [03:00] */
#define RX0_RX_TEST_TESTMUXSELECT_SM_MASK                          0x000f
#define RX0_RX_TEST_TESTMUXSELECT_SM_ALIGN                         0
#define RX0_RX_TEST_TESTMUXSELECT_SM_BITS                          4
#define RX0_RX_TEST_TESTMUXSELECT_SM_SHIFT                         0


/****************************************************************************
 * RX0 :: Rx_Control_1G_type
 ***************************************************************************/
/* RX0 :: Rx_Control_1G_type :: fpat_md [15:15] */
#define RX0_RX_CONTROL_1G_TYPE_FPAT_MD_MASK                        0x8000
#define RX0_RX_CONTROL_1G_TYPE_FPAT_MD_ALIGN                       0
#define RX0_RX_CONTROL_1G_TYPE_FPAT_MD_BITS                        1
#define RX0_RX_CONTROL_1G_TYPE_FPAT_MD_SHIFT                       15

/* RX0 :: Rx_Control_1G_type :: pkt_count_en [14:14] */
#define RX0_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_MASK                   0x4000
#define RX0_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_ALIGN                  0
#define RX0_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_BITS                   1
#define RX0_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_SHIFT                  14

/* RX0 :: Rx_Control_1G_type :: staMuxRegDis [13:13] */
#define RX0_RX_CONTROL_1G_TYPE_STAMUXREGDIS_MASK                   0x2000
#define RX0_RX_CONTROL_1G_TYPE_STAMUXREGDIS_ALIGN                  0
#define RX0_RX_CONTROL_1G_TYPE_STAMUXREGDIS_BITS                   1
#define RX0_RX_CONTROL_1G_TYPE_STAMUXREGDIS_SHIFT                  13

/* RX0 :: Rx_Control_1G_type :: prbs_clr_dis [12:12] */
#define RX0_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_MASK                   0x1000
#define RX0_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_ALIGN                  0
#define RX0_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_BITS                   1
#define RX0_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_SHIFT                  12

/* RX0 :: Rx_Control_1G_type :: rxd_dec_sel [11:11] */
#define RX0_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_MASK                    0x0800
#define RX0_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_ALIGN                   0
#define RX0_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_BITS                    1
#define RX0_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_SHIFT                   11

/* RX0 :: Rx_Control_1G_type :: cgbad_tst [10:10] */
#define RX0_RX_CONTROL_1G_TYPE_CGBAD_TST_MASK                      0x0400
#define RX0_RX_CONTROL_1G_TYPE_CGBAD_TST_ALIGN                     0
#define RX0_RX_CONTROL_1G_TYPE_CGBAD_TST_BITS                      1
#define RX0_RX_CONTROL_1G_TYPE_CGBAD_TST_SHIFT                     10

/* RX0 :: Rx_Control_1G_type :: Emon_en [09:09] */
#define RX0_RX_CONTROL_1G_TYPE_EMON_EN_MASK                        0x0200
#define RX0_RX_CONTROL_1G_TYPE_EMON_EN_ALIGN                       0
#define RX0_RX_CONTROL_1G_TYPE_EMON_EN_BITS                        1
#define RX0_RX_CONTROL_1G_TYPE_EMON_EN_SHIFT                       9

/* RX0 :: Rx_Control_1G_type :: prbs_en [08:08] */
#define RX0_RX_CONTROL_1G_TYPE_PRBS_EN_MASK                        0x0100
#define RX0_RX_CONTROL_1G_TYPE_PRBS_EN_ALIGN                       0
#define RX0_RX_CONTROL_1G_TYPE_PRBS_EN_BITS                        1
#define RX0_RX_CONTROL_1G_TYPE_PRBS_EN_SHIFT                       8

/* RX0 :: Rx_Control_1G_type :: cgbad_en [07:07] */
#define RX0_RX_CONTROL_1G_TYPE_CGBAD_EN_MASK                       0x0080
#define RX0_RX_CONTROL_1G_TYPE_CGBAD_EN_ALIGN                      0
#define RX0_RX_CONTROL_1G_TYPE_CGBAD_EN_BITS                       1
#define RX0_RX_CONTROL_1G_TYPE_CGBAD_EN_SHIFT                      7

/* RX0 :: Rx_Control_1G_type :: cstretch [06:06] */
#define RX0_RX_CONTROL_1G_TYPE_CSTRETCH_MASK                       0x0040
#define RX0_RX_CONTROL_1G_TYPE_CSTRETCH_ALIGN                      0
#define RX0_RX_CONTROL_1G_TYPE_CSTRETCH_BITS                       1
#define RX0_RX_CONTROL_1G_TYPE_CSTRETCH_SHIFT                      6

/* RX0 :: Rx_Control_1G_type :: rtbi_ckflip [05:05] */
#define RX0_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_MASK                    0x0020
#define RX0_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_ALIGN                   0
#define RX0_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_BITS                    1
#define RX0_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_SHIFT                   5

/* RX0 :: Rx_Control_1G_type :: rtbi_flip [04:04] */
#define RX0_RX_CONTROL_1G_TYPE_RTBI_FLIP_MASK                      0x0010
#define RX0_RX_CONTROL_1G_TYPE_RTBI_FLIP_ALIGN                     0
#define RX0_RX_CONTROL_1G_TYPE_RTBI_FLIP_BITS                      1
#define RX0_RX_CONTROL_1G_TYPE_RTBI_FLIP_SHIFT                     4

/* RX0 :: Rx_Control_1G_type :: phase_sel [03:03] */
#define RX0_RX_CONTROL_1G_TYPE_PHASE_SEL_MASK                      0x0008
#define RX0_RX_CONTROL_1G_TYPE_PHASE_SEL_ALIGN                     0
#define RX0_RX_CONTROL_1G_TYPE_PHASE_SEL_BITS                      1
#define RX0_RX_CONTROL_1G_TYPE_PHASE_SEL_SHIFT                     3

/* RX0 :: Rx_Control_1G_type :: reserved0 [02:02] */
#define RX0_RX_CONTROL_1G_TYPE_RESERVED0_MASK                      0x0004
#define RX0_RX_CONTROL_1G_TYPE_RESERVED0_ALIGN                     0
#define RX0_RX_CONTROL_1G_TYPE_RESERVED0_BITS                      1
#define RX0_RX_CONTROL_1G_TYPE_RESERVED0_SHIFT                     2

/* RX0 :: Rx_Control_1G_type :: freq_sel_force [01:01] */
#define RX0_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_MASK                 0x0002
#define RX0_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_ALIGN                0
#define RX0_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_BITS                 1
#define RX0_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_SHIFT                1

/* RX0 :: Rx_Control_1G_type :: freq_sel [00:00] */
#define RX0_RX_CONTROL_1G_TYPE_FREQ_SEL_MASK                       0x0001
#define RX0_RX_CONTROL_1G_TYPE_FREQ_SEL_ALIGN                      0
#define RX0_RX_CONTROL_1G_TYPE_FREQ_SEL_BITS                       1
#define RX0_RX_CONTROL_1G_TYPE_FREQ_SEL_SHIFT                      0


/****************************************************************************
 * RX0 :: Rx_Astatus
 ***************************************************************************/
/* RX0 :: Rx_Astatus :: reserved0 [15:01] */
#define RX0_RX_ASTATUS_RESERVED0_MASK                              0xfffe
#define RX0_RX_ASTATUS_RESERVED0_ALIGN                             0
#define RX0_RX_ASTATUS_RESERVED0_BITS                              15
#define RX0_RX_ASTATUS_RESERVED0_SHIFT                             1

/* RX0 :: Rx_Astatus :: sigdet [00:00] */
#define RX0_RX_ASTATUS_SIGDET_MASK                                 0x0001
#define RX0_RX_ASTATUS_SIGDET_ALIGN                                0
#define RX0_RX_ASTATUS_SIGDET_BITS                                 1
#define RX0_RX_ASTATUS_SIGDET_SHIFT                                0


/****************************************************************************
 * RX0 :: Rx_analogBias0
 ***************************************************************************/
/* RX0 :: Rx_analogBias0 :: imode_vcm [15:15] */
#define RX0_RX_ANALOGBIAS0_IMODE_VCM_MASK                          0x8000
#define RX0_RX_ANALOGBIAS0_IMODE_VCM_ALIGN                         0
#define RX0_RX_ANALOGBIAS0_IMODE_VCM_BITS                          1
#define RX0_RX_ANALOGBIAS0_IMODE_VCM_SHIFT                         15

/* RX0 :: Rx_analogBias0 :: imin_vcm [14:14] */
#define RX0_RX_ANALOGBIAS0_IMIN_VCM_MASK                           0x4000
#define RX0_RX_ANALOGBIAS0_IMIN_VCM_ALIGN                          0
#define RX0_RX_ANALOGBIAS0_IMIN_VCM_BITS                           1
#define RX0_RX_ANALOGBIAS0_IMIN_VCM_SHIFT                          14

/* RX0 :: Rx_analogBias0 :: imax_sigdet [13:13] */
#define RX0_RX_ANALOGBIAS0_IMAX_SIGDET_MASK                        0x2000
#define RX0_RX_ANALOGBIAS0_IMAX_SIGDET_ALIGN                       0
#define RX0_RX_ANALOGBIAS0_IMAX_SIGDET_BITS                        1
#define RX0_RX_ANALOGBIAS0_IMAX_SIGDET_SHIFT                       13

/* RX0 :: Rx_analogBias0 :: imode_sigdet [12:12] */
#define RX0_RX_ANALOGBIAS0_IMODE_SIGDET_MASK                       0x1000
#define RX0_RX_ANALOGBIAS0_IMODE_SIGDET_ALIGN                      0
#define RX0_RX_ANALOGBIAS0_IMODE_SIGDET_BITS                       1
#define RX0_RX_ANALOGBIAS0_IMODE_SIGDET_SHIFT                      12

/* RX0 :: Rx_analogBias0 :: imin_sigdet [11:11] */
#define RX0_RX_ANALOGBIAS0_IMIN_SIGDET_MASK                        0x0800
#define RX0_RX_ANALOGBIAS0_IMIN_SIGDET_ALIGN                       0
#define RX0_RX_ANALOGBIAS0_IMIN_SIGDET_BITS                        1
#define RX0_RX_ANALOGBIAS0_IMIN_SIGDET_SHIFT                       11

/* RX0 :: Rx_analogBias0 :: refh_rx [10:10] */
#define RX0_RX_ANALOGBIAS0_REFH_RX_MASK                            0x0400
#define RX0_RX_ANALOGBIAS0_REFH_RX_ALIGN                           0
#define RX0_RX_ANALOGBIAS0_REFH_RX_BITS                            1
#define RX0_RX_ANALOGBIAS0_REFH_RX_SHIFT                           10

/* RX0 :: Rx_analogBias0 :: refl_rx [09:09] */
#define RX0_RX_ANALOGBIAS0_REFL_RX_MASK                            0x0200
#define RX0_RX_ANALOGBIAS0_REFL_RX_ALIGN                           0
#define RX0_RX_ANALOGBIAS0_REFL_RX_BITS                            1
#define RX0_RX_ANALOGBIAS0_REFL_RX_SHIFT                           9

/* RX0 :: Rx_analogBias0 :: tport_en [08:08] */
#define RX0_RX_ANALOGBIAS0_TPORT_EN_MASK                           0x0100
#define RX0_RX_ANALOGBIAS0_TPORT_EN_ALIGN                          0
#define RX0_RX_ANALOGBIAS0_TPORT_EN_BITS                           1
#define RX0_RX_ANALOGBIAS0_TPORT_EN_SHIFT                          8

/* RX0 :: Rx_analogBias0 :: vddr_bg [07:07] */
#define RX0_RX_ANALOGBIAS0_VDDR_BG_MASK                            0x0080
#define RX0_RX_ANALOGBIAS0_VDDR_BG_ALIGN                           0
#define RX0_RX_ANALOGBIAS0_VDDR_BG_BITS                            1
#define RX0_RX_ANALOGBIAS0_VDDR_BG_SHIFT                           7

/* RX0 :: Rx_analogBias0 :: sig_pwrdn [06:06] */
#define RX0_RX_ANALOGBIAS0_SIG_PWRDN_MASK                          0x0040
#define RX0_RX_ANALOGBIAS0_SIG_PWRDN_ALIGN                         0
#define RX0_RX_ANALOGBIAS0_SIG_PWRDN_BITS                          1
#define RX0_RX_ANALOGBIAS0_SIG_PWRDN_SHIFT                         6

/* RX0 :: Rx_analogBias0 :: offset_ctrl [05:03] */
#define RX0_RX_ANALOGBIAS0_OFFSET_CTRL_MASK                        0x0038
#define RX0_RX_ANALOGBIAS0_OFFSET_CTRL_ALIGN                       0
#define RX0_RX_ANALOGBIAS0_OFFSET_CTRL_BITS                        3
#define RX0_RX_ANALOGBIAS0_OFFSET_CTRL_SHIFT                       3

/* RX0 :: Rx_analogBias0 :: offset_sel [02:02] */
#define RX0_RX_ANALOGBIAS0_OFFSET_SEL_MASK                         0x0004
#define RX0_RX_ANALOGBIAS0_OFFSET_SEL_ALIGN                        0
#define RX0_RX_ANALOGBIAS0_OFFSET_SEL_BITS                         1
#define RX0_RX_ANALOGBIAS0_OFFSET_SEL_SHIFT                        2

/* RX0 :: Rx_analogBias0 :: reserved0 [01:00] */
#define RX0_RX_ANALOGBIAS0_RESERVED0_MASK                          0x0003
#define RX0_RX_ANALOGBIAS0_RESERVED0_ALIGN                         0
#define RX0_RX_ANALOGBIAS0_RESERVED0_BITS                          2
#define RX0_RX_ANALOGBIAS0_RESERVED0_SHIFT                         0


/****************************************************************************
 * RX0 :: Rx_analogBias1
 ***************************************************************************/
/* RX0 :: Rx_analogBias1 :: imax_clkbuf [15:15] */
#define RX0_RX_ANALOGBIAS1_IMAX_CLKBUF_MASK                        0x8000
#define RX0_RX_ANALOGBIAS1_IMAX_CLKBUF_ALIGN                       0
#define RX0_RX_ANALOGBIAS1_IMAX_CLKBUF_BITS                        1
#define RX0_RX_ANALOGBIAS1_IMAX_CLKBUF_SHIFT                       15

/* RX0 :: Rx_analogBias1 :: imode_clkbuf [14:14] */
#define RX0_RX_ANALOGBIAS1_IMODE_CLKBUF_MASK                       0x4000
#define RX0_RX_ANALOGBIAS1_IMODE_CLKBUF_ALIGN                      0
#define RX0_RX_ANALOGBIAS1_IMODE_CLKBUF_BITS                       1
#define RX0_RX_ANALOGBIAS1_IMODE_CLKBUF_SHIFT                      14

/* RX0 :: Rx_analogBias1 :: imin_clkbuf [13:13] */
#define RX0_RX_ANALOGBIAS1_IMIN_CLKBUF_MASK                        0x2000
#define RX0_RX_ANALOGBIAS1_IMIN_CLKBUF_ALIGN                       0
#define RX0_RX_ANALOGBIAS1_IMIN_CLKBUF_BITS                        1
#define RX0_RX_ANALOGBIAS1_IMIN_CLKBUF_SHIFT                       13

/* RX0 :: Rx_analogBias1 :: imax_eqfl [12:12] */
#define RX0_RX_ANALOGBIAS1_IMAX_EQFL_MASK                          0x1000
#define RX0_RX_ANALOGBIAS1_IMAX_EQFL_ALIGN                         0
#define RX0_RX_ANALOGBIAS1_IMAX_EQFL_BITS                          1
#define RX0_RX_ANALOGBIAS1_IMAX_EQFL_SHIFT                         12

/* RX0 :: Rx_analogBias1 :: imode_eqfl [11:11] */
#define RX0_RX_ANALOGBIAS1_IMODE_EQFL_MASK                         0x0800
#define RX0_RX_ANALOGBIAS1_IMODE_EQFL_ALIGN                        0
#define RX0_RX_ANALOGBIAS1_IMODE_EQFL_BITS                         1
#define RX0_RX_ANALOGBIAS1_IMODE_EQFL_SHIFT                        11

/* RX0 :: Rx_analogBias1 :: imin_eqfl [10:10] */
#define RX0_RX_ANALOGBIAS1_IMIN_EQFL_MASK                          0x0400
#define RX0_RX_ANALOGBIAS1_IMIN_EQFL_ALIGN                         0
#define RX0_RX_ANALOGBIAS1_IMIN_EQFL_BITS                          1
#define RX0_RX_ANALOGBIAS1_IMIN_EQFL_SHIFT                         10

/* RX0 :: Rx_analogBias1 :: imax_dfesum [09:09] */
#define RX0_RX_ANALOGBIAS1_IMAX_DFESUM_MASK                        0x0200
#define RX0_RX_ANALOGBIAS1_IMAX_DFESUM_ALIGN                       0
#define RX0_RX_ANALOGBIAS1_IMAX_DFESUM_BITS                        1
#define RX0_RX_ANALOGBIAS1_IMAX_DFESUM_SHIFT                       9

/* RX0 :: Rx_analogBias1 :: imode_dfesum [08:08] */
#define RX0_RX_ANALOGBIAS1_IMODE_DFESUM_MASK                       0x0100
#define RX0_RX_ANALOGBIAS1_IMODE_DFESUM_ALIGN                      0
#define RX0_RX_ANALOGBIAS1_IMODE_DFESUM_BITS                       1
#define RX0_RX_ANALOGBIAS1_IMODE_DFESUM_SHIFT                      8

/* RX0 :: Rx_analogBias1 :: imin_dfesum [07:07] */
#define RX0_RX_ANALOGBIAS1_IMIN_DFESUM_MASK                        0x0080
#define RX0_RX_ANALOGBIAS1_IMIN_DFESUM_ALIGN                       0
#define RX0_RX_ANALOGBIAS1_IMIN_DFESUM_BITS                        1
#define RX0_RX_ANALOGBIAS1_IMIN_DFESUM_SHIFT                       7

/* RX0 :: Rx_analogBias1 :: imax_vga [06:06] */
#define RX0_RX_ANALOGBIAS1_IMAX_VGA_MASK                           0x0040
#define RX0_RX_ANALOGBIAS1_IMAX_VGA_ALIGN                          0
#define RX0_RX_ANALOGBIAS1_IMAX_VGA_BITS                           1
#define RX0_RX_ANALOGBIAS1_IMAX_VGA_SHIFT                          6

/* RX0 :: Rx_analogBias1 :: imode_vga [05:05] */
#define RX0_RX_ANALOGBIAS1_IMODE_VGA_MASK                          0x0020
#define RX0_RX_ANALOGBIAS1_IMODE_VGA_ALIGN                         0
#define RX0_RX_ANALOGBIAS1_IMODE_VGA_BITS                          1
#define RX0_RX_ANALOGBIAS1_IMODE_VGA_SHIFT                         5

/* RX0 :: Rx_analogBias1 :: imin_vga [04:04] */
#define RX0_RX_ANALOGBIAS1_IMIN_VGA_MASK                           0x0010
#define RX0_RX_ANALOGBIAS1_IMIN_VGA_ALIGN                          0
#define RX0_RX_ANALOGBIAS1_IMIN_VGA_BITS                           1
#define RX0_RX_ANALOGBIAS1_IMIN_VGA_SHIFT                          4

/* RX0 :: Rx_analogBias1 :: imax_interp [03:03] */
#define RX0_RX_ANALOGBIAS1_IMAX_INTERP_MASK                        0x0008
#define RX0_RX_ANALOGBIAS1_IMAX_INTERP_ALIGN                       0
#define RX0_RX_ANALOGBIAS1_IMAX_INTERP_BITS                        1
#define RX0_RX_ANALOGBIAS1_IMAX_INTERP_SHIFT                       3

/* RX0 :: Rx_analogBias1 :: imode_interp [02:02] */
#define RX0_RX_ANALOGBIAS1_IMODE_INTERP_MASK                       0x0004
#define RX0_RX_ANALOGBIAS1_IMODE_INTERP_ALIGN                      0
#define RX0_RX_ANALOGBIAS1_IMODE_INTERP_BITS                       1
#define RX0_RX_ANALOGBIAS1_IMODE_INTERP_SHIFT                      2

/* RX0 :: Rx_analogBias1 :: imin_interp [01:01] */
#define RX0_RX_ANALOGBIAS1_IMIN_INTERP_MASK                        0x0002
#define RX0_RX_ANALOGBIAS1_IMIN_INTERP_ALIGN                       0
#define RX0_RX_ANALOGBIAS1_IMIN_INTERP_BITS                        1
#define RX0_RX_ANALOGBIAS1_IMIN_INTERP_SHIFT                       1

/* RX0 :: Rx_analogBias1 :: imax_vcm [00:00] */
#define RX0_RX_ANALOGBIAS1_IMAX_VCM_MASK                           0x0001
#define RX0_RX_ANALOGBIAS1_IMAX_VCM_ALIGN                          0
#define RX0_RX_ANALOGBIAS1_IMAX_VCM_BITS                           1
#define RX0_RX_ANALOGBIAS1_IMAX_VCM_SHIFT                          0


/****************************************************************************
 * RX0 :: Rx_analogBias2
 ***************************************************************************/
/* RX0 :: Rx_analogBias2 :: en_clk16 [15:15] */
#define RX0_RX_ANALOGBIAS2_EN_CLK16_MASK                           0x8000
#define RX0_RX_ANALOGBIAS2_EN_CLK16_ALIGN                          0
#define RX0_RX_ANALOGBIAS2_EN_CLK16_BITS                           1
#define RX0_RX_ANALOGBIAS2_EN_CLK16_SHIFT                          15

/* RX0 :: Rx_analogBias2 :: pd_ch_p1 [14:14] */
#define RX0_RX_ANALOGBIAS2_PD_CH_P1_MASK                           0x4000
#define RX0_RX_ANALOGBIAS2_PD_CH_P1_ALIGN                          0
#define RX0_RX_ANALOGBIAS2_PD_CH_P1_BITS                           1
#define RX0_RX_ANALOGBIAS2_PD_CH_P1_SHIFT                          14

/* RX0 :: Rx_analogBias2 :: en_vcctrl [13:13] */
#define RX0_RX_ANALOGBIAS2_EN_VCCTRL_MASK                          0x2000
#define RX0_RX_ANALOGBIAS2_EN_VCCTRL_ALIGN                         0
#define RX0_RX_ANALOGBIAS2_EN_VCCTRL_BITS                          1
#define RX0_RX_ANALOGBIAS2_EN_VCCTRL_SHIFT                         13

/* RX0 :: Rx_analogBias2 :: en_dfeclk [12:12] */
#define RX0_RX_ANALOGBIAS2_EN_DFECLK_MASK                          0x1000
#define RX0_RX_ANALOGBIAS2_EN_DFECLK_ALIGN                         0
#define RX0_RX_ANALOGBIAS2_EN_DFECLK_BITS                          1
#define RX0_RX_ANALOGBIAS2_EN_DFECLK_SHIFT                         12

/* RX0 :: Rx_analogBias2 :: en_hgain [11:11] */
#define RX0_RX_ANALOGBIAS2_EN_HGAIN_MASK                           0x0800
#define RX0_RX_ANALOGBIAS2_EN_HGAIN_ALIGN                          0
#define RX0_RX_ANALOGBIAS2_EN_HGAIN_BITS                           1
#define RX0_RX_ANALOGBIAS2_EN_HGAIN_SHIFT                          11

/* RX0 :: Rx_analogBias2 :: en_dfeckpwr [10:10] */
#define RX0_RX_ANALOGBIAS2_EN_DFECKPWR_MASK                        0x0400
#define RX0_RX_ANALOGBIAS2_EN_DFECKPWR_ALIGN                       0
#define RX0_RX_ANALOGBIAS2_EN_DFECKPWR_BITS                        1
#define RX0_RX_ANALOGBIAS2_EN_DFECKPWR_SHIFT                       10

/* RX0 :: Rx_analogBias2 :: offset_pd [09:09] */
#define RX0_RX_ANALOGBIAS2_OFFSET_PD_MASK                          0x0200
#define RX0_RX_ANALOGBIAS2_OFFSET_PD_ALIGN                         0
#define RX0_RX_ANALOGBIAS2_OFFSET_PD_BITS                          1
#define RX0_RX_ANALOGBIAS2_OFFSET_PD_SHIFT                         9

/* RX0 :: Rx_analogBias2 :: imax_dfetap [08:08] */
#define RX0_RX_ANALOGBIAS2_IMAX_DFETAP_MASK                        0x0100
#define RX0_RX_ANALOGBIAS2_IMAX_DFETAP_ALIGN                       0
#define RX0_RX_ANALOGBIAS2_IMAX_DFETAP_BITS                        1
#define RX0_RX_ANALOGBIAS2_IMAX_DFETAP_SHIFT                       8

/* RX0 :: Rx_analogBias2 :: imode_dfetap [07:07] */
#define RX0_RX_ANALOGBIAS2_IMODE_DFETAP_MASK                       0x0080
#define RX0_RX_ANALOGBIAS2_IMODE_DFETAP_ALIGN                      0
#define RX0_RX_ANALOGBIAS2_IMODE_DFETAP_BITS                       1
#define RX0_RX_ANALOGBIAS2_IMODE_DFETAP_SHIFT                      7

/* RX0 :: Rx_analogBias2 :: imin_dfetap [06:06] */
#define RX0_RX_ANALOGBIAS2_IMIN_DFETAP_MASK                        0x0040
#define RX0_RX_ANALOGBIAS2_IMIN_DFETAP_ALIGN                       0
#define RX0_RX_ANALOGBIAS2_IMIN_DFETAP_BITS                        1
#define RX0_RX_ANALOGBIAS2_IMIN_DFETAP_SHIFT                       6

/* RX0 :: Rx_analogBias2 :: imax_slcd2c [05:05] */
#define RX0_RX_ANALOGBIAS2_IMAX_SLCD2C_MASK                        0x0020
#define RX0_RX_ANALOGBIAS2_IMAX_SLCD2C_ALIGN                       0
#define RX0_RX_ANALOGBIAS2_IMAX_SLCD2C_BITS                        1
#define RX0_RX_ANALOGBIAS2_IMAX_SLCD2C_SHIFT                       5

/* RX0 :: Rx_analogBias2 :: imode_slcd2c [04:04] */
#define RX0_RX_ANALOGBIAS2_IMODE_SLCD2C_MASK                       0x0010
#define RX0_RX_ANALOGBIAS2_IMODE_SLCD2C_ALIGN                      0
#define RX0_RX_ANALOGBIAS2_IMODE_SLCD2C_BITS                       1
#define RX0_RX_ANALOGBIAS2_IMODE_SLCD2C_SHIFT                      4

/* RX0 :: Rx_analogBias2 :: imin_slcd2c [03:03] */
#define RX0_RX_ANALOGBIAS2_IMIN_SLCD2C_MASK                        0x0008
#define RX0_RX_ANALOGBIAS2_IMIN_SLCD2C_ALIGN                       0
#define RX0_RX_ANALOGBIAS2_IMIN_SLCD2C_BITS                        1
#define RX0_RX_ANALOGBIAS2_IMIN_SLCD2C_SHIFT                       3

/* RX0 :: Rx_analogBias2 :: imax_dfevref [02:02] */
#define RX0_RX_ANALOGBIAS2_IMAX_DFEVREF_MASK                       0x0004
#define RX0_RX_ANALOGBIAS2_IMAX_DFEVREF_ALIGN                      0
#define RX0_RX_ANALOGBIAS2_IMAX_DFEVREF_BITS                       1
#define RX0_RX_ANALOGBIAS2_IMAX_DFEVREF_SHIFT                      2

/* RX0 :: Rx_analogBias2 :: imode_dfevref [01:01] */
#define RX0_RX_ANALOGBIAS2_IMODE_DFEVREF_MASK                      0x0002
#define RX0_RX_ANALOGBIAS2_IMODE_DFEVREF_ALIGN                     0
#define RX0_RX_ANALOGBIAS2_IMODE_DFEVREF_BITS                      1
#define RX0_RX_ANALOGBIAS2_IMODE_DFEVREF_SHIFT                     1

/* RX0 :: Rx_analogBias2 :: imin_dfevref [00:00] */
#define RX0_RX_ANALOGBIAS2_IMIN_DFEVREF_MASK                       0x0001
#define RX0_RX_ANALOGBIAS2_IMIN_DFEVREF_ALIGN                      0
#define RX0_RX_ANALOGBIAS2_IMIN_DFEVREF_BITS                       1
#define RX0_RX_ANALOGBIAS2_IMIN_DFEVREF_SHIFT                      0


/****************************************************************************
 * XGXS16G_USER_RX1
 ***************************************************************************/
/****************************************************************************
 * RX1 :: Rx_Status
 ***************************************************************************/
/* union - case sigdet_Status [15:00] */
/* RX1 :: Rx_Status :: cx4_sigdet [15:15] */
#define RX1_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_MASK                0x8000
#define RX1_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_ALIGN               0
#define RX1_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_BITS                1
#define RX1_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_SHIFT               15

/* RX1 :: Rx_Status :: reserved0 [14:13] */
#define RX1_RX_STATUS_SIGDET_STATUS_RESERVED0_MASK                 0x6000
#define RX1_RX_STATUS_SIGDET_STATUS_RESERVED0_ALIGN                0
#define RX1_RX_STATUS_SIGDET_STATUS_RESERVED0_BITS                 2
#define RX1_RX_STATUS_SIGDET_STATUS_RESERVED0_SHIFT                13

/* RX1 :: Rx_Status :: rxSeqDone [12:12] */
#define RX1_RX_STATUS_SIGDET_STATUS_RXSEQDONE_MASK                 0x1000
#define RX1_RX_STATUS_SIGDET_STATUS_RXSEQDONE_ALIGN                0
#define RX1_RX_STATUS_SIGDET_STATUS_RXSEQDONE_BITS                 1
#define RX1_RX_STATUS_SIGDET_STATUS_RXSEQDONE_SHIFT                12

/* RX1 :: Rx_Status :: rx_sigdet_ll [11:11] */
#define RX1_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_MASK              0x0800
#define RX1_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_ALIGN             0
#define RX1_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_BITS              1
#define RX1_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_SHIFT             11

/* RX1 :: Rx_Status :: cs4_sigdet_ll [10:10] */
#define RX1_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_MASK             0x0400
#define RX1_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_ALIGN            0
#define RX1_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_BITS             1
#define RX1_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_SHIFT            10

/* RX1 :: Rx_Status :: rx_reset [09:09] */
#define RX1_RX_STATUS_SIGDET_STATUS_RX_RESET_MASK                  0x0200
#define RX1_RX_STATUS_SIGDET_STATUS_RX_RESET_ALIGN                 0
#define RX1_RX_STATUS_SIGDET_STATUS_RX_RESET_BITS                  1
#define RX1_RX_STATUS_SIGDET_STATUS_RX_RESET_SHIFT                 9

/* RX1 :: Rx_Status :: rx_pwrdn [08:08] */
#define RX1_RX_STATUS_SIGDET_STATUS_RX_PWRDN_MASK                  0x0100
#define RX1_RX_STATUS_SIGDET_STATUS_RX_PWRDN_ALIGN                 0
#define RX1_RX_STATUS_SIGDET_STATUS_RX_PWRDN_BITS                  1
#define RX1_RX_STATUS_SIGDET_STATUS_RX_PWRDN_SHIFT                 8

/* RX1 :: Rx_Status :: reserved1 [07:00] */
#define RX1_RX_STATUS_SIGDET_STATUS_RESERVED1_MASK                 0x00ff
#define RX1_RX_STATUS_SIGDET_STATUS_RESERVED1_ALIGN                0
#define RX1_RX_STATUS_SIGDET_STATUS_RESERVED1_BITS                 8
#define RX1_RX_STATUS_SIGDET_STATUS_RESERVED1_SHIFT                0


/* union - case sync_Status [15:00] */
/* RX1 :: Rx_Status :: reserved0 [15:11] */
#define RX1_RX_STATUS_SYNC_STATUS_RESERVED0_MASK                   0xf800
#define RX1_RX_STATUS_SYNC_STATUS_RESERVED0_ALIGN                  0
#define RX1_RX_STATUS_SYNC_STATUS_RESERVED0_BITS                   5
#define RX1_RX_STATUS_SYNC_STATUS_RESERVED0_SHIFT                  11

/* RX1 :: Rx_Status :: test_acq_en [10:10] */
#define RX1_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_MASK                 0x0400
#define RX1_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_ALIGN                0
#define RX1_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_BITS                 1
#define RX1_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_SHIFT                10

/* RX1 :: Rx_Status :: reserved1 [09:09] */
#define RX1_RX_STATUS_SYNC_STATUS_RESERVED1_MASK                   0x0200
#define RX1_RX_STATUS_SYNC_STATUS_RESERVED1_ALIGN                  0
#define RX1_RX_STATUS_SYNC_STATUS_RESERVED1_BITS                   1
#define RX1_RX_STATUS_SYNC_STATUS_RESERVED1_SHIFT                  9

/* RX1 :: Rx_Status :: rxSeqStart [08:08] */
#define RX1_RX_STATUS_SYNC_STATUS_RXSEQSTART_MASK                  0x0100
#define RX1_RX_STATUS_SYNC_STATUS_RXSEQSTART_ALIGN                 0
#define RX1_RX_STATUS_SYNC_STATUS_RXSEQSTART_BITS                  1
#define RX1_RX_STATUS_SYNC_STATUS_RXSEQSTART_SHIFT                 8

/* RX1 :: Rx_Status :: mux_comadj_sync_status [07:07] */
#define RX1_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_MASK      0x0080
#define RX1_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_ALIGN     0
#define RX1_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_BITS      1
#define RX1_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_SHIFT     7

/* RX1 :: Rx_Status :: sync_status [06:06] */
#define RX1_RX_STATUS_SYNC_STATUS_SYNC_STATUS_MASK                 0x0040
#define RX1_RX_STATUS_SYNC_STATUS_SYNC_STATUS_ALIGN                0
#define RX1_RX_STATUS_SYNC_STATUS_SYNC_STATUS_BITS                 1
#define RX1_RX_STATUS_SYNC_STATUS_SYNC_STATUS_SHIFT                6

/* RX1 :: Rx_Status :: rx_sigdet [05:05] */
#define RX1_RX_STATUS_SYNC_STATUS_RX_SIGDET_MASK                   0x0020
#define RX1_RX_STATUS_SYNC_STATUS_RX_SIGDET_ALIGN                  0
#define RX1_RX_STATUS_SYNC_STATUS_RX_SIGDET_BITS                   1
#define RX1_RX_STATUS_SYNC_STATUS_RX_SIGDET_SHIFT                  5

/* RX1 :: Rx_Status :: reserved2 [04:03] */
#define RX1_RX_STATUS_SYNC_STATUS_RESERVED2_MASK                   0x0018
#define RX1_RX_STATUS_SYNC_STATUS_RESERVED2_ALIGN                  0
#define RX1_RX_STATUS_SYNC_STATUS_RESERVED2_BITS                   2
#define RX1_RX_STATUS_SYNC_STATUS_RESERVED2_SHIFT                  3

/* RX1 :: Rx_Status :: saturate_status [02:02] */
#define RX1_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_MASK             0x0004
#define RX1_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_ALIGN            0
#define RX1_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_BITS             1
#define RX1_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_SHIFT            2

/* RX1 :: Rx_Status :: cx4_sigdet [01:01] */
#define RX1_RX_STATUS_SYNC_STATUS_CX4_SIGDET_MASK                  0x0002
#define RX1_RX_STATUS_SYNC_STATUS_CX4_SIGDET_ALIGN                 0
#define RX1_RX_STATUS_SYNC_STATUS_CX4_SIGDET_BITS                  1
#define RX1_RX_STATUS_SYNC_STATUS_CX4_SIGDET_SHIFT                 1

/* RX1 :: Rx_Status :: rxSeqDone [00:00] */
#define RX1_RX_STATUS_SYNC_STATUS_RXSEQDONE_MASK                   0x0001
#define RX1_RX_STATUS_SYNC_STATUS_RXSEQDONE_ALIGN                  0
#define RX1_RX_STATUS_SYNC_STATUS_RXSEQDONE_BITS                   1
#define RX1_RX_STATUS_SYNC_STATUS_RXSEQDONE_SHIFT                  0


/* union - case rxTestSel_0 [15:00] */
/* RX1 :: Rx_Status :: reserved0 [15:10] */
#define RX1_RX_STATUS_RXTESTSEL_0_RESERVED0_MASK                   0xfc00
#define RX1_RX_STATUS_RXTESTSEL_0_RESERVED0_ALIGN                  0
#define RX1_RX_STATUS_RXTESTSEL_0_RESERVED0_BITS                   6
#define RX1_RX_STATUS_RXTESTSEL_0_RESERVED0_SHIFT                  10

/* RX1 :: Rx_Status :: indck_mode_en [09:09] */
#define RX1_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_MASK               0x0200
#define RX1_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_ALIGN              0
#define RX1_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_BITS               1
#define RX1_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_SHIFT              9

/* RX1 :: Rx_Status :: pci_mode_en [08:08] */
#define RX1_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_MASK                 0x0100
#define RX1_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_ALIGN                0
#define RX1_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_BITS                 1
#define RX1_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_SHIFT                8

/* RX1 :: Rx_Status :: rx_polarity [07:07] */
#define RX1_RX_STATUS_RXTESTSEL_0_RX_POLARITY_MASK                 0x0080
#define RX1_RX_STATUS_RXTESTSEL_0_RX_POLARITY_ALIGN                0
#define RX1_RX_STATUS_RXTESTSEL_0_RX_POLARITY_BITS                 1
#define RX1_RX_STATUS_RXTESTSEL_0_RX_POLARITY_SHIFT                7

/* RX1 :: Rx_Status :: rxpol_flip [06:06] */
#define RX1_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_MASK                  0x0040
#define RX1_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_ALIGN                 0
#define RX1_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_BITS                  1
#define RX1_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_SHIFT                 6

/* RX1 :: Rx_Status :: comma_mask [05:05] */
#define RX1_RX_STATUS_RXTESTSEL_0_COMMA_MASK_MASK                  0x0020
#define RX1_RX_STATUS_RXTESTSEL_0_COMMA_MASK_ALIGN                 0
#define RX1_RX_STATUS_RXTESTSEL_0_COMMA_MASK_BITS                  1
#define RX1_RX_STATUS_RXTESTSEL_0_COMMA_MASK_SHIFT                 5

/* RX1 :: Rx_Status :: link_en_r [04:04] */
#define RX1_RX_STATUS_RXTESTSEL_0_LINK_EN_R_MASK                   0x0010
#define RX1_RX_STATUS_RXTESTSEL_0_LINK_EN_R_ALIGN                  0
#define RX1_RX_STATUS_RXTESTSEL_0_LINK_EN_R_BITS                   1
#define RX1_RX_STATUS_RXTESTSEL_0_LINK_EN_R_SHIFT                  4

/* RX1 :: Rx_Status :: comma_adj_en [03:03] */
#define RX1_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_MASK                0x0008
#define RX1_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_ALIGN               0
#define RX1_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_BITS                1
#define RX1_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_SHIFT               3

/* RX1 :: Rx_Status :: comma_adj_en_ext [02:02] */
#define RX1_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_MASK            0x0004
#define RX1_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_ALIGN           0
#define RX1_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_BITS            1
#define RX1_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_SHIFT           2

/* RX1 :: Rx_Status :: reserved1 [01:00] */
#define RX1_RX_STATUS_RXTESTSEL_0_RESERVED1_MASK                   0x0003
#define RX1_RX_STATUS_RXTESTSEL_0_RESERVED1_ALIGN                  0
#define RX1_RX_STATUS_RXTESTSEL_0_RESERVED1_BITS                   2
#define RX1_RX_STATUS_RXTESTSEL_0_RESERVED1_SHIFT                  0


/* union - case rxTestSel_1 [15:00] */
/* RX1 :: Rx_Status :: reserved0 [15:05] */
#define RX1_RX_STATUS_RXTESTSEL_1_RESERVED0_MASK                   0xffe0
#define RX1_RX_STATUS_RXTESTSEL_1_RESERVED0_ALIGN                  0
#define RX1_RX_STATUS_RXTESTSEL_1_RESERVED0_BITS                   11
#define RX1_RX_STATUS_RXTESTSEL_1_RESERVED0_SHIFT                  5

/* RX1 :: Rx_Status :: cdrAcqDone_r2 [04:04] */
#define RX1_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_MASK               0x0010
#define RX1_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_ALIGN              0
#define RX1_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_BITS               1
#define RX1_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_SHIFT              4

/* RX1 :: Rx_Status :: freq_sel_PC [03:03] */
#define RX1_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_MASK                 0x0008
#define RX1_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_ALIGN                0
#define RX1_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_BITS                 1
#define RX1_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_SHIFT                3

/* RX1 :: Rx_Status :: freq_sel_SM [02:02] */
#define RX1_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_MASK                 0x0004
#define RX1_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_ALIGN                0
#define RX1_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_BITS                 1
#define RX1_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_SHIFT                2

/* RX1 :: Rx_Status :: integ_mode_SM [01:00] */
#define RX1_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_MASK               0x0003
#define RX1_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_ALIGN              0
#define RX1_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_BITS               2
#define RX1_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_SHIFT              0


/* union - case scale_Status [15:00] */
/* RX1 :: Rx_Status :: prop_scale [15:12] */
#define RX1_RX_STATUS_SCALE_STATUS_PROP_SCALE_MASK                 0xf000
#define RX1_RX_STATUS_SCALE_STATUS_PROP_SCALE_ALIGN                0
#define RX1_RX_STATUS_SCALE_STATUS_PROP_SCALE_BITS                 4
#define RX1_RX_STATUS_SCALE_STATUS_PROP_SCALE_SHIFT                12

/* RX1 :: Rx_Status :: integ_scale [11:08] */
#define RX1_RX_STATUS_SCALE_STATUS_INTEG_SCALE_MASK                0x0f00
#define RX1_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ALIGN               0
#define RX1_RX_STATUS_SCALE_STATUS_INTEG_SCALE_BITS                4
#define RX1_RX_STATUS_SCALE_STATUS_INTEG_SCALE_SHIFT               8

/* RX1 :: Rx_Status :: prop_scale_acq [07:04] */
#define RX1_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_MASK             0x00f0
#define RX1_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_ALIGN            0
#define RX1_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_BITS             4
#define RX1_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_SHIFT            4

/* RX1 :: Rx_Status :: integ_scale_acq [03:00] */
#define RX1_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_MASK            0x000f
#define RX1_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_ALIGN           0
#define RX1_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_BITS            4
#define RX1_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_SHIFT           0


/* union - case adc_CdrStatus1 [15:00] */
/* RX1 :: Rx_Status :: reserved0 [15:07] */
#define RX1_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_MASK                0xff80
#define RX1_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_ALIGN               0
#define RX1_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_BITS                9
#define RX1_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_SHIFT               7

/* RX1 :: Rx_Status :: rxMuxCkSel [06:06] */
#define RX1_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_MASK               0x0040
#define RX1_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_ALIGN              0
#define RX1_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_BITS               1
#define RX1_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_SHIFT              6

/* RX1 :: Rx_Status :: glpbk_combo [05:05] */
#define RX1_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_MASK              0x0020
#define RX1_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_ALIGN             0
#define RX1_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_BITS              1
#define RX1_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_SHIFT             5

/* RX1 :: Rx_Status :: clockSwitchSel [04:04] */
#define RX1_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_MASK           0x0010
#define RX1_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_ALIGN          0
#define RX1_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_BITS           1
#define RX1_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_SHIFT          4

/* RX1 :: Rx_Status :: rxck_tst [03:03] */
#define RX1_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_MASK                 0x0008
#define RX1_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_ALIGN                0
#define RX1_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_BITS                 1
#define RX1_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_SHIFT                3

/* RX1 :: Rx_Status :: rxck_i [02:02] */
#define RX1_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_MASK                   0x0004
#define RX1_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_ALIGN                  0
#define RX1_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_BITS                   1
#define RX1_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_SHIFT                  2

/* RX1 :: Rx_Status :: refclk [01:01] */
#define RX1_RX_STATUS_ADC_CDRSTATUS1_REFCLK_MASK                   0x0002
#define RX1_RX_STATUS_ADC_CDRSTATUS1_REFCLK_ALIGN                  0
#define RX1_RX_STATUS_ADC_CDRSTATUS1_REFCLK_BITS                   1
#define RX1_RX_STATUS_ADC_CDRSTATUS1_REFCLK_SHIFT                  1

/* RX1 :: Rx_Status :: pll_bypass [00:00] */
#define RX1_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_MASK               0x0001
#define RX1_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_ALIGN              0
#define RX1_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_BITS               1
#define RX1_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_SHIFT              0


/* union - case adc_CdrStatus2 [15:00] */
/* RX1 :: Rx_Status :: reserved0 [15:06] */
#define RX1_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_MASK                0xffc0
#define RX1_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_ALIGN               0
#define RX1_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_BITS                10
#define RX1_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_SHIFT               6

/* RX1 :: Rx_Status :: rxMuxCkSel [05:05] */
#define RX1_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_MASK               0x0020
#define RX1_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_ALIGN              0
#define RX1_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_BITS               1
#define RX1_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_SHIFT              5

/* RX1 :: Rx_Status :: rxSeqStart [04:04] */
#define RX1_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_MASK               0x0010
#define RX1_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_ALIGN              0
#define RX1_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_BITS               1
#define RX1_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_SHIFT              4

/* RX1 :: Rx_Status :: reserved1 [03:01] */
#define RX1_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_MASK                0x000e
#define RX1_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_ALIGN               0
#define RX1_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_BITS                3
#define RX1_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_SHIFT               1

/* RX1 :: Rx_Status :: rxSeqDone [00:00] */
#define RX1_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_MASK                0x0001
#define RX1_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_ALIGN               0
#define RX1_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_BITS                1
#define RX1_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_SHIFT               0


/* union - case adc_CdrStatus3 [15:00] */
/* RX1 :: Rx_Status :: reserved0 [15:04] */
#define RX1_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_MASK                0xfff0
#define RX1_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_ALIGN               0
#define RX1_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_BITS                12
#define RX1_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_SHIFT               4

/* RX1 :: Rx_Status :: rxSeqStart [03:03] */
#define RX1_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_MASK               0x0008
#define RX1_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_ALIGN              0
#define RX1_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_BITS               1
#define RX1_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_SHIFT              3

/* RX1 :: Rx_Status :: reserved1 [02:01] */
#define RX1_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_MASK                0x0006
#define RX1_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_ALIGN               0
#define RX1_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_BITS                2
#define RX1_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_SHIFT               1

/* RX1 :: Rx_Status :: allow_increment_PC [00:00] */
#define RX1_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_MASK       0x0001
#define RX1_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_ALIGN      0
#define RX1_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_BITS       1
#define RX1_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_SHIFT      0


/* union - case adc_CdrStatus4 [15:00] */
/* RX1 :: Rx_Status :: reserved0 [15:08] */
#define RX1_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_MASK                0xff00
#define RX1_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_ALIGN               0
#define RX1_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_BITS                8
#define RX1_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_SHIFT               8

/* RX1 :: Rx_Status :: rx_pwrdn [07:07] */
#define RX1_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_MASK                 0x0080
#define RX1_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_ALIGN                0
#define RX1_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_BITS                 1
#define RX1_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_SHIFT                7

/* RX1 :: Rx_Status :: freq_sel [06:06] */
#define RX1_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_MASK                 0x0040
#define RX1_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_ALIGN                0
#define RX1_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_BITS                 1
#define RX1_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_SHIFT                6

/* RX1 :: Rx_Status :: pll_lock_rstb [05:05] */
#define RX1_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_MASK            0x0020
#define RX1_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_ALIGN           0
#define RX1_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_BITS            1
#define RX1_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_SHIFT           5

/* RX1 :: Rx_Status :: pwrdn [04:04] */
#define RX1_RX_STATUS_ADC_CDRSTATUS4_PWRDN_MASK                    0x0010
#define RX1_RX_STATUS_ADC_CDRSTATUS4_PWRDN_ALIGN                   0
#define RX1_RX_STATUS_ADC_CDRSTATUS4_PWRDN_BITS                    1
#define RX1_RX_STATUS_ADC_CDRSTATUS4_PWRDN_SHIFT                   4

/* RX1 :: Rx_Status :: reserved1 [03:00] */
#define RX1_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_MASK                0x000f
#define RX1_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_ALIGN               0
#define RX1_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_BITS                4
#define RX1_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_SHIFT               0


/* union - case adc_CdrStatus5 [15:00] */
/* RX1 :: Rx_Status :: reserved0 [15:00] */
#define RX1_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_MASK                0xffff
#define RX1_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_ALIGN               0
#define RX1_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_BITS                16
#define RX1_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_SHIFT               0


/* union - case adc_CdrStatus6 [15:00] */
/* RX1 :: Rx_Status :: reserved0 [15:05] */
#define RX1_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_MASK                0xffe0
#define RX1_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_ALIGN               0
#define RX1_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_BITS                11
#define RX1_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_SHIFT               5

/* RX1 :: Rx_Status :: rx_reset [04:04] */
#define RX1_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_MASK                 0x0010
#define RX1_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_ALIGN                0
#define RX1_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_BITS                 1
#define RX1_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_SHIFT                4

/* RX1 :: Rx_Status :: rx_pwrdn [03:03] */
#define RX1_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_MASK                 0x0008
#define RX1_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_ALIGN                0
#define RX1_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_BITS                 1
#define RX1_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_SHIFT                3

/* RX1 :: Rx_Status :: reset_anlg [02:02] */
#define RX1_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_MASK               0x0004
#define RX1_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_ALIGN              0
#define RX1_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_BITS               1
#define RX1_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_SHIFT              2

/* RX1 :: Rx_Status :: pwrdn_rx [01:01] */
#define RX1_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_MASK                 0x0002
#define RX1_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_ALIGN                0
#define RX1_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_BITS                 1
#define RX1_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_SHIFT                1

/* RX1 :: Rx_Status :: pwrdn_pll [00:00] */
#define RX1_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_MASK                0x0001
#define RX1_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_ALIGN               0
#define RX1_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_BITS                1
#define RX1_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_SHIFT               0


/* union - case adc_CdrStatus7e [15:00] */
/* RX1 :: Rx_Status :: reserved0 [15:05] */
#define RX1_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_MASK               0xffe0
#define RX1_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_ALIGN              0
#define RX1_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_BITS               11
#define RX1_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_SHIFT              5

/* RX1 :: Rx_Status :: rxck0_even [04:04] */
#define RX1_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_MASK              0x0010
#define RX1_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_ALIGN             0
#define RX1_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_BITS              1
#define RX1_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_SHIFT             4

/* RX1 :: Rx_Status :: rxck1_even [03:03] */
#define RX1_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_MASK              0x0008
#define RX1_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_ALIGN             0
#define RX1_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_BITS              1
#define RX1_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_SHIFT             3

/* RX1 :: Rx_Status :: comdet_even [02:02] */
#define RX1_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_MASK             0x0004
#define RX1_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_ALIGN            0
#define RX1_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_BITS             1
#define RX1_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_SHIFT            2

/* RX1 :: Rx_Status :: en_cdet_even [01:01] */
#define RX1_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_MASK            0x0002
#define RX1_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_ALIGN           0
#define RX1_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_BITS            1
#define RX1_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_SHIFT           1

/* RX1 :: Rx_Status :: comma_adj_en_even [00:00] */
#define RX1_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_MASK       0x0001
#define RX1_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_ALIGN      0
#define RX1_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_BITS       1
#define RX1_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_SHIFT      0


/* union - case adc_CdrStatus7o [15:00] */
/* RX1 :: Rx_Status :: reserved0 [15:05] */
#define RX1_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_MASK               0xffe0
#define RX1_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_ALIGN              0
#define RX1_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_BITS               11
#define RX1_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_SHIFT              5

/* RX1 :: Rx_Status :: rxck0_odd [04:04] */
#define RX1_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_MASK               0x0010
#define RX1_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_ALIGN              0
#define RX1_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_BITS               1
#define RX1_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_SHIFT              4

/* RX1 :: Rx_Status :: rxck1_odd [03:03] */
#define RX1_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_MASK               0x0008
#define RX1_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_ALIGN              0
#define RX1_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_BITS               1
#define RX1_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_SHIFT              3

/* RX1 :: Rx_Status :: comdet_odd [02:02] */
#define RX1_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_MASK              0x0004
#define RX1_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_ALIGN             0
#define RX1_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_BITS              1
#define RX1_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_SHIFT             2

/* RX1 :: Rx_Status :: en_cdet_odd [01:01] */
#define RX1_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_MASK             0x0002
#define RX1_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_ALIGN            0
#define RX1_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_BITS             1
#define RX1_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_SHIFT            1

/* RX1 :: Rx_Status :: comma_adj_en_odd [00:00] */
#define RX1_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_MASK        0x0001
#define RX1_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_ALIGN       0
#define RX1_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_BITS        1
#define RX1_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_SHIFT       0


/* union - case adc_CdrStatus8 [15:00] */
/* RX1 :: Rx_Status :: reserved0 [15:01] */
#define RX1_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_MASK                0xfffe
#define RX1_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_ALIGN               0
#define RX1_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_BITS                15
#define RX1_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_SHIFT               1

/* RX1 :: Rx_Status :: sigdet [00:00] */
#define RX1_RX_STATUS_ADC_CDRSTATUS8_SIGDET_MASK                   0x0001
#define RX1_RX_STATUS_ADC_CDRSTATUS8_SIGDET_ALIGN                  0
#define RX1_RX_STATUS_ADC_CDRSTATUS8_SIGDET_BITS                   1
#define RX1_RX_STATUS_ADC_CDRSTATUS8_SIGDET_SHIFT                  0


/* union - case adc_CdrStatus9 [15:00] */
/* RX1 :: Rx_Status :: reserved0 [15:00] */
#define RX1_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_MASK                0xffff
#define RX1_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_ALIGN               0
#define RX1_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_BITS                16
#define RX1_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_SHIFT               0


/* union - case adc_CdrStatus10 [15:00] */
/* RX1 :: Rx_Status :: reserved0 [15:07] */
#define RX1_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_MASK               0xff80
#define RX1_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_ALIGN              0
#define RX1_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_BITS               9
#define RX1_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_SHIFT              7

/* RX1 :: Rx_Status :: prbs_en [06:06] */
#define RX1_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_MASK                 0x0040
#define RX1_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_ALIGN                0
#define RX1_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_BITS                 1
#define RX1_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_SHIFT                6

/* RX1 :: Rx_Status :: rstb_tst [05:05] */
#define RX1_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_MASK                0x0020
#define RX1_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_ALIGN               0
#define RX1_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_BITS                1
#define RX1_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_SHIFT               5

/* RX1 :: Rx_Status :: reserved1 [04:04] */
#define RX1_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_MASK               0x0010
#define RX1_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_ALIGN              0
#define RX1_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_BITS               1
#define RX1_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_SHIFT              4

/* RX1 :: Rx_Status :: prbs_state [03:00] */
#define RX1_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_MASK              0x000f
#define RX1_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_ALIGN             0
#define RX1_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_BITS              4
#define RX1_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_SHIFT             0


/* union - case adc_CdrStatus11 [15:00] */
/* RX1 :: Rx_Status :: reserved0 [15:00] */
#define RX1_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_MASK               0xffff
#define RX1_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_ALIGN              0
#define RX1_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_BITS               16
#define RX1_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_SHIFT              0


/* union - case adc_CdrStatus12_1 [15:00] */
/* RX1 :: Rx_Status :: reserved0 [15:06] */
#define RX1_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_MASK             0xffc0
#define RX1_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_ALIGN            0
#define RX1_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_BITS             10
#define RX1_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_SHIFT            6

/* RX1 :: Rx_Status :: enable4 [05:05] */
#define RX1_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_MASK               0x0020
#define RX1_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_ALIGN              0
#define RX1_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_BITS               1
#define RX1_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_SHIFT              5

/* RX1 :: Rx_Status :: radr_test [04:00] */
#define RX1_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_MASK             0x001f
#define RX1_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_ALIGN            0
#define RX1_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_BITS             5
#define RX1_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_SHIFT            0


/* union - case adc_CdrStatus12_2 [15:00] */
/* RX1 :: Rx_Status :: reserved0 [15:05] */
#define RX1_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_MASK             0xffe0
#define RX1_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_ALIGN            0
#define RX1_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_BITS             11
#define RX1_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_SHIFT            5

/* RX1 :: Rx_Status :: wadr_test [04:00] */
#define RX1_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_MASK             0x001f
#define RX1_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_ALIGN            0
#define RX1_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_BITS             5
#define RX1_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_SHIFT            0


/* union - case adc_CdrStatus12_3 [15:00] */
/* RX1 :: Rx_Status :: reserved0 [15:06] */
#define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_MASK             0xffc0
#define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_ALIGN            0
#define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_BITS             10
#define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_SHIFT            6

/* RX1 :: Rx_Status :: rxck_66B_tmux [05:05] */
#define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_MASK         0x0020
#define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_ALIGN        0
#define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_BITS         1
#define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_SHIFT        5

/* RX1 :: Rx_Status :: rstb_66B [04:04] */
#define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_MASK              0x0010
#define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_ALIGN             0
#define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_BITS              1
#define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_SHIFT             4

/* RX1 :: Rx_Status :: prstb_66B_mux [03:03] */
#define RX1_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_MASK         0x0008
#define RX1_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_ALIGN        0
#define RX1_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_BITS         1
#define RX1_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_SHIFT        3

/* RX1 :: Rx_Status :: rxck_i66_tmux [02:02] */
#define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_MASK         0x0004
#define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_ALIGN        0
#define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_BITS         1
#define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_SHIFT        2

/* RX1 :: Rx_Status :: rstb_i66 [01:01] */
#define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_MASK              0x0002
#define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_ALIGN             0
#define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_BITS              1
#define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_SHIFT             1

/* RX1 :: Rx_Status :: prstb_i66_mux [00:00] */
#define RX1_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_MASK         0x0001
#define RX1_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_ALIGN        0
#define RX1_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_BITS         1
#define RX1_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_SHIFT        0


/* union - case adc_CdrStatus12_4 [15:00] */
/* RX1 :: Rx_Status :: reserved0 [15:04] */
#define RX1_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_MASK             0xfff0
#define RX1_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_ALIGN            0
#define RX1_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_BITS             12
#define RX1_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_SHIFT            4

/* RX1 :: Rx_Status :: rfifo_error_r [03:02] */
#define RX1_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_MASK         0x000c
#define RX1_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_ALIGN        0
#define RX1_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_BITS         2
#define RX1_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_SHIFT        2

/* RX1 :: Rx_Status :: rfifo_unflow [01:01] */
#define RX1_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_MASK          0x0002
#define RX1_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_ALIGN         0
#define RX1_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_BITS          1
#define RX1_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_SHIFT         1

/* RX1 :: Rx_Status :: rfifo_ovflow [00:00] */
#define RX1_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_MASK          0x0001
#define RX1_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_ALIGN         0
#define RX1_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_BITS          1
#define RX1_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_SHIFT         0


/* union - case integ_Status [15:00] */
/* RX1 :: Rx_Status :: integ_status [15:00] */
#define RX1_RX_STATUS_INTEG_STATUS_INTEG_STATUS_MASK               0xffff
#define RX1_RX_STATUS_INTEG_STATUS_INTEG_STATUS_ALIGN              0
#define RX1_RX_STATUS_INTEG_STATUS_INTEG_STATUS_BITS               16
#define RX1_RX_STATUS_INTEG_STATUS_INTEG_STATUS_SHIFT              0


/* union - case vco_Status [15:00] */
/* RX1 :: Rx_Status :: vco_status [15:00] */
#define RX1_RX_STATUS_VCO_STATUS_VCO_STATUS_MASK                   0xffff
#define RX1_RX_STATUS_VCO_STATUS_VCO_STATUS_ALIGN                  0
#define RX1_RX_STATUS_VCO_STATUS_VCO_STATUS_BITS                   16
#define RX1_RX_STATUS_VCO_STATUS_VCO_STATUS_SHIFT                  0


/* union - case prbs_Status [15:00] */
/* RX1 :: Rx_Status :: prbs_lock [15:15] */
#define RX1_RX_STATUS_PRBS_STATUS_PRBS_LOCK_MASK                   0x8000
#define RX1_RX_STATUS_PRBS_STATUS_PRBS_LOCK_ALIGN                  0
#define RX1_RX_STATUS_PRBS_STATUS_PRBS_LOCK_BITS                   1
#define RX1_RX_STATUS_PRBS_STATUS_PRBS_LOCK_SHIFT                  15

/* RX1 :: Rx_Status :: prbs_stky [14:14] */
#define RX1_RX_STATUS_PRBS_STATUS_PRBS_STKY_MASK                   0x4000
#define RX1_RX_STATUS_PRBS_STATUS_PRBS_STKY_ALIGN                  0
#define RX1_RX_STATUS_PRBS_STATUS_PRBS_STKY_BITS                   1
#define RX1_RX_STATUS_PRBS_STATUS_PRBS_STKY_SHIFT                  14

/* RX1 :: Rx_Status :: ptbs_errors [13:00] */
#define RX1_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_MASK                 0x3fff
#define RX1_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_ALIGN                0
#define RX1_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_BITS                 14
#define RX1_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_SHIFT                0



/****************************************************************************
 * RX1 :: Rx_Control
 ***************************************************************************/
/* RX1 :: Rx_Control :: reserved0 [15:03] */
#define RX1_RX_CONTROL_RESERVED0_MASK                              0xfff8
#define RX1_RX_CONTROL_RESERVED0_ALIGN                             0
#define RX1_RX_CONTROL_RESERVED0_BITS                              13
#define RX1_RX_CONTROL_RESERVED0_SHIFT                             3

/* RX1 :: Rx_Control :: status_sel [02:00] */
#define RX1_RX_CONTROL_STATUS_SEL_MASK                             0x0007
#define RX1_RX_CONTROL_STATUS_SEL_ALIGN                            0
#define RX1_RX_CONTROL_STATUS_SEL_BITS                             3
#define RX1_RX_CONTROL_STATUS_SEL_SHIFT                            0
#define RX1_RX_CONTROL_STATUS_SEL_sigdetStatus                     0
#define RX1_RX_CONTROL_STATUS_SEL_syncStatus                       1
#define RX1_RX_CONTROL_STATUS_SEL_rxTestSel                        2
#define RX1_RX_CONTROL_STATUS_SEL_scaleStatus                      3
#define RX1_RX_CONTROL_STATUS_SEL_adcCdrStatus                     4
#define RX1_RX_CONTROL_STATUS_SEL_integStatus                      5
#define RX1_RX_CONTROL_STATUS_SEL_vcoStatus                        6
#define RX1_RX_CONTROL_STATUS_SEL_prbsStatus                       7


/****************************************************************************
 * RX1 :: Rx_Test
 ***************************************************************************/
/* RX1 :: Rx_Test :: sigdet_mux_SM [15:12] */
#define RX1_RX_TEST_SIGDET_MUX_SM_MASK                             0xf000
#define RX1_RX_TEST_SIGDET_MUX_SM_ALIGN                            0
#define RX1_RX_TEST_SIGDET_MUX_SM_BITS                             4
#define RX1_RX_TEST_SIGDET_MUX_SM_SHIFT                            12

/* RX1 :: Rx_Test :: reserved0 [11:09] */
#define RX1_RX_TEST_RESERVED0_MASK                                 0x0e00
#define RX1_RX_TEST_RESERVED0_ALIGN                                0
#define RX1_RX_TEST_RESERVED0_BITS                                 3
#define RX1_RX_TEST_RESERVED0_SHIFT                                9

/* RX1 :: Rx_Test :: tpctrl_SM [08:04] */
#define RX1_RX_TEST_TPCTRL_SM_MASK                                 0x01f0
#define RX1_RX_TEST_TPCTRL_SM_ALIGN                                0
#define RX1_RX_TEST_TPCTRL_SM_BITS                                 5
#define RX1_RX_TEST_TPCTRL_SM_SHIFT                                4

/* RX1 :: Rx_Test :: testMuxSelect_SM [03:00] */
#define RX1_RX_TEST_TESTMUXSELECT_SM_MASK                          0x000f
#define RX1_RX_TEST_TESTMUXSELECT_SM_ALIGN                         0
#define RX1_RX_TEST_TESTMUXSELECT_SM_BITS                          4
#define RX1_RX_TEST_TESTMUXSELECT_SM_SHIFT                         0


/****************************************************************************
 * RX1 :: Rx_Control_1G_type
 ***************************************************************************/
/* RX1 :: Rx_Control_1G_type :: fpat_md [15:15] */
#define RX1_RX_CONTROL_1G_TYPE_FPAT_MD_MASK                        0x8000
#define RX1_RX_CONTROL_1G_TYPE_FPAT_MD_ALIGN                       0
#define RX1_RX_CONTROL_1G_TYPE_FPAT_MD_BITS                        1
#define RX1_RX_CONTROL_1G_TYPE_FPAT_MD_SHIFT                       15

/* RX1 :: Rx_Control_1G_type :: pkt_count_en [14:14] */
#define RX1_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_MASK                   0x4000
#define RX1_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_ALIGN                  0
#define RX1_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_BITS                   1
#define RX1_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_SHIFT                  14

/* RX1 :: Rx_Control_1G_type :: staMuxRegDis [13:13] */
#define RX1_RX_CONTROL_1G_TYPE_STAMUXREGDIS_MASK                   0x2000
#define RX1_RX_CONTROL_1G_TYPE_STAMUXREGDIS_ALIGN                  0
#define RX1_RX_CONTROL_1G_TYPE_STAMUXREGDIS_BITS                   1
#define RX1_RX_CONTROL_1G_TYPE_STAMUXREGDIS_SHIFT                  13

/* RX1 :: Rx_Control_1G_type :: prbs_clr_dis [12:12] */
#define RX1_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_MASK                   0x1000
#define RX1_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_ALIGN                  0
#define RX1_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_BITS                   1
#define RX1_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_SHIFT                  12

/* RX1 :: Rx_Control_1G_type :: rxd_dec_sel [11:11] */
#define RX1_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_MASK                    0x0800
#define RX1_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_ALIGN                   0
#define RX1_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_BITS                    1
#define RX1_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_SHIFT                   11

/* RX1 :: Rx_Control_1G_type :: cgbad_tst [10:10] */
#define RX1_RX_CONTROL_1G_TYPE_CGBAD_TST_MASK                      0x0400
#define RX1_RX_CONTROL_1G_TYPE_CGBAD_TST_ALIGN                     0
#define RX1_RX_CONTROL_1G_TYPE_CGBAD_TST_BITS                      1
#define RX1_RX_CONTROL_1G_TYPE_CGBAD_TST_SHIFT                     10

/* RX1 :: Rx_Control_1G_type :: Emon_en [09:09] */
#define RX1_RX_CONTROL_1G_TYPE_EMON_EN_MASK                        0x0200
#define RX1_RX_CONTROL_1G_TYPE_EMON_EN_ALIGN                       0
#define RX1_RX_CONTROL_1G_TYPE_EMON_EN_BITS                        1
#define RX1_RX_CONTROL_1G_TYPE_EMON_EN_SHIFT                       9

/* RX1 :: Rx_Control_1G_type :: prbs_en [08:08] */
#define RX1_RX_CONTROL_1G_TYPE_PRBS_EN_MASK                        0x0100
#define RX1_RX_CONTROL_1G_TYPE_PRBS_EN_ALIGN                       0
#define RX1_RX_CONTROL_1G_TYPE_PRBS_EN_BITS                        1
#define RX1_RX_CONTROL_1G_TYPE_PRBS_EN_SHIFT                       8

/* RX1 :: Rx_Control_1G_type :: cgbad_en [07:07] */
#define RX1_RX_CONTROL_1G_TYPE_CGBAD_EN_MASK                       0x0080
#define RX1_RX_CONTROL_1G_TYPE_CGBAD_EN_ALIGN                      0
#define RX1_RX_CONTROL_1G_TYPE_CGBAD_EN_BITS                       1
#define RX1_RX_CONTROL_1G_TYPE_CGBAD_EN_SHIFT                      7

/* RX1 :: Rx_Control_1G_type :: cstretch [06:06] */
#define RX1_RX_CONTROL_1G_TYPE_CSTRETCH_MASK                       0x0040
#define RX1_RX_CONTROL_1G_TYPE_CSTRETCH_ALIGN                      0
#define RX1_RX_CONTROL_1G_TYPE_CSTRETCH_BITS                       1
#define RX1_RX_CONTROL_1G_TYPE_CSTRETCH_SHIFT                      6

/* RX1 :: Rx_Control_1G_type :: rtbi_ckflip [05:05] */
#define RX1_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_MASK                    0x0020
#define RX1_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_ALIGN                   0
#define RX1_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_BITS                    1
#define RX1_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_SHIFT                   5

/* RX1 :: Rx_Control_1G_type :: rtbi_flip [04:04] */
#define RX1_RX_CONTROL_1G_TYPE_RTBI_FLIP_MASK                      0x0010
#define RX1_RX_CONTROL_1G_TYPE_RTBI_FLIP_ALIGN                     0
#define RX1_RX_CONTROL_1G_TYPE_RTBI_FLIP_BITS                      1
#define RX1_RX_CONTROL_1G_TYPE_RTBI_FLIP_SHIFT                     4

/* RX1 :: Rx_Control_1G_type :: phase_sel [03:03] */
#define RX1_RX_CONTROL_1G_TYPE_PHASE_SEL_MASK                      0x0008
#define RX1_RX_CONTROL_1G_TYPE_PHASE_SEL_ALIGN                     0
#define RX1_RX_CONTROL_1G_TYPE_PHASE_SEL_BITS                      1
#define RX1_RX_CONTROL_1G_TYPE_PHASE_SEL_SHIFT                     3

/* RX1 :: Rx_Control_1G_type :: reserved0 [02:02] */
#define RX1_RX_CONTROL_1G_TYPE_RESERVED0_MASK                      0x0004
#define RX1_RX_CONTROL_1G_TYPE_RESERVED0_ALIGN                     0
#define RX1_RX_CONTROL_1G_TYPE_RESERVED0_BITS                      1
#define RX1_RX_CONTROL_1G_TYPE_RESERVED0_SHIFT                     2

/* RX1 :: Rx_Control_1G_type :: freq_sel_force [01:01] */
#define RX1_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_MASK                 0x0002
#define RX1_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_ALIGN                0
#define RX1_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_BITS                 1
#define RX1_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_SHIFT                1

/* RX1 :: Rx_Control_1G_type :: freq_sel [00:00] */
#define RX1_RX_CONTROL_1G_TYPE_FREQ_SEL_MASK                       0x0001
#define RX1_RX_CONTROL_1G_TYPE_FREQ_SEL_ALIGN                      0
#define RX1_RX_CONTROL_1G_TYPE_FREQ_SEL_BITS                       1
#define RX1_RX_CONTROL_1G_TYPE_FREQ_SEL_SHIFT                      0


/****************************************************************************
 * RX1 :: Rx_Astatus
 ***************************************************************************/
/* RX1 :: Rx_Astatus :: reserved0 [15:01] */
#define RX1_RX_ASTATUS_RESERVED0_MASK                              0xfffe
#define RX1_RX_ASTATUS_RESERVED0_ALIGN                             0
#define RX1_RX_ASTATUS_RESERVED0_BITS                              15
#define RX1_RX_ASTATUS_RESERVED0_SHIFT                             1

/* RX1 :: Rx_Astatus :: sigdet [00:00] */
#define RX1_RX_ASTATUS_SIGDET_MASK                                 0x0001
#define RX1_RX_ASTATUS_SIGDET_ALIGN                                0
#define RX1_RX_ASTATUS_SIGDET_BITS                                 1
#define RX1_RX_ASTATUS_SIGDET_SHIFT                                0


/****************************************************************************
 * RX1 :: Rx_analogBias0
 ***************************************************************************/
/* RX1 :: Rx_analogBias0 :: imode_vcm [15:15] */
#define RX1_RX_ANALOGBIAS0_IMODE_VCM_MASK                          0x8000
#define RX1_RX_ANALOGBIAS0_IMODE_VCM_ALIGN                         0
#define RX1_RX_ANALOGBIAS0_IMODE_VCM_BITS                          1
#define RX1_RX_ANALOGBIAS0_IMODE_VCM_SHIFT                         15

/* RX1 :: Rx_analogBias0 :: imin_vcm [14:14] */
#define RX1_RX_ANALOGBIAS0_IMIN_VCM_MASK                           0x4000
#define RX1_RX_ANALOGBIAS0_IMIN_VCM_ALIGN                          0
#define RX1_RX_ANALOGBIAS0_IMIN_VCM_BITS                           1
#define RX1_RX_ANALOGBIAS0_IMIN_VCM_SHIFT                          14

/* RX1 :: Rx_analogBias0 :: imax_sigdet [13:13] */
#define RX1_RX_ANALOGBIAS0_IMAX_SIGDET_MASK                        0x2000
#define RX1_RX_ANALOGBIAS0_IMAX_SIGDET_ALIGN                       0
#define RX1_RX_ANALOGBIAS0_IMAX_SIGDET_BITS                        1
#define RX1_RX_ANALOGBIAS0_IMAX_SIGDET_SHIFT                       13

/* RX1 :: Rx_analogBias0 :: imode_sigdet [12:12] */
#define RX1_RX_ANALOGBIAS0_IMODE_SIGDET_MASK                       0x1000
#define RX1_RX_ANALOGBIAS0_IMODE_SIGDET_ALIGN                      0
#define RX1_RX_ANALOGBIAS0_IMODE_SIGDET_BITS                       1
#define RX1_RX_ANALOGBIAS0_IMODE_SIGDET_SHIFT                      12

/* RX1 :: Rx_analogBias0 :: imin_sigdet [11:11] */
#define RX1_RX_ANALOGBIAS0_IMIN_SIGDET_MASK                        0x0800
#define RX1_RX_ANALOGBIAS0_IMIN_SIGDET_ALIGN                       0
#define RX1_RX_ANALOGBIAS0_IMIN_SIGDET_BITS                        1
#define RX1_RX_ANALOGBIAS0_IMIN_SIGDET_SHIFT                       11

/* RX1 :: Rx_analogBias0 :: refh_rx [10:10] */
#define RX1_RX_ANALOGBIAS0_REFH_RX_MASK                            0x0400
#define RX1_RX_ANALOGBIAS0_REFH_RX_ALIGN                           0
#define RX1_RX_ANALOGBIAS0_REFH_RX_BITS                            1
#define RX1_RX_ANALOGBIAS0_REFH_RX_SHIFT                           10

/* RX1 :: Rx_analogBias0 :: refl_rx [09:09] */
#define RX1_RX_ANALOGBIAS0_REFL_RX_MASK                            0x0200
#define RX1_RX_ANALOGBIAS0_REFL_RX_ALIGN                           0
#define RX1_RX_ANALOGBIAS0_REFL_RX_BITS                            1
#define RX1_RX_ANALOGBIAS0_REFL_RX_SHIFT                           9

/* RX1 :: Rx_analogBias0 :: tport_en [08:08] */
#define RX1_RX_ANALOGBIAS0_TPORT_EN_MASK                           0x0100
#define RX1_RX_ANALOGBIAS0_TPORT_EN_ALIGN                          0
#define RX1_RX_ANALOGBIAS0_TPORT_EN_BITS                           1
#define RX1_RX_ANALOGBIAS0_TPORT_EN_SHIFT                          8

/* RX1 :: Rx_analogBias0 :: vddr_bg [07:07] */
#define RX1_RX_ANALOGBIAS0_VDDR_BG_MASK                            0x0080
#define RX1_RX_ANALOGBIAS0_VDDR_BG_ALIGN                           0
#define RX1_RX_ANALOGBIAS0_VDDR_BG_BITS                            1
#define RX1_RX_ANALOGBIAS0_VDDR_BG_SHIFT                           7

/* RX1 :: Rx_analogBias0 :: sig_pwrdn [06:06] */
#define RX1_RX_ANALOGBIAS0_SIG_PWRDN_MASK                          0x0040
#define RX1_RX_ANALOGBIAS0_SIG_PWRDN_ALIGN                         0
#define RX1_RX_ANALOGBIAS0_SIG_PWRDN_BITS                          1
#define RX1_RX_ANALOGBIAS0_SIG_PWRDN_SHIFT                         6

/* RX1 :: Rx_analogBias0 :: offset_ctrl [05:03] */
#define RX1_RX_ANALOGBIAS0_OFFSET_CTRL_MASK                        0x0038
#define RX1_RX_ANALOGBIAS0_OFFSET_CTRL_ALIGN                       0
#define RX1_RX_ANALOGBIAS0_OFFSET_CTRL_BITS                        3
#define RX1_RX_ANALOGBIAS0_OFFSET_CTRL_SHIFT                       3

/* RX1 :: Rx_analogBias0 :: offset_sel [02:02] */
#define RX1_RX_ANALOGBIAS0_OFFSET_SEL_MASK                         0x0004
#define RX1_RX_ANALOGBIAS0_OFFSET_SEL_ALIGN                        0
#define RX1_RX_ANALOGBIAS0_OFFSET_SEL_BITS                         1
#define RX1_RX_ANALOGBIAS0_OFFSET_SEL_SHIFT                        2

/* RX1 :: Rx_analogBias0 :: reserved0 [01:00] */
#define RX1_RX_ANALOGBIAS0_RESERVED0_MASK                          0x0003
#define RX1_RX_ANALOGBIAS0_RESERVED0_ALIGN                         0
#define RX1_RX_ANALOGBIAS0_RESERVED0_BITS                          2
#define RX1_RX_ANALOGBIAS0_RESERVED0_SHIFT                         0


/****************************************************************************
 * RX1 :: Rx_analogBias1
 ***************************************************************************/
/* RX1 :: Rx_analogBias1 :: imax_clkbuf [15:15] */
#define RX1_RX_ANALOGBIAS1_IMAX_CLKBUF_MASK                        0x8000
#define RX1_RX_ANALOGBIAS1_IMAX_CLKBUF_ALIGN                       0
#define RX1_RX_ANALOGBIAS1_IMAX_CLKBUF_BITS                        1
#define RX1_RX_ANALOGBIAS1_IMAX_CLKBUF_SHIFT                       15

/* RX1 :: Rx_analogBias1 :: imode_clkbuf [14:14] */
#define RX1_RX_ANALOGBIAS1_IMODE_CLKBUF_MASK                       0x4000
#define RX1_RX_ANALOGBIAS1_IMODE_CLKBUF_ALIGN                      0
#define RX1_RX_ANALOGBIAS1_IMODE_CLKBUF_BITS                       1
#define RX1_RX_ANALOGBIAS1_IMODE_CLKBUF_SHIFT                      14

/* RX1 :: Rx_analogBias1 :: imin_clkbuf [13:13] */
#define RX1_RX_ANALOGBIAS1_IMIN_CLKBUF_MASK                        0x2000
#define RX1_RX_ANALOGBIAS1_IMIN_CLKBUF_ALIGN                       0
#define RX1_RX_ANALOGBIAS1_IMIN_CLKBUF_BITS                        1
#define RX1_RX_ANALOGBIAS1_IMIN_CLKBUF_SHIFT                       13

/* RX1 :: Rx_analogBias1 :: imax_eqfl [12:12] */
#define RX1_RX_ANALOGBIAS1_IMAX_EQFL_MASK                          0x1000
#define RX1_RX_ANALOGBIAS1_IMAX_EQFL_ALIGN                         0
#define RX1_RX_ANALOGBIAS1_IMAX_EQFL_BITS                          1
#define RX1_RX_ANALOGBIAS1_IMAX_EQFL_SHIFT                         12

/* RX1 :: Rx_analogBias1 :: imode_eqfl [11:11] */
#define RX1_RX_ANALOGBIAS1_IMODE_EQFL_MASK                         0x0800
#define RX1_RX_ANALOGBIAS1_IMODE_EQFL_ALIGN                        0
#define RX1_RX_ANALOGBIAS1_IMODE_EQFL_BITS                         1
#define RX1_RX_ANALOGBIAS1_IMODE_EQFL_SHIFT                        11

/* RX1 :: Rx_analogBias1 :: imin_eqfl [10:10] */
#define RX1_RX_ANALOGBIAS1_IMIN_EQFL_MASK                          0x0400
#define RX1_RX_ANALOGBIAS1_IMIN_EQFL_ALIGN                         0
#define RX1_RX_ANALOGBIAS1_IMIN_EQFL_BITS                          1
#define RX1_RX_ANALOGBIAS1_IMIN_EQFL_SHIFT                         10

/* RX1 :: Rx_analogBias1 :: imax_dfesum [09:09] */
#define RX1_RX_ANALOGBIAS1_IMAX_DFESUM_MASK                        0x0200
#define RX1_RX_ANALOGBIAS1_IMAX_DFESUM_ALIGN                       0
#define RX1_RX_ANALOGBIAS1_IMAX_DFESUM_BITS                        1
#define RX1_RX_ANALOGBIAS1_IMAX_DFESUM_SHIFT                       9

/* RX1 :: Rx_analogBias1 :: imode_dfesum [08:08] */
#define RX1_RX_ANALOGBIAS1_IMODE_DFESUM_MASK                       0x0100
#define RX1_RX_ANALOGBIAS1_IMODE_DFESUM_ALIGN                      0
#define RX1_RX_ANALOGBIAS1_IMODE_DFESUM_BITS                       1
#define RX1_RX_ANALOGBIAS1_IMODE_DFESUM_SHIFT                      8

/* RX1 :: Rx_analogBias1 :: imin_dfesum [07:07] */
#define RX1_RX_ANALOGBIAS1_IMIN_DFESUM_MASK                        0x0080
#define RX1_RX_ANALOGBIAS1_IMIN_DFESUM_ALIGN                       0
#define RX1_RX_ANALOGBIAS1_IMIN_DFESUM_BITS                        1
#define RX1_RX_ANALOGBIAS1_IMIN_DFESUM_SHIFT                       7

/* RX1 :: Rx_analogBias1 :: imax_vga [06:06] */
#define RX1_RX_ANALOGBIAS1_IMAX_VGA_MASK                           0x0040
#define RX1_RX_ANALOGBIAS1_IMAX_VGA_ALIGN                          0
#define RX1_RX_ANALOGBIAS1_IMAX_VGA_BITS                           1
#define RX1_RX_ANALOGBIAS1_IMAX_VGA_SHIFT                          6

/* RX1 :: Rx_analogBias1 :: imode_vga [05:05] */
#define RX1_RX_ANALOGBIAS1_IMODE_VGA_MASK                          0x0020
#define RX1_RX_ANALOGBIAS1_IMODE_VGA_ALIGN                         0
#define RX1_RX_ANALOGBIAS1_IMODE_VGA_BITS                          1
#define RX1_RX_ANALOGBIAS1_IMODE_VGA_SHIFT                         5

/* RX1 :: Rx_analogBias1 :: imin_vga [04:04] */
#define RX1_RX_ANALOGBIAS1_IMIN_VGA_MASK                           0x0010
#define RX1_RX_ANALOGBIAS1_IMIN_VGA_ALIGN                          0
#define RX1_RX_ANALOGBIAS1_IMIN_VGA_BITS                           1
#define RX1_RX_ANALOGBIAS1_IMIN_VGA_SHIFT                          4

/* RX1 :: Rx_analogBias1 :: imax_interp [03:03] */
#define RX1_RX_ANALOGBIAS1_IMAX_INTERP_MASK                        0x0008
#define RX1_RX_ANALOGBIAS1_IMAX_INTERP_ALIGN                       0
#define RX1_RX_ANALOGBIAS1_IMAX_INTERP_BITS                        1
#define RX1_RX_ANALOGBIAS1_IMAX_INTERP_SHIFT                       3

/* RX1 :: Rx_analogBias1 :: imode_interp [02:02] */
#define RX1_RX_ANALOGBIAS1_IMODE_INTERP_MASK                       0x0004
#define RX1_RX_ANALOGBIAS1_IMODE_INTERP_ALIGN                      0
#define RX1_RX_ANALOGBIAS1_IMODE_INTERP_BITS                       1
#define RX1_RX_ANALOGBIAS1_IMODE_INTERP_SHIFT                      2

/* RX1 :: Rx_analogBias1 :: imin_interp [01:01] */
#define RX1_RX_ANALOGBIAS1_IMIN_INTERP_MASK                        0x0002
#define RX1_RX_ANALOGBIAS1_IMIN_INTERP_ALIGN                       0
#define RX1_RX_ANALOGBIAS1_IMIN_INTERP_BITS                        1
#define RX1_RX_ANALOGBIAS1_IMIN_INTERP_SHIFT                       1

/* RX1 :: Rx_analogBias1 :: imax_vcm [00:00] */
#define RX1_RX_ANALOGBIAS1_IMAX_VCM_MASK                           0x0001
#define RX1_RX_ANALOGBIAS1_IMAX_VCM_ALIGN                          0
#define RX1_RX_ANALOGBIAS1_IMAX_VCM_BITS                           1
#define RX1_RX_ANALOGBIAS1_IMAX_VCM_SHIFT                          0


/****************************************************************************
 * RX1 :: Rx_analogBias2
 ***************************************************************************/
/* RX1 :: Rx_analogBias2 :: en_clk16 [15:15] */
#define RX1_RX_ANALOGBIAS2_EN_CLK16_MASK                           0x8000
#define RX1_RX_ANALOGBIAS2_EN_CLK16_ALIGN                          0
#define RX1_RX_ANALOGBIAS2_EN_CLK16_BITS                           1
#define RX1_RX_ANALOGBIAS2_EN_CLK16_SHIFT                          15

/* RX1 :: Rx_analogBias2 :: pd_ch_p1 [14:14] */
#define RX1_RX_ANALOGBIAS2_PD_CH_P1_MASK                           0x4000
#define RX1_RX_ANALOGBIAS2_PD_CH_P1_ALIGN                          0
#define RX1_RX_ANALOGBIAS2_PD_CH_P1_BITS                           1
#define RX1_RX_ANALOGBIAS2_PD_CH_P1_SHIFT                          14

/* RX1 :: Rx_analogBias2 :: en_vcctrl [13:13] */
#define RX1_RX_ANALOGBIAS2_EN_VCCTRL_MASK                          0x2000
#define RX1_RX_ANALOGBIAS2_EN_VCCTRL_ALIGN                         0
#define RX1_RX_ANALOGBIAS2_EN_VCCTRL_BITS                          1
#define RX1_RX_ANALOGBIAS2_EN_VCCTRL_SHIFT                         13

/* RX1 :: Rx_analogBias2 :: en_dfeclk [12:12] */
#define RX1_RX_ANALOGBIAS2_EN_DFECLK_MASK                          0x1000
#define RX1_RX_ANALOGBIAS2_EN_DFECLK_ALIGN                         0
#define RX1_RX_ANALOGBIAS2_EN_DFECLK_BITS                          1
#define RX1_RX_ANALOGBIAS2_EN_DFECLK_SHIFT                         12

/* RX1 :: Rx_analogBias2 :: en_hgain [11:11] */
#define RX1_RX_ANALOGBIAS2_EN_HGAIN_MASK                           0x0800
#define RX1_RX_ANALOGBIAS2_EN_HGAIN_ALIGN                          0
#define RX1_RX_ANALOGBIAS2_EN_HGAIN_BITS                           1
#define RX1_RX_ANALOGBIAS2_EN_HGAIN_SHIFT                          11

/* RX1 :: Rx_analogBias2 :: en_dfeckpwr [10:10] */
#define RX1_RX_ANALOGBIAS2_EN_DFECKPWR_MASK                        0x0400
#define RX1_RX_ANALOGBIAS2_EN_DFECKPWR_ALIGN                       0
#define RX1_RX_ANALOGBIAS2_EN_DFECKPWR_BITS                        1
#define RX1_RX_ANALOGBIAS2_EN_DFECKPWR_SHIFT                       10

/* RX1 :: Rx_analogBias2 :: offset_pd [09:09] */
#define RX1_RX_ANALOGBIAS2_OFFSET_PD_MASK                          0x0200
#define RX1_RX_ANALOGBIAS2_OFFSET_PD_ALIGN                         0
#define RX1_RX_ANALOGBIAS2_OFFSET_PD_BITS                          1
#define RX1_RX_ANALOGBIAS2_OFFSET_PD_SHIFT                         9

/* RX1 :: Rx_analogBias2 :: imax_dfetap [08:08] */
#define RX1_RX_ANALOGBIAS2_IMAX_DFETAP_MASK                        0x0100
#define RX1_RX_ANALOGBIAS2_IMAX_DFETAP_ALIGN                       0
#define RX1_RX_ANALOGBIAS2_IMAX_DFETAP_BITS                        1
#define RX1_RX_ANALOGBIAS2_IMAX_DFETAP_SHIFT                       8

/* RX1 :: Rx_analogBias2 :: imode_dfetap [07:07] */
#define RX1_RX_ANALOGBIAS2_IMODE_DFETAP_MASK                       0x0080
#define RX1_RX_ANALOGBIAS2_IMODE_DFETAP_ALIGN                      0
#define RX1_RX_ANALOGBIAS2_IMODE_DFETAP_BITS                       1
#define RX1_RX_ANALOGBIAS2_IMODE_DFETAP_SHIFT                      7

/* RX1 :: Rx_analogBias2 :: imin_dfetap [06:06] */
#define RX1_RX_ANALOGBIAS2_IMIN_DFETAP_MASK                        0x0040
#define RX1_RX_ANALOGBIAS2_IMIN_DFETAP_ALIGN                       0
#define RX1_RX_ANALOGBIAS2_IMIN_DFETAP_BITS                        1
#define RX1_RX_ANALOGBIAS2_IMIN_DFETAP_SHIFT                       6

/* RX1 :: Rx_analogBias2 :: imax_slcd2c [05:05] */
#define RX1_RX_ANALOGBIAS2_IMAX_SLCD2C_MASK                        0x0020
#define RX1_RX_ANALOGBIAS2_IMAX_SLCD2C_ALIGN                       0
#define RX1_RX_ANALOGBIAS2_IMAX_SLCD2C_BITS                        1
#define RX1_RX_ANALOGBIAS2_IMAX_SLCD2C_SHIFT                       5

/* RX1 :: Rx_analogBias2 :: imode_slcd2c [04:04] */
#define RX1_RX_ANALOGBIAS2_IMODE_SLCD2C_MASK                       0x0010
#define RX1_RX_ANALOGBIAS2_IMODE_SLCD2C_ALIGN                      0
#define RX1_RX_ANALOGBIAS2_IMODE_SLCD2C_BITS                       1
#define RX1_RX_ANALOGBIAS2_IMODE_SLCD2C_SHIFT                      4

/* RX1 :: Rx_analogBias2 :: imin_slcd2c [03:03] */
#define RX1_RX_ANALOGBIAS2_IMIN_SLCD2C_MASK                        0x0008
#define RX1_RX_ANALOGBIAS2_IMIN_SLCD2C_ALIGN                       0
#define RX1_RX_ANALOGBIAS2_IMIN_SLCD2C_BITS                        1
#define RX1_RX_ANALOGBIAS2_IMIN_SLCD2C_SHIFT                       3

/* RX1 :: Rx_analogBias2 :: imax_dfevref [02:02] */
#define RX1_RX_ANALOGBIAS2_IMAX_DFEVREF_MASK                       0x0004
#define RX1_RX_ANALOGBIAS2_IMAX_DFEVREF_ALIGN                      0
#define RX1_RX_ANALOGBIAS2_IMAX_DFEVREF_BITS                       1
#define RX1_RX_ANALOGBIAS2_IMAX_DFEVREF_SHIFT                      2

/* RX1 :: Rx_analogBias2 :: imode_dfevref [01:01] */
#define RX1_RX_ANALOGBIAS2_IMODE_DFEVREF_MASK                      0x0002
#define RX1_RX_ANALOGBIAS2_IMODE_DFEVREF_ALIGN                     0
#define RX1_RX_ANALOGBIAS2_IMODE_DFEVREF_BITS                      1
#define RX1_RX_ANALOGBIAS2_IMODE_DFEVREF_SHIFT                     1

/* RX1 :: Rx_analogBias2 :: imin_dfevref [00:00] */
#define RX1_RX_ANALOGBIAS2_IMIN_DFEVREF_MASK                       0x0001
#define RX1_RX_ANALOGBIAS2_IMIN_DFEVREF_ALIGN                      0
#define RX1_RX_ANALOGBIAS2_IMIN_DFEVREF_BITS                       1
#define RX1_RX_ANALOGBIAS2_IMIN_DFEVREF_SHIFT                      0


/****************************************************************************
 * XGXS16G_USER_RX2
 ***************************************************************************/
/****************************************************************************
 * RX2 :: Rx_Status
 ***************************************************************************/
/* union - case sigdet_Status [15:00] */
/* RX2 :: Rx_Status :: cx4_sigdet [15:15] */
#define RX2_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_MASK                0x8000
#define RX2_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_ALIGN               0
#define RX2_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_BITS                1
#define RX2_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_SHIFT               15

/* RX2 :: Rx_Status :: reserved0 [14:13] */
#define RX2_RX_STATUS_SIGDET_STATUS_RESERVED0_MASK                 0x6000
#define RX2_RX_STATUS_SIGDET_STATUS_RESERVED0_ALIGN                0
#define RX2_RX_STATUS_SIGDET_STATUS_RESERVED0_BITS                 2
#define RX2_RX_STATUS_SIGDET_STATUS_RESERVED0_SHIFT                13

/* RX2 :: Rx_Status :: rxSeqDone [12:12] */
#define RX2_RX_STATUS_SIGDET_STATUS_RXSEQDONE_MASK                 0x1000
#define RX2_RX_STATUS_SIGDET_STATUS_RXSEQDONE_ALIGN                0
#define RX2_RX_STATUS_SIGDET_STATUS_RXSEQDONE_BITS                 1
#define RX2_RX_STATUS_SIGDET_STATUS_RXSEQDONE_SHIFT                12

/* RX2 :: Rx_Status :: rx_sigdet_ll [11:11] */
#define RX2_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_MASK              0x0800
#define RX2_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_ALIGN             0
#define RX2_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_BITS              1
#define RX2_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_SHIFT             11

/* RX2 :: Rx_Status :: cs4_sigdet_ll [10:10] */
#define RX2_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_MASK             0x0400
#define RX2_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_ALIGN            0
#define RX2_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_BITS             1
#define RX2_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_SHIFT            10

/* RX2 :: Rx_Status :: rx_reset [09:09] */
#define RX2_RX_STATUS_SIGDET_STATUS_RX_RESET_MASK                  0x0200
#define RX2_RX_STATUS_SIGDET_STATUS_RX_RESET_ALIGN                 0
#define RX2_RX_STATUS_SIGDET_STATUS_RX_RESET_BITS                  1
#define RX2_RX_STATUS_SIGDET_STATUS_RX_RESET_SHIFT                 9

/* RX2 :: Rx_Status :: rx_pwrdn [08:08] */
#define RX2_RX_STATUS_SIGDET_STATUS_RX_PWRDN_MASK                  0x0100
#define RX2_RX_STATUS_SIGDET_STATUS_RX_PWRDN_ALIGN                 0
#define RX2_RX_STATUS_SIGDET_STATUS_RX_PWRDN_BITS                  1
#define RX2_RX_STATUS_SIGDET_STATUS_RX_PWRDN_SHIFT                 8

/* RX2 :: Rx_Status :: reserved1 [07:00] */
#define RX2_RX_STATUS_SIGDET_STATUS_RESERVED1_MASK                 0x00ff
#define RX2_RX_STATUS_SIGDET_STATUS_RESERVED1_ALIGN                0
#define RX2_RX_STATUS_SIGDET_STATUS_RESERVED1_BITS                 8
#define RX2_RX_STATUS_SIGDET_STATUS_RESERVED1_SHIFT                0


/* union - case sync_Status [15:00] */
/* RX2 :: Rx_Status :: reserved0 [15:11] */
#define RX2_RX_STATUS_SYNC_STATUS_RESERVED0_MASK                   0xf800
#define RX2_RX_STATUS_SYNC_STATUS_RESERVED0_ALIGN                  0
#define RX2_RX_STATUS_SYNC_STATUS_RESERVED0_BITS                   5
#define RX2_RX_STATUS_SYNC_STATUS_RESERVED0_SHIFT                  11

/* RX2 :: Rx_Status :: test_acq_en [10:10] */
#define RX2_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_MASK                 0x0400
#define RX2_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_ALIGN                0
#define RX2_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_BITS                 1
#define RX2_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_SHIFT                10

/* RX2 :: Rx_Status :: reserved1 [09:09] */
#define RX2_RX_STATUS_SYNC_STATUS_RESERVED1_MASK                   0x0200
#define RX2_RX_STATUS_SYNC_STATUS_RESERVED1_ALIGN                  0
#define RX2_RX_STATUS_SYNC_STATUS_RESERVED1_BITS                   1
#define RX2_RX_STATUS_SYNC_STATUS_RESERVED1_SHIFT                  9

/* RX2 :: Rx_Status :: rxSeqStart [08:08] */
#define RX2_RX_STATUS_SYNC_STATUS_RXSEQSTART_MASK                  0x0100
#define RX2_RX_STATUS_SYNC_STATUS_RXSEQSTART_ALIGN                 0
#define RX2_RX_STATUS_SYNC_STATUS_RXSEQSTART_BITS                  1
#define RX2_RX_STATUS_SYNC_STATUS_RXSEQSTART_SHIFT                 8

/* RX2 :: Rx_Status :: mux_comadj_sync_status [07:07] */
#define RX2_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_MASK      0x0080
#define RX2_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_ALIGN     0
#define RX2_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_BITS      1
#define RX2_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_SHIFT     7

/* RX2 :: Rx_Status :: sync_status [06:06] */
#define RX2_RX_STATUS_SYNC_STATUS_SYNC_STATUS_MASK                 0x0040
#define RX2_RX_STATUS_SYNC_STATUS_SYNC_STATUS_ALIGN                0
#define RX2_RX_STATUS_SYNC_STATUS_SYNC_STATUS_BITS                 1
#define RX2_RX_STATUS_SYNC_STATUS_SYNC_STATUS_SHIFT                6

/* RX2 :: Rx_Status :: rx_sigdet [05:05] */
#define RX2_RX_STATUS_SYNC_STATUS_RX_SIGDET_MASK                   0x0020
#define RX2_RX_STATUS_SYNC_STATUS_RX_SIGDET_ALIGN                  0
#define RX2_RX_STATUS_SYNC_STATUS_RX_SIGDET_BITS                   1
#define RX2_RX_STATUS_SYNC_STATUS_RX_SIGDET_SHIFT                  5

/* RX2 :: Rx_Status :: reserved2 [04:03] */
#define RX2_RX_STATUS_SYNC_STATUS_RESERVED2_MASK                   0x0018
#define RX2_RX_STATUS_SYNC_STATUS_RESERVED2_ALIGN                  0
#define RX2_RX_STATUS_SYNC_STATUS_RESERVED2_BITS                   2
#define RX2_RX_STATUS_SYNC_STATUS_RESERVED2_SHIFT                  3

/* RX2 :: Rx_Status :: saturate_status [02:02] */
#define RX2_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_MASK             0x0004
#define RX2_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_ALIGN            0
#define RX2_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_BITS             1
#define RX2_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_SHIFT            2

/* RX2 :: Rx_Status :: cx4_sigdet [01:01] */
#define RX2_RX_STATUS_SYNC_STATUS_CX4_SIGDET_MASK                  0x0002
#define RX2_RX_STATUS_SYNC_STATUS_CX4_SIGDET_ALIGN                 0
#define RX2_RX_STATUS_SYNC_STATUS_CX4_SIGDET_BITS                  1
#define RX2_RX_STATUS_SYNC_STATUS_CX4_SIGDET_SHIFT                 1

/* RX2 :: Rx_Status :: rxSeqDone [00:00] */
#define RX2_RX_STATUS_SYNC_STATUS_RXSEQDONE_MASK                   0x0001
#define RX2_RX_STATUS_SYNC_STATUS_RXSEQDONE_ALIGN                  0
#define RX2_RX_STATUS_SYNC_STATUS_RXSEQDONE_BITS                   1
#define RX2_RX_STATUS_SYNC_STATUS_RXSEQDONE_SHIFT                  0


/* union - case rxTestSel_0 [15:00] */
/* RX2 :: Rx_Status :: reserved0 [15:10] */
#define RX2_RX_STATUS_RXTESTSEL_0_RESERVED0_MASK                   0xfc00
#define RX2_RX_STATUS_RXTESTSEL_0_RESERVED0_ALIGN                  0
#define RX2_RX_STATUS_RXTESTSEL_0_RESERVED0_BITS                   6
#define RX2_RX_STATUS_RXTESTSEL_0_RESERVED0_SHIFT                  10

/* RX2 :: Rx_Status :: indck_mode_en [09:09] */
#define RX2_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_MASK               0x0200
#define RX2_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_ALIGN              0
#define RX2_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_BITS               1
#define RX2_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_SHIFT              9

/* RX2 :: Rx_Status :: pci_mode_en [08:08] */
#define RX2_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_MASK                 0x0100
#define RX2_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_ALIGN                0
#define RX2_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_BITS                 1
#define RX2_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_SHIFT                8

/* RX2 :: Rx_Status :: rx_polarity [07:07] */
#define RX2_RX_STATUS_RXTESTSEL_0_RX_POLARITY_MASK                 0x0080
#define RX2_RX_STATUS_RXTESTSEL_0_RX_POLARITY_ALIGN                0
#define RX2_RX_STATUS_RXTESTSEL_0_RX_POLARITY_BITS                 1
#define RX2_RX_STATUS_RXTESTSEL_0_RX_POLARITY_SHIFT                7

/* RX2 :: Rx_Status :: rxpol_flip [06:06] */
#define RX2_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_MASK                  0x0040
#define RX2_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_ALIGN                 0
#define RX2_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_BITS                  1
#define RX2_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_SHIFT                 6

/* RX2 :: Rx_Status :: comma_mask [05:05] */
#define RX2_RX_STATUS_RXTESTSEL_0_COMMA_MASK_MASK                  0x0020
#define RX2_RX_STATUS_RXTESTSEL_0_COMMA_MASK_ALIGN                 0
#define RX2_RX_STATUS_RXTESTSEL_0_COMMA_MASK_BITS                  1
#define RX2_RX_STATUS_RXTESTSEL_0_COMMA_MASK_SHIFT                 5

/* RX2 :: Rx_Status :: link_en_r [04:04] */
#define RX2_RX_STATUS_RXTESTSEL_0_LINK_EN_R_MASK                   0x0010
#define RX2_RX_STATUS_RXTESTSEL_0_LINK_EN_R_ALIGN                  0
#define RX2_RX_STATUS_RXTESTSEL_0_LINK_EN_R_BITS                   1
#define RX2_RX_STATUS_RXTESTSEL_0_LINK_EN_R_SHIFT                  4

/* RX2 :: Rx_Status :: comma_adj_en [03:03] */
#define RX2_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_MASK                0x0008
#define RX2_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_ALIGN               0
#define RX2_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_BITS                1
#define RX2_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_SHIFT               3

/* RX2 :: Rx_Status :: comma_adj_en_ext [02:02] */
#define RX2_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_MASK            0x0004
#define RX2_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_ALIGN           0
#define RX2_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_BITS            1
#define RX2_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_SHIFT           2

/* RX2 :: Rx_Status :: reserved1 [01:00] */
#define RX2_RX_STATUS_RXTESTSEL_0_RESERVED1_MASK                   0x0003
#define RX2_RX_STATUS_RXTESTSEL_0_RESERVED1_ALIGN                  0
#define RX2_RX_STATUS_RXTESTSEL_0_RESERVED1_BITS                   2
#define RX2_RX_STATUS_RXTESTSEL_0_RESERVED1_SHIFT                  0


/* union - case rxTestSel_1 [15:00] */
/* RX2 :: Rx_Status :: reserved0 [15:05] */
#define RX2_RX_STATUS_RXTESTSEL_1_RESERVED0_MASK                   0xffe0
#define RX2_RX_STATUS_RXTESTSEL_1_RESERVED0_ALIGN                  0
#define RX2_RX_STATUS_RXTESTSEL_1_RESERVED0_BITS                   11
#define RX2_RX_STATUS_RXTESTSEL_1_RESERVED0_SHIFT                  5

/* RX2 :: Rx_Status :: cdrAcqDone_r2 [04:04] */
#define RX2_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_MASK               0x0010
#define RX2_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_ALIGN              0
#define RX2_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_BITS               1
#define RX2_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_SHIFT              4

/* RX2 :: Rx_Status :: freq_sel_PC [03:03] */
#define RX2_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_MASK                 0x0008
#define RX2_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_ALIGN                0
#define RX2_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_BITS                 1
#define RX2_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_SHIFT                3

/* RX2 :: Rx_Status :: freq_sel_SM [02:02] */
#define RX2_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_MASK                 0x0004
#define RX2_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_ALIGN                0
#define RX2_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_BITS                 1
#define RX2_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_SHIFT                2

/* RX2 :: Rx_Status :: integ_mode_SM [01:00] */
#define RX2_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_MASK               0x0003
#define RX2_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_ALIGN              0
#define RX2_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_BITS               2
#define RX2_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_SHIFT              0


/* union - case scale_Status [15:00] */
/* RX2 :: Rx_Status :: prop_scale [15:12] */
#define RX2_RX_STATUS_SCALE_STATUS_PROP_SCALE_MASK                 0xf000
#define RX2_RX_STATUS_SCALE_STATUS_PROP_SCALE_ALIGN                0
#define RX2_RX_STATUS_SCALE_STATUS_PROP_SCALE_BITS                 4
#define RX2_RX_STATUS_SCALE_STATUS_PROP_SCALE_SHIFT                12

/* RX2 :: Rx_Status :: integ_scale [11:08] */
#define RX2_RX_STATUS_SCALE_STATUS_INTEG_SCALE_MASK                0x0f00
#define RX2_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ALIGN               0
#define RX2_RX_STATUS_SCALE_STATUS_INTEG_SCALE_BITS                4
#define RX2_RX_STATUS_SCALE_STATUS_INTEG_SCALE_SHIFT               8

/* RX2 :: Rx_Status :: prop_scale_acq [07:04] */
#define RX2_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_MASK             0x00f0
#define RX2_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_ALIGN            0
#define RX2_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_BITS             4
#define RX2_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_SHIFT            4

/* RX2 :: Rx_Status :: integ_scale_acq [03:00] */
#define RX2_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_MASK            0x000f
#define RX2_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_ALIGN           0
#define RX2_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_BITS            4
#define RX2_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_SHIFT           0


/* union - case adc_CdrStatus1 [15:00] */
/* RX2 :: Rx_Status :: reserved0 [15:07] */
#define RX2_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_MASK                0xff80
#define RX2_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_ALIGN               0
#define RX2_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_BITS                9
#define RX2_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_SHIFT               7

/* RX2 :: Rx_Status :: rxMuxCkSel [06:06] */
#define RX2_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_MASK               0x0040
#define RX2_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_ALIGN              0
#define RX2_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_BITS               1
#define RX2_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_SHIFT              6

/* RX2 :: Rx_Status :: glpbk_combo [05:05] */
#define RX2_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_MASK              0x0020
#define RX2_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_ALIGN             0
#define RX2_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_BITS              1
#define RX2_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_SHIFT             5

/* RX2 :: Rx_Status :: clockSwitchSel [04:04] */
#define RX2_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_MASK           0x0010
#define RX2_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_ALIGN          0
#define RX2_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_BITS           1
#define RX2_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_SHIFT          4

/* RX2 :: Rx_Status :: rxck_tst [03:03] */
#define RX2_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_MASK                 0x0008
#define RX2_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_ALIGN                0
#define RX2_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_BITS                 1
#define RX2_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_SHIFT                3

/* RX2 :: Rx_Status :: rxck_i [02:02] */
#define RX2_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_MASK                   0x0004
#define RX2_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_ALIGN                  0
#define RX2_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_BITS                   1
#define RX2_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_SHIFT                  2

/* RX2 :: Rx_Status :: refclk [01:01] */
#define RX2_RX_STATUS_ADC_CDRSTATUS1_REFCLK_MASK                   0x0002
#define RX2_RX_STATUS_ADC_CDRSTATUS1_REFCLK_ALIGN                  0
#define RX2_RX_STATUS_ADC_CDRSTATUS1_REFCLK_BITS                   1
#define RX2_RX_STATUS_ADC_CDRSTATUS1_REFCLK_SHIFT                  1

/* RX2 :: Rx_Status :: pll_bypass [00:00] */
#define RX2_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_MASK               0x0001
#define RX2_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_ALIGN              0
#define RX2_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_BITS               1
#define RX2_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_SHIFT              0


/* union - case adc_CdrStatus2 [15:00] */
/* RX2 :: Rx_Status :: reserved0 [15:06] */
#define RX2_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_MASK                0xffc0
#define RX2_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_ALIGN               0
#define RX2_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_BITS                10
#define RX2_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_SHIFT               6

/* RX2 :: Rx_Status :: rxMuxCkSel [05:05] */
#define RX2_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_MASK               0x0020
#define RX2_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_ALIGN              0
#define RX2_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_BITS               1
#define RX2_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_SHIFT              5

/* RX2 :: Rx_Status :: rxSeqStart [04:04] */
#define RX2_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_MASK               0x0010
#define RX2_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_ALIGN              0
#define RX2_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_BITS               1
#define RX2_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_SHIFT              4

/* RX2 :: Rx_Status :: reserved1 [03:01] */
#define RX2_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_MASK                0x000e
#define RX2_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_ALIGN               0
#define RX2_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_BITS                3
#define RX2_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_SHIFT               1

/* RX2 :: Rx_Status :: rxSeqDone [00:00] */
#define RX2_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_MASK                0x0001
#define RX2_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_ALIGN               0
#define RX2_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_BITS                1
#define RX2_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_SHIFT               0


/* union - case adc_CdrStatus3 [15:00] */
/* RX2 :: Rx_Status :: reserved0 [15:04] */
#define RX2_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_MASK                0xfff0
#define RX2_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_ALIGN               0
#define RX2_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_BITS                12
#define RX2_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_SHIFT               4

/* RX2 :: Rx_Status :: rxSeqStart [03:03] */
#define RX2_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_MASK               0x0008
#define RX2_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_ALIGN              0
#define RX2_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_BITS               1
#define RX2_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_SHIFT              3

/* RX2 :: Rx_Status :: reserved1 [02:01] */
#define RX2_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_MASK                0x0006
#define RX2_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_ALIGN               0
#define RX2_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_BITS                2
#define RX2_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_SHIFT               1

/* RX2 :: Rx_Status :: allow_increment_PC [00:00] */
#define RX2_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_MASK       0x0001
#define RX2_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_ALIGN      0
#define RX2_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_BITS       1
#define RX2_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_SHIFT      0


/* union - case adc_CdrStatus4 [15:00] */
/* RX2 :: Rx_Status :: reserved0 [15:08] */
#define RX2_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_MASK                0xff00
#define RX2_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_ALIGN               0
#define RX2_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_BITS                8
#define RX2_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_SHIFT               8

/* RX2 :: Rx_Status :: rx_pwrdn [07:07] */
#define RX2_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_MASK                 0x0080
#define RX2_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_ALIGN                0
#define RX2_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_BITS                 1
#define RX2_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_SHIFT                7

/* RX2 :: Rx_Status :: freq_sel [06:06] */
#define RX2_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_MASK                 0x0040
#define RX2_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_ALIGN                0
#define RX2_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_BITS                 1
#define RX2_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_SHIFT                6

/* RX2 :: Rx_Status :: pll_lock_rstb [05:05] */
#define RX2_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_MASK            0x0020
#define RX2_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_ALIGN           0
#define RX2_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_BITS            1
#define RX2_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_SHIFT           5

/* RX2 :: Rx_Status :: pwrdn [04:04] */
#define RX2_RX_STATUS_ADC_CDRSTATUS4_PWRDN_MASK                    0x0010
#define RX2_RX_STATUS_ADC_CDRSTATUS4_PWRDN_ALIGN                   0
#define RX2_RX_STATUS_ADC_CDRSTATUS4_PWRDN_BITS                    1
#define RX2_RX_STATUS_ADC_CDRSTATUS4_PWRDN_SHIFT                   4

/* RX2 :: Rx_Status :: reserved1 [03:00] */
#define RX2_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_MASK                0x000f
#define RX2_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_ALIGN               0
#define RX2_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_BITS                4
#define RX2_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_SHIFT               0


/* union - case adc_CdrStatus5 [15:00] */
/* RX2 :: Rx_Status :: reserved0 [15:00] */
#define RX2_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_MASK                0xffff
#define RX2_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_ALIGN               0
#define RX2_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_BITS                16
#define RX2_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_SHIFT               0


/* union - case adc_CdrStatus6 [15:00] */
/* RX2 :: Rx_Status :: reserved0 [15:05] */
#define RX2_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_MASK                0xffe0
#define RX2_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_ALIGN               0
#define RX2_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_BITS                11
#define RX2_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_SHIFT               5

/* RX2 :: Rx_Status :: rx_reset [04:04] */
#define RX2_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_MASK                 0x0010
#define RX2_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_ALIGN                0
#define RX2_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_BITS                 1
#define RX2_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_SHIFT                4

/* RX2 :: Rx_Status :: rx_pwrdn [03:03] */
#define RX2_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_MASK                 0x0008
#define RX2_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_ALIGN                0
#define RX2_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_BITS                 1
#define RX2_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_SHIFT                3

/* RX2 :: Rx_Status :: reset_anlg [02:02] */
#define RX2_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_MASK               0x0004
#define RX2_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_ALIGN              0
#define RX2_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_BITS               1
#define RX2_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_SHIFT              2

/* RX2 :: Rx_Status :: pwrdn_rx [01:01] */
#define RX2_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_MASK                 0x0002
#define RX2_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_ALIGN                0
#define RX2_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_BITS                 1
#define RX2_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_SHIFT                1

/* RX2 :: Rx_Status :: pwrdn_pll [00:00] */
#define RX2_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_MASK                0x0001
#define RX2_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_ALIGN               0
#define RX2_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_BITS                1
#define RX2_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_SHIFT               0


/* union - case adc_CdrStatus7e [15:00] */
/* RX2 :: Rx_Status :: reserved0 [15:05] */
#define RX2_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_MASK               0xffe0
#define RX2_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_ALIGN              0
#define RX2_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_BITS               11
#define RX2_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_SHIFT              5

/* RX2 :: Rx_Status :: rxck0_even [04:04] */
#define RX2_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_MASK              0x0010
#define RX2_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_ALIGN             0
#define RX2_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_BITS              1
#define RX2_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_SHIFT             4

/* RX2 :: Rx_Status :: rxck1_even [03:03] */
#define RX2_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_MASK              0x0008
#define RX2_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_ALIGN             0
#define RX2_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_BITS              1
#define RX2_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_SHIFT             3

/* RX2 :: Rx_Status :: comdet_even [02:02] */
#define RX2_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_MASK             0x0004
#define RX2_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_ALIGN            0
#define RX2_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_BITS             1
#define RX2_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_SHIFT            2

/* RX2 :: Rx_Status :: en_cdet_even [01:01] */
#define RX2_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_MASK            0x0002
#define RX2_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_ALIGN           0
#define RX2_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_BITS            1
#define RX2_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_SHIFT           1

/* RX2 :: Rx_Status :: comma_adj_en_even [00:00] */
#define RX2_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_MASK       0x0001
#define RX2_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_ALIGN      0
#define RX2_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_BITS       1
#define RX2_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_SHIFT      0


/* union - case adc_CdrStatus7o [15:00] */
/* RX2 :: Rx_Status :: reserved0 [15:05] */
#define RX2_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_MASK               0xffe0
#define RX2_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_ALIGN              0
#define RX2_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_BITS               11
#define RX2_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_SHIFT              5

/* RX2 :: Rx_Status :: rxck0_odd [04:04] */
#define RX2_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_MASK               0x0010
#define RX2_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_ALIGN              0
#define RX2_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_BITS               1
#define RX2_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_SHIFT              4

/* RX2 :: Rx_Status :: rxck1_odd [03:03] */
#define RX2_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_MASK               0x0008
#define RX2_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_ALIGN              0
#define RX2_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_BITS               1
#define RX2_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_SHIFT              3

/* RX2 :: Rx_Status :: comdet_odd [02:02] */
#define RX2_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_MASK              0x0004
#define RX2_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_ALIGN             0
#define RX2_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_BITS              1
#define RX2_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_SHIFT             2

/* RX2 :: Rx_Status :: en_cdet_odd [01:01] */
#define RX2_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_MASK             0x0002
#define RX2_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_ALIGN            0
#define RX2_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_BITS             1
#define RX2_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_SHIFT            1

/* RX2 :: Rx_Status :: comma_adj_en_odd [00:00] */
#define RX2_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_MASK        0x0001
#define RX2_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_ALIGN       0
#define RX2_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_BITS        1
#define RX2_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_SHIFT       0


/* union - case adc_CdrStatus8 [15:00] */
/* RX2 :: Rx_Status :: reserved0 [15:01] */
#define RX2_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_MASK                0xfffe
#define RX2_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_ALIGN               0
#define RX2_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_BITS                15
#define RX2_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_SHIFT               1

/* RX2 :: Rx_Status :: sigdet [00:00] */
#define RX2_RX_STATUS_ADC_CDRSTATUS8_SIGDET_MASK                   0x0001
#define RX2_RX_STATUS_ADC_CDRSTATUS8_SIGDET_ALIGN                  0
#define RX2_RX_STATUS_ADC_CDRSTATUS8_SIGDET_BITS                   1
#define RX2_RX_STATUS_ADC_CDRSTATUS8_SIGDET_SHIFT                  0


/* union - case adc_CdrStatus9 [15:00] */
/* RX2 :: Rx_Status :: reserved0 [15:00] */
#define RX2_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_MASK                0xffff
#define RX2_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_ALIGN               0
#define RX2_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_BITS                16
#define RX2_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_SHIFT               0


/* union - case adc_CdrStatus10 [15:00] */
/* RX2 :: Rx_Status :: reserved0 [15:07] */
#define RX2_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_MASK               0xff80
#define RX2_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_ALIGN              0
#define RX2_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_BITS               9
#define RX2_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_SHIFT              7

/* RX2 :: Rx_Status :: prbs_en [06:06] */
#define RX2_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_MASK                 0x0040
#define RX2_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_ALIGN                0
#define RX2_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_BITS                 1
#define RX2_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_SHIFT                6

/* RX2 :: Rx_Status :: rstb_tst [05:05] */
#define RX2_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_MASK                0x0020
#define RX2_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_ALIGN               0
#define RX2_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_BITS                1
#define RX2_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_SHIFT               5

/* RX2 :: Rx_Status :: reserved1 [04:04] */
#define RX2_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_MASK               0x0010
#define RX2_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_ALIGN              0
#define RX2_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_BITS               1
#define RX2_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_SHIFT              4

/* RX2 :: Rx_Status :: prbs_state [03:00] */
#define RX2_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_MASK              0x000f
#define RX2_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_ALIGN             0
#define RX2_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_BITS              4
#define RX2_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_SHIFT             0


/* union - case adc_CdrStatus11 [15:00] */
/* RX2 :: Rx_Status :: reserved0 [15:00] */
#define RX2_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_MASK               0xffff
#define RX2_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_ALIGN              0
#define RX2_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_BITS               16
#define RX2_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_SHIFT              0


/* union - case adc_CdrStatus12_1 [15:00] */
/* RX2 :: Rx_Status :: reserved0 [15:06] */
#define RX2_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_MASK             0xffc0
#define RX2_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_ALIGN            0
#define RX2_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_BITS             10
#define RX2_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_SHIFT            6

/* RX2 :: Rx_Status :: enable4 [05:05] */
#define RX2_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_MASK               0x0020
#define RX2_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_ALIGN              0
#define RX2_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_BITS               1
#define RX2_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_SHIFT              5

/* RX2 :: Rx_Status :: radr_test [04:00] */
#define RX2_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_MASK             0x001f
#define RX2_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_ALIGN            0
#define RX2_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_BITS             5
#define RX2_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_SHIFT            0


/* union - case adc_CdrStatus12_2 [15:00] */
/* RX2 :: Rx_Status :: reserved0 [15:05] */
#define RX2_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_MASK             0xffe0
#define RX2_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_ALIGN            0
#define RX2_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_BITS             11
#define RX2_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_SHIFT            5

/* RX2 :: Rx_Status :: wadr_test [04:00] */
#define RX2_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_MASK             0x001f
#define RX2_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_ALIGN            0
#define RX2_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_BITS             5
#define RX2_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_SHIFT            0


/* union - case adc_CdrStatus12_3 [15:00] */
/* RX2 :: Rx_Status :: reserved0 [15:06] */
#define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_MASK             0xffc0
#define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_ALIGN            0
#define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_BITS             10
#define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_SHIFT            6

/* RX2 :: Rx_Status :: rxck_66B_tmux [05:05] */
#define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_MASK         0x0020
#define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_ALIGN        0
#define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_BITS         1
#define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_SHIFT        5

/* RX2 :: Rx_Status :: rstb_66B [04:04] */
#define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_MASK              0x0010
#define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_ALIGN             0
#define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_BITS              1
#define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_SHIFT             4

/* RX2 :: Rx_Status :: prstb_66B_mux [03:03] */
#define RX2_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_MASK         0x0008
#define RX2_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_ALIGN        0
#define RX2_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_BITS         1
#define RX2_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_SHIFT        3

/* RX2 :: Rx_Status :: rxck_i66_tmux [02:02] */
#define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_MASK         0x0004
#define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_ALIGN        0
#define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_BITS         1
#define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_SHIFT        2

/* RX2 :: Rx_Status :: rstb_i66 [01:01] */
#define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_MASK              0x0002
#define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_ALIGN             0
#define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_BITS              1
#define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_SHIFT             1

/* RX2 :: Rx_Status :: prstb_i66_mux [00:00] */
#define RX2_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_MASK         0x0001
#define RX2_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_ALIGN        0
#define RX2_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_BITS         1
#define RX2_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_SHIFT        0


/* union - case adc_CdrStatus12_4 [15:00] */
/* RX2 :: Rx_Status :: reserved0 [15:04] */
#define RX2_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_MASK             0xfff0
#define RX2_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_ALIGN            0
#define RX2_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_BITS             12
#define RX2_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_SHIFT            4

/* RX2 :: Rx_Status :: rfifo_error_r [03:02] */
#define RX2_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_MASK         0x000c
#define RX2_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_ALIGN        0
#define RX2_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_BITS         2
#define RX2_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_SHIFT        2

/* RX2 :: Rx_Status :: rfifo_unflow [01:01] */
#define RX2_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_MASK          0x0002
#define RX2_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_ALIGN         0
#define RX2_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_BITS          1
#define RX2_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_SHIFT         1

/* RX2 :: Rx_Status :: rfifo_ovflow [00:00] */
#define RX2_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_MASK          0x0001
#define RX2_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_ALIGN         0
#define RX2_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_BITS          1
#define RX2_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_SHIFT         0


/* union - case integ_Status [15:00] */
/* RX2 :: Rx_Status :: integ_status [15:00] */
#define RX2_RX_STATUS_INTEG_STATUS_INTEG_STATUS_MASK               0xffff
#define RX2_RX_STATUS_INTEG_STATUS_INTEG_STATUS_ALIGN              0
#define RX2_RX_STATUS_INTEG_STATUS_INTEG_STATUS_BITS               16
#define RX2_RX_STATUS_INTEG_STATUS_INTEG_STATUS_SHIFT              0


/* union - case vco_Status [15:00] */
/* RX2 :: Rx_Status :: vco_status [15:00] */
#define RX2_RX_STATUS_VCO_STATUS_VCO_STATUS_MASK                   0xffff
#define RX2_RX_STATUS_VCO_STATUS_VCO_STATUS_ALIGN                  0
#define RX2_RX_STATUS_VCO_STATUS_VCO_STATUS_BITS                   16
#define RX2_RX_STATUS_VCO_STATUS_VCO_STATUS_SHIFT                  0


/* union - case prbs_Status [15:00] */
/* RX2 :: Rx_Status :: prbs_lock [15:15] */
#define RX2_RX_STATUS_PRBS_STATUS_PRBS_LOCK_MASK                   0x8000
#define RX2_RX_STATUS_PRBS_STATUS_PRBS_LOCK_ALIGN                  0
#define RX2_RX_STATUS_PRBS_STATUS_PRBS_LOCK_BITS                   1
#define RX2_RX_STATUS_PRBS_STATUS_PRBS_LOCK_SHIFT                  15

/* RX2 :: Rx_Status :: prbs_stky [14:14] */
#define RX2_RX_STATUS_PRBS_STATUS_PRBS_STKY_MASK                   0x4000
#define RX2_RX_STATUS_PRBS_STATUS_PRBS_STKY_ALIGN                  0
#define RX2_RX_STATUS_PRBS_STATUS_PRBS_STKY_BITS                   1
#define RX2_RX_STATUS_PRBS_STATUS_PRBS_STKY_SHIFT                  14

/* RX2 :: Rx_Status :: ptbs_errors [13:00] */
#define RX2_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_MASK                 0x3fff
#define RX2_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_ALIGN                0
#define RX2_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_BITS                 14
#define RX2_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_SHIFT                0



/****************************************************************************
 * RX2 :: Rx_Control
 ***************************************************************************/
/* RX2 :: Rx_Control :: reserved0 [15:03] */
#define RX2_RX_CONTROL_RESERVED0_MASK                              0xfff8
#define RX2_RX_CONTROL_RESERVED0_ALIGN                             0
#define RX2_RX_CONTROL_RESERVED0_BITS                              13
#define RX2_RX_CONTROL_RESERVED0_SHIFT                             3

/* RX2 :: Rx_Control :: status_sel [02:00] */
#define RX2_RX_CONTROL_STATUS_SEL_MASK                             0x0007
#define RX2_RX_CONTROL_STATUS_SEL_ALIGN                            0
#define RX2_RX_CONTROL_STATUS_SEL_BITS                             3
#define RX2_RX_CONTROL_STATUS_SEL_SHIFT                            0
#define RX2_RX_CONTROL_STATUS_SEL_sigdetStatus                     0
#define RX2_RX_CONTROL_STATUS_SEL_syncStatus                       1
#define RX2_RX_CONTROL_STATUS_SEL_rxTestSel                        2
#define RX2_RX_CONTROL_STATUS_SEL_scaleStatus                      3
#define RX2_RX_CONTROL_STATUS_SEL_adcCdrStatus                     4
#define RX2_RX_CONTROL_STATUS_SEL_integStatus                      5
#define RX2_RX_CONTROL_STATUS_SEL_vcoStatus                        6
#define RX2_RX_CONTROL_STATUS_SEL_prbsStatus                       7


/****************************************************************************
 * RX2 :: Rx_Test
 ***************************************************************************/
/* RX2 :: Rx_Test :: sigdet_mux_SM [15:12] */
#define RX2_RX_TEST_SIGDET_MUX_SM_MASK                             0xf000
#define RX2_RX_TEST_SIGDET_MUX_SM_ALIGN                            0
#define RX2_RX_TEST_SIGDET_MUX_SM_BITS                             4
#define RX2_RX_TEST_SIGDET_MUX_SM_SHIFT                            12

/* RX2 :: Rx_Test :: reserved0 [11:09] */
#define RX2_RX_TEST_RESERVED0_MASK                                 0x0e00
#define RX2_RX_TEST_RESERVED0_ALIGN                                0
#define RX2_RX_TEST_RESERVED0_BITS                                 3
#define RX2_RX_TEST_RESERVED0_SHIFT                                9

/* RX2 :: Rx_Test :: tpctrl_SM [08:04] */
#define RX2_RX_TEST_TPCTRL_SM_MASK                                 0x01f0
#define RX2_RX_TEST_TPCTRL_SM_ALIGN                                0
#define RX2_RX_TEST_TPCTRL_SM_BITS                                 5
#define RX2_RX_TEST_TPCTRL_SM_SHIFT                                4

/* RX2 :: Rx_Test :: testMuxSelect_SM [03:00] */
#define RX2_RX_TEST_TESTMUXSELECT_SM_MASK                          0x000f
#define RX2_RX_TEST_TESTMUXSELECT_SM_ALIGN                         0
#define RX2_RX_TEST_TESTMUXSELECT_SM_BITS                          4
#define RX2_RX_TEST_TESTMUXSELECT_SM_SHIFT                         0


/****************************************************************************
 * RX2 :: Rx_Control_1G_type
 ***************************************************************************/
/* RX2 :: Rx_Control_1G_type :: fpat_md [15:15] */
#define RX2_RX_CONTROL_1G_TYPE_FPAT_MD_MASK                        0x8000
#define RX2_RX_CONTROL_1G_TYPE_FPAT_MD_ALIGN                       0
#define RX2_RX_CONTROL_1G_TYPE_FPAT_MD_BITS                        1
#define RX2_RX_CONTROL_1G_TYPE_FPAT_MD_SHIFT                       15

/* RX2 :: Rx_Control_1G_type :: pkt_count_en [14:14] */
#define RX2_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_MASK                   0x4000
#define RX2_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_ALIGN                  0
#define RX2_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_BITS                   1
#define RX2_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_SHIFT                  14

/* RX2 :: Rx_Control_1G_type :: staMuxRegDis [13:13] */
#define RX2_RX_CONTROL_1G_TYPE_STAMUXREGDIS_MASK                   0x2000
#define RX2_RX_CONTROL_1G_TYPE_STAMUXREGDIS_ALIGN                  0
#define RX2_RX_CONTROL_1G_TYPE_STAMUXREGDIS_BITS                   1
#define RX2_RX_CONTROL_1G_TYPE_STAMUXREGDIS_SHIFT                  13

/* RX2 :: Rx_Control_1G_type :: prbs_clr_dis [12:12] */
#define RX2_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_MASK                   0x1000
#define RX2_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_ALIGN                  0
#define RX2_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_BITS                   1
#define RX2_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_SHIFT                  12

/* RX2 :: Rx_Control_1G_type :: rxd_dec_sel [11:11] */
#define RX2_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_MASK                    0x0800
#define RX2_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_ALIGN                   0
#define RX2_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_BITS                    1
#define RX2_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_SHIFT                   11

/* RX2 :: Rx_Control_1G_type :: cgbad_tst [10:10] */
#define RX2_RX_CONTROL_1G_TYPE_CGBAD_TST_MASK                      0x0400
#define RX2_RX_CONTROL_1G_TYPE_CGBAD_TST_ALIGN                     0
#define RX2_RX_CONTROL_1G_TYPE_CGBAD_TST_BITS                      1
#define RX2_RX_CONTROL_1G_TYPE_CGBAD_TST_SHIFT                     10

/* RX2 :: Rx_Control_1G_type :: Emon_en [09:09] */
#define RX2_RX_CONTROL_1G_TYPE_EMON_EN_MASK                        0x0200
#define RX2_RX_CONTROL_1G_TYPE_EMON_EN_ALIGN                       0
#define RX2_RX_CONTROL_1G_TYPE_EMON_EN_BITS                        1
#define RX2_RX_CONTROL_1G_TYPE_EMON_EN_SHIFT                       9

/* RX2 :: Rx_Control_1G_type :: prbs_en [08:08] */
#define RX2_RX_CONTROL_1G_TYPE_PRBS_EN_MASK                        0x0100
#define RX2_RX_CONTROL_1G_TYPE_PRBS_EN_ALIGN                       0
#define RX2_RX_CONTROL_1G_TYPE_PRBS_EN_BITS                        1
#define RX2_RX_CONTROL_1G_TYPE_PRBS_EN_SHIFT                       8

/* RX2 :: Rx_Control_1G_type :: cgbad_en [07:07] */
#define RX2_RX_CONTROL_1G_TYPE_CGBAD_EN_MASK                       0x0080
#define RX2_RX_CONTROL_1G_TYPE_CGBAD_EN_ALIGN                      0
#define RX2_RX_CONTROL_1G_TYPE_CGBAD_EN_BITS                       1
#define RX2_RX_CONTROL_1G_TYPE_CGBAD_EN_SHIFT                      7

/* RX2 :: Rx_Control_1G_type :: cstretch [06:06] */
#define RX2_RX_CONTROL_1G_TYPE_CSTRETCH_MASK                       0x0040
#define RX2_RX_CONTROL_1G_TYPE_CSTRETCH_ALIGN                      0
#define RX2_RX_CONTROL_1G_TYPE_CSTRETCH_BITS                       1
#define RX2_RX_CONTROL_1G_TYPE_CSTRETCH_SHIFT                      6

/* RX2 :: Rx_Control_1G_type :: rtbi_ckflip [05:05] */
#define RX2_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_MASK                    0x0020
#define RX2_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_ALIGN                   0
#define RX2_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_BITS                    1
#define RX2_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_SHIFT                   5

/* RX2 :: Rx_Control_1G_type :: rtbi_flip [04:04] */
#define RX2_RX_CONTROL_1G_TYPE_RTBI_FLIP_MASK                      0x0010
#define RX2_RX_CONTROL_1G_TYPE_RTBI_FLIP_ALIGN                     0
#define RX2_RX_CONTROL_1G_TYPE_RTBI_FLIP_BITS                      1
#define RX2_RX_CONTROL_1G_TYPE_RTBI_FLIP_SHIFT                     4

/* RX2 :: Rx_Control_1G_type :: phase_sel [03:03] */
#define RX2_RX_CONTROL_1G_TYPE_PHASE_SEL_MASK                      0x0008
#define RX2_RX_CONTROL_1G_TYPE_PHASE_SEL_ALIGN                     0
#define RX2_RX_CONTROL_1G_TYPE_PHASE_SEL_BITS                      1
#define RX2_RX_CONTROL_1G_TYPE_PHASE_SEL_SHIFT                     3

/* RX2 :: Rx_Control_1G_type :: reserved0 [02:02] */
#define RX2_RX_CONTROL_1G_TYPE_RESERVED0_MASK                      0x0004
#define RX2_RX_CONTROL_1G_TYPE_RESERVED0_ALIGN                     0
#define RX2_RX_CONTROL_1G_TYPE_RESERVED0_BITS                      1
#define RX2_RX_CONTROL_1G_TYPE_RESERVED0_SHIFT                     2

/* RX2 :: Rx_Control_1G_type :: freq_sel_force [01:01] */
#define RX2_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_MASK                 0x0002
#define RX2_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_ALIGN                0
#define RX2_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_BITS                 1
#define RX2_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_SHIFT                1

/* RX2 :: Rx_Control_1G_type :: freq_sel [00:00] */
#define RX2_RX_CONTROL_1G_TYPE_FREQ_SEL_MASK                       0x0001
#define RX2_RX_CONTROL_1G_TYPE_FREQ_SEL_ALIGN                      0
#define RX2_RX_CONTROL_1G_TYPE_FREQ_SEL_BITS                       1
#define RX2_RX_CONTROL_1G_TYPE_FREQ_SEL_SHIFT                      0


/****************************************************************************
 * RX2 :: Rx_Astatus
 ***************************************************************************/
/* RX2 :: Rx_Astatus :: reserved0 [15:01] */
#define RX2_RX_ASTATUS_RESERVED0_MASK                              0xfffe
#define RX2_RX_ASTATUS_RESERVED0_ALIGN                             0
#define RX2_RX_ASTATUS_RESERVED0_BITS                              15
#define RX2_RX_ASTATUS_RESERVED0_SHIFT                             1

/* RX2 :: Rx_Astatus :: sigdet [00:00] */
#define RX2_RX_ASTATUS_SIGDET_MASK                                 0x0001
#define RX2_RX_ASTATUS_SIGDET_ALIGN                                0
#define RX2_RX_ASTATUS_SIGDET_BITS                                 1
#define RX2_RX_ASTATUS_SIGDET_SHIFT                                0


/****************************************************************************
 * RX2 :: Rx_analogBias0
 ***************************************************************************/
/* RX2 :: Rx_analogBias0 :: imode_vcm [15:15] */
#define RX2_RX_ANALOGBIAS0_IMODE_VCM_MASK                          0x8000
#define RX2_RX_ANALOGBIAS0_IMODE_VCM_ALIGN                         0
#define RX2_RX_ANALOGBIAS0_IMODE_VCM_BITS                          1
#define RX2_RX_ANALOGBIAS0_IMODE_VCM_SHIFT                         15

/* RX2 :: Rx_analogBias0 :: imin_vcm [14:14] */
#define RX2_RX_ANALOGBIAS0_IMIN_VCM_MASK                           0x4000
#define RX2_RX_ANALOGBIAS0_IMIN_VCM_ALIGN                          0
#define RX2_RX_ANALOGBIAS0_IMIN_VCM_BITS                           1
#define RX2_RX_ANALOGBIAS0_IMIN_VCM_SHIFT                          14

/* RX2 :: Rx_analogBias0 :: imax_sigdet [13:13] */
#define RX2_RX_ANALOGBIAS0_IMAX_SIGDET_MASK                        0x2000
#define RX2_RX_ANALOGBIAS0_IMAX_SIGDET_ALIGN                       0
#define RX2_RX_ANALOGBIAS0_IMAX_SIGDET_BITS                        1
#define RX2_RX_ANALOGBIAS0_IMAX_SIGDET_SHIFT                       13

/* RX2 :: Rx_analogBias0 :: imode_sigdet [12:12] */
#define RX2_RX_ANALOGBIAS0_IMODE_SIGDET_MASK                       0x1000
#define RX2_RX_ANALOGBIAS0_IMODE_SIGDET_ALIGN                      0
#define RX2_RX_ANALOGBIAS0_IMODE_SIGDET_BITS                       1
#define RX2_RX_ANALOGBIAS0_IMODE_SIGDET_SHIFT                      12

/* RX2 :: Rx_analogBias0 :: imin_sigdet [11:11] */
#define RX2_RX_ANALOGBIAS0_IMIN_SIGDET_MASK                        0x0800
#define RX2_RX_ANALOGBIAS0_IMIN_SIGDET_ALIGN                       0
#define RX2_RX_ANALOGBIAS0_IMIN_SIGDET_BITS                        1
#define RX2_RX_ANALOGBIAS0_IMIN_SIGDET_SHIFT                       11

/* RX2 :: Rx_analogBias0 :: refh_rx [10:10] */
#define RX2_RX_ANALOGBIAS0_REFH_RX_MASK                            0x0400
#define RX2_RX_ANALOGBIAS0_REFH_RX_ALIGN                           0
#define RX2_RX_ANALOGBIAS0_REFH_RX_BITS                            1
#define RX2_RX_ANALOGBIAS0_REFH_RX_SHIFT                           10

/* RX2 :: Rx_analogBias0 :: refl_rx [09:09] */
#define RX2_RX_ANALOGBIAS0_REFL_RX_MASK                            0x0200
#define RX2_RX_ANALOGBIAS0_REFL_RX_ALIGN                           0
#define RX2_RX_ANALOGBIAS0_REFL_RX_BITS                            1
#define RX2_RX_ANALOGBIAS0_REFL_RX_SHIFT                           9

/* RX2 :: Rx_analogBias0 :: tport_en [08:08] */
#define RX2_RX_ANALOGBIAS0_TPORT_EN_MASK                           0x0100
#define RX2_RX_ANALOGBIAS0_TPORT_EN_ALIGN                          0
#define RX2_RX_ANALOGBIAS0_TPORT_EN_BITS                           1
#define RX2_RX_ANALOGBIAS0_TPORT_EN_SHIFT                          8

/* RX2 :: Rx_analogBias0 :: vddr_bg [07:07] */
#define RX2_RX_ANALOGBIAS0_VDDR_BG_MASK                            0x0080
#define RX2_RX_ANALOGBIAS0_VDDR_BG_ALIGN                           0
#define RX2_RX_ANALOGBIAS0_VDDR_BG_BITS                            1
#define RX2_RX_ANALOGBIAS0_VDDR_BG_SHIFT                           7

/* RX2 :: Rx_analogBias0 :: sig_pwrdn [06:06] */
#define RX2_RX_ANALOGBIAS0_SIG_PWRDN_MASK                          0x0040
#define RX2_RX_ANALOGBIAS0_SIG_PWRDN_ALIGN                         0
#define RX2_RX_ANALOGBIAS0_SIG_PWRDN_BITS                          1
#define RX2_RX_ANALOGBIAS0_SIG_PWRDN_SHIFT                         6

/* RX2 :: Rx_analogBias0 :: offset_ctrl [05:03] */
#define RX2_RX_ANALOGBIAS0_OFFSET_CTRL_MASK                        0x0038
#define RX2_RX_ANALOGBIAS0_OFFSET_CTRL_ALIGN                       0
#define RX2_RX_ANALOGBIAS0_OFFSET_CTRL_BITS                        3
#define RX2_RX_ANALOGBIAS0_OFFSET_CTRL_SHIFT                       3

/* RX2 :: Rx_analogBias0 :: offset_sel [02:02] */
#define RX2_RX_ANALOGBIAS0_OFFSET_SEL_MASK                         0x0004
#define RX2_RX_ANALOGBIAS0_OFFSET_SEL_ALIGN                        0
#define RX2_RX_ANALOGBIAS0_OFFSET_SEL_BITS                         1
#define RX2_RX_ANALOGBIAS0_OFFSET_SEL_SHIFT                        2

/* RX2 :: Rx_analogBias0 :: reserved0 [01:00] */
#define RX2_RX_ANALOGBIAS0_RESERVED0_MASK                          0x0003
#define RX2_RX_ANALOGBIAS0_RESERVED0_ALIGN                         0
#define RX2_RX_ANALOGBIAS0_RESERVED0_BITS                          2
#define RX2_RX_ANALOGBIAS0_RESERVED0_SHIFT                         0


/****************************************************************************
 * RX2 :: Rx_analogBias1
 ***************************************************************************/
/* RX2 :: Rx_analogBias1 :: imax_clkbuf [15:15] */
#define RX2_RX_ANALOGBIAS1_IMAX_CLKBUF_MASK                        0x8000
#define RX2_RX_ANALOGBIAS1_IMAX_CLKBUF_ALIGN                       0
#define RX2_RX_ANALOGBIAS1_IMAX_CLKBUF_BITS                        1
#define RX2_RX_ANALOGBIAS1_IMAX_CLKBUF_SHIFT                       15

/* RX2 :: Rx_analogBias1 :: imode_clkbuf [14:14] */
#define RX2_RX_ANALOGBIAS1_IMODE_CLKBUF_MASK                       0x4000
#define RX2_RX_ANALOGBIAS1_IMODE_CLKBUF_ALIGN                      0
#define RX2_RX_ANALOGBIAS1_IMODE_CLKBUF_BITS                       1
#define RX2_RX_ANALOGBIAS1_IMODE_CLKBUF_SHIFT                      14

/* RX2 :: Rx_analogBias1 :: imin_clkbuf [13:13] */
#define RX2_RX_ANALOGBIAS1_IMIN_CLKBUF_MASK                        0x2000
#define RX2_RX_ANALOGBIAS1_IMIN_CLKBUF_ALIGN                       0
#define RX2_RX_ANALOGBIAS1_IMIN_CLKBUF_BITS                        1
#define RX2_RX_ANALOGBIAS1_IMIN_CLKBUF_SHIFT                       13

/* RX2 :: Rx_analogBias1 :: imax_eqfl [12:12] */
#define RX2_RX_ANALOGBIAS1_IMAX_EQFL_MASK                          0x1000
#define RX2_RX_ANALOGBIAS1_IMAX_EQFL_ALIGN                         0
#define RX2_RX_ANALOGBIAS1_IMAX_EQFL_BITS                          1
#define RX2_RX_ANALOGBIAS1_IMAX_EQFL_SHIFT                         12

/* RX2 :: Rx_analogBias1 :: imode_eqfl [11:11] */
#define RX2_RX_ANALOGBIAS1_IMODE_EQFL_MASK                         0x0800
#define RX2_RX_ANALOGBIAS1_IMODE_EQFL_ALIGN                        0
#define RX2_RX_ANALOGBIAS1_IMODE_EQFL_BITS                         1
#define RX2_RX_ANALOGBIAS1_IMODE_EQFL_SHIFT                        11

/* RX2 :: Rx_analogBias1 :: imin_eqfl [10:10] */
#define RX2_RX_ANALOGBIAS1_IMIN_EQFL_MASK                          0x0400
#define RX2_RX_ANALOGBIAS1_IMIN_EQFL_ALIGN                         0
#define RX2_RX_ANALOGBIAS1_IMIN_EQFL_BITS                          1
#define RX2_RX_ANALOGBIAS1_IMIN_EQFL_SHIFT                         10

/* RX2 :: Rx_analogBias1 :: imax_dfesum [09:09] */
#define RX2_RX_ANALOGBIAS1_IMAX_DFESUM_MASK                        0x0200
#define RX2_RX_ANALOGBIAS1_IMAX_DFESUM_ALIGN                       0
#define RX2_RX_ANALOGBIAS1_IMAX_DFESUM_BITS                        1
#define RX2_RX_ANALOGBIAS1_IMAX_DFESUM_SHIFT                       9

/* RX2 :: Rx_analogBias1 :: imode_dfesum [08:08] */
#define RX2_RX_ANALOGBIAS1_IMODE_DFESUM_MASK                       0x0100
#define RX2_RX_ANALOGBIAS1_IMODE_DFESUM_ALIGN                      0
#define RX2_RX_ANALOGBIAS1_IMODE_DFESUM_BITS                       1
#define RX2_RX_ANALOGBIAS1_IMODE_DFESUM_SHIFT                      8

/* RX2 :: Rx_analogBias1 :: imin_dfesum [07:07] */
#define RX2_RX_ANALOGBIAS1_IMIN_DFESUM_MASK                        0x0080
#define RX2_RX_ANALOGBIAS1_IMIN_DFESUM_ALIGN                       0
#define RX2_RX_ANALOGBIAS1_IMIN_DFESUM_BITS                        1
#define RX2_RX_ANALOGBIAS1_IMIN_DFESUM_SHIFT                       7

/* RX2 :: Rx_analogBias1 :: imax_vga [06:06] */
#define RX2_RX_ANALOGBIAS1_IMAX_VGA_MASK                           0x0040
#define RX2_RX_ANALOGBIAS1_IMAX_VGA_ALIGN                          0
#define RX2_RX_ANALOGBIAS1_IMAX_VGA_BITS                           1
#define RX2_RX_ANALOGBIAS1_IMAX_VGA_SHIFT                          6

/* RX2 :: Rx_analogBias1 :: imode_vga [05:05] */
#define RX2_RX_ANALOGBIAS1_IMODE_VGA_MASK                          0x0020
#define RX2_RX_ANALOGBIAS1_IMODE_VGA_ALIGN                         0
#define RX2_RX_ANALOGBIAS1_IMODE_VGA_BITS                          1
#define RX2_RX_ANALOGBIAS1_IMODE_VGA_SHIFT                         5

/* RX2 :: Rx_analogBias1 :: imin_vga [04:04] */
#define RX2_RX_ANALOGBIAS1_IMIN_VGA_MASK                           0x0010
#define RX2_RX_ANALOGBIAS1_IMIN_VGA_ALIGN                          0
#define RX2_RX_ANALOGBIAS1_IMIN_VGA_BITS                           1
#define RX2_RX_ANALOGBIAS1_IMIN_VGA_SHIFT                          4

/* RX2 :: Rx_analogBias1 :: imax_interp [03:03] */
#define RX2_RX_ANALOGBIAS1_IMAX_INTERP_MASK                        0x0008
#define RX2_RX_ANALOGBIAS1_IMAX_INTERP_ALIGN                       0
#define RX2_RX_ANALOGBIAS1_IMAX_INTERP_BITS                        1
#define RX2_RX_ANALOGBIAS1_IMAX_INTERP_SHIFT                       3

/* RX2 :: Rx_analogBias1 :: imode_interp [02:02] */
#define RX2_RX_ANALOGBIAS1_IMODE_INTERP_MASK                       0x0004
#define RX2_RX_ANALOGBIAS1_IMODE_INTERP_ALIGN                      0
#define RX2_RX_ANALOGBIAS1_IMODE_INTERP_BITS                       1
#define RX2_RX_ANALOGBIAS1_IMODE_INTERP_SHIFT                      2

/* RX2 :: Rx_analogBias1 :: imin_interp [01:01] */
#define RX2_RX_ANALOGBIAS1_IMIN_INTERP_MASK                        0x0002
#define RX2_RX_ANALOGBIAS1_IMIN_INTERP_ALIGN                       0
#define RX2_RX_ANALOGBIAS1_IMIN_INTERP_BITS                        1
#define RX2_RX_ANALOGBIAS1_IMIN_INTERP_SHIFT                       1

/* RX2 :: Rx_analogBias1 :: imax_vcm [00:00] */
#define RX2_RX_ANALOGBIAS1_IMAX_VCM_MASK                           0x0001
#define RX2_RX_ANALOGBIAS1_IMAX_VCM_ALIGN                          0
#define RX2_RX_ANALOGBIAS1_IMAX_VCM_BITS                           1
#define RX2_RX_ANALOGBIAS1_IMAX_VCM_SHIFT                          0


/****************************************************************************
 * RX2 :: Rx_analogBias2
 ***************************************************************************/
/* RX2 :: Rx_analogBias2 :: en_clk16 [15:15] */
#define RX2_RX_ANALOGBIAS2_EN_CLK16_MASK                           0x8000
#define RX2_RX_ANALOGBIAS2_EN_CLK16_ALIGN                          0
#define RX2_RX_ANALOGBIAS2_EN_CLK16_BITS                           1
#define RX2_RX_ANALOGBIAS2_EN_CLK16_SHIFT                          15

/* RX2 :: Rx_analogBias2 :: pd_ch_p1 [14:14] */
#define RX2_RX_ANALOGBIAS2_PD_CH_P1_MASK                           0x4000
#define RX2_RX_ANALOGBIAS2_PD_CH_P1_ALIGN                          0
#define RX2_RX_ANALOGBIAS2_PD_CH_P1_BITS                           1
#define RX2_RX_ANALOGBIAS2_PD_CH_P1_SHIFT                          14

/* RX2 :: Rx_analogBias2 :: en_vcctrl [13:13] */
#define RX2_RX_ANALOGBIAS2_EN_VCCTRL_MASK                          0x2000
#define RX2_RX_ANALOGBIAS2_EN_VCCTRL_ALIGN                         0
#define RX2_RX_ANALOGBIAS2_EN_VCCTRL_BITS                          1
#define RX2_RX_ANALOGBIAS2_EN_VCCTRL_SHIFT                         13

/* RX2 :: Rx_analogBias2 :: en_dfeclk [12:12] */
#define RX2_RX_ANALOGBIAS2_EN_DFECLK_MASK                          0x1000
#define RX2_RX_ANALOGBIAS2_EN_DFECLK_ALIGN                         0
#define RX2_RX_ANALOGBIAS2_EN_DFECLK_BITS                          1
#define RX2_RX_ANALOGBIAS2_EN_DFECLK_SHIFT                         12

/* RX2 :: Rx_analogBias2 :: en_hgain [11:11] */
#define RX2_RX_ANALOGBIAS2_EN_HGAIN_MASK                           0x0800
#define RX2_RX_ANALOGBIAS2_EN_HGAIN_ALIGN                          0
#define RX2_RX_ANALOGBIAS2_EN_HGAIN_BITS                           1
#define RX2_RX_ANALOGBIAS2_EN_HGAIN_SHIFT                          11

/* RX2 :: Rx_analogBias2 :: en_dfeckpwr [10:10] */
#define RX2_RX_ANALOGBIAS2_EN_DFECKPWR_MASK                        0x0400
#define RX2_RX_ANALOGBIAS2_EN_DFECKPWR_ALIGN                       0
#define RX2_RX_ANALOGBIAS2_EN_DFECKPWR_BITS                        1
#define RX2_RX_ANALOGBIAS2_EN_DFECKPWR_SHIFT                       10

/* RX2 :: Rx_analogBias2 :: offset_pd [09:09] */
#define RX2_RX_ANALOGBIAS2_OFFSET_PD_MASK                          0x0200
#define RX2_RX_ANALOGBIAS2_OFFSET_PD_ALIGN                         0
#define RX2_RX_ANALOGBIAS2_OFFSET_PD_BITS                          1
#define RX2_RX_ANALOGBIAS2_OFFSET_PD_SHIFT                         9

/* RX2 :: Rx_analogBias2 :: imax_dfetap [08:08] */
#define RX2_RX_ANALOGBIAS2_IMAX_DFETAP_MASK                        0x0100
#define RX2_RX_ANALOGBIAS2_IMAX_DFETAP_ALIGN                       0
#define RX2_RX_ANALOGBIAS2_IMAX_DFETAP_BITS                        1
#define RX2_RX_ANALOGBIAS2_IMAX_DFETAP_SHIFT                       8

/* RX2 :: Rx_analogBias2 :: imode_dfetap [07:07] */
#define RX2_RX_ANALOGBIAS2_IMODE_DFETAP_MASK                       0x0080
#define RX2_RX_ANALOGBIAS2_IMODE_DFETAP_ALIGN                      0
#define RX2_RX_ANALOGBIAS2_IMODE_DFETAP_BITS                       1
#define RX2_RX_ANALOGBIAS2_IMODE_DFETAP_SHIFT                      7

/* RX2 :: Rx_analogBias2 :: imin_dfetap [06:06] */
#define RX2_RX_ANALOGBIAS2_IMIN_DFETAP_MASK                        0x0040
#define RX2_RX_ANALOGBIAS2_IMIN_DFETAP_ALIGN                       0
#define RX2_RX_ANALOGBIAS2_IMIN_DFETAP_BITS                        1
#define RX2_RX_ANALOGBIAS2_IMIN_DFETAP_SHIFT                       6

/* RX2 :: Rx_analogBias2 :: imax_slcd2c [05:05] */
#define RX2_RX_ANALOGBIAS2_IMAX_SLCD2C_MASK                        0x0020
#define RX2_RX_ANALOGBIAS2_IMAX_SLCD2C_ALIGN                       0
#define RX2_RX_ANALOGBIAS2_IMAX_SLCD2C_BITS                        1
#define RX2_RX_ANALOGBIAS2_IMAX_SLCD2C_SHIFT                       5

/* RX2 :: Rx_analogBias2 :: imode_slcd2c [04:04] */
#define RX2_RX_ANALOGBIAS2_IMODE_SLCD2C_MASK                       0x0010
#define RX2_RX_ANALOGBIAS2_IMODE_SLCD2C_ALIGN                      0
#define RX2_RX_ANALOGBIAS2_IMODE_SLCD2C_BITS                       1
#define RX2_RX_ANALOGBIAS2_IMODE_SLCD2C_SHIFT                      4

/* RX2 :: Rx_analogBias2 :: imin_slcd2c [03:03] */
#define RX2_RX_ANALOGBIAS2_IMIN_SLCD2C_MASK                        0x0008
#define RX2_RX_ANALOGBIAS2_IMIN_SLCD2C_ALIGN                       0
#define RX2_RX_ANALOGBIAS2_IMIN_SLCD2C_BITS                        1
#define RX2_RX_ANALOGBIAS2_IMIN_SLCD2C_SHIFT                       3

/* RX2 :: Rx_analogBias2 :: imax_dfevref [02:02] */
#define RX2_RX_ANALOGBIAS2_IMAX_DFEVREF_MASK                       0x0004
#define RX2_RX_ANALOGBIAS2_IMAX_DFEVREF_ALIGN                      0
#define RX2_RX_ANALOGBIAS2_IMAX_DFEVREF_BITS                       1
#define RX2_RX_ANALOGBIAS2_IMAX_DFEVREF_SHIFT                      2

/* RX2 :: Rx_analogBias2 :: imode_dfevref [01:01] */
#define RX2_RX_ANALOGBIAS2_IMODE_DFEVREF_MASK                      0x0002
#define RX2_RX_ANALOGBIAS2_IMODE_DFEVREF_ALIGN                     0
#define RX2_RX_ANALOGBIAS2_IMODE_DFEVREF_BITS                      1
#define RX2_RX_ANALOGBIAS2_IMODE_DFEVREF_SHIFT                     1

/* RX2 :: Rx_analogBias2 :: imin_dfevref [00:00] */
#define RX2_RX_ANALOGBIAS2_IMIN_DFEVREF_MASK                       0x0001
#define RX2_RX_ANALOGBIAS2_IMIN_DFEVREF_ALIGN                      0
#define RX2_RX_ANALOGBIAS2_IMIN_DFEVREF_BITS                       1
#define RX2_RX_ANALOGBIAS2_IMIN_DFEVREF_SHIFT                      0


/****************************************************************************
 * XGXS16G_USER_RX3
 ***************************************************************************/
/****************************************************************************
 * RX3 :: Rx_Status
 ***************************************************************************/
/* union - case sigdet_Status [15:00] */
/* RX3 :: Rx_Status :: cx4_sigdet [15:15] */
#define RX3_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_MASK                0x8000
#define RX3_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_ALIGN               0
#define RX3_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_BITS                1
#define RX3_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_SHIFT               15

/* RX3 :: Rx_Status :: reserved0 [14:13] */
#define RX3_RX_STATUS_SIGDET_STATUS_RESERVED0_MASK                 0x6000
#define RX3_RX_STATUS_SIGDET_STATUS_RESERVED0_ALIGN                0
#define RX3_RX_STATUS_SIGDET_STATUS_RESERVED0_BITS                 2
#define RX3_RX_STATUS_SIGDET_STATUS_RESERVED0_SHIFT                13

/* RX3 :: Rx_Status :: rxSeqDone [12:12] */
#define RX3_RX_STATUS_SIGDET_STATUS_RXSEQDONE_MASK                 0x1000
#define RX3_RX_STATUS_SIGDET_STATUS_RXSEQDONE_ALIGN                0
#define RX3_RX_STATUS_SIGDET_STATUS_RXSEQDONE_BITS                 1
#define RX3_RX_STATUS_SIGDET_STATUS_RXSEQDONE_SHIFT                12

/* RX3 :: Rx_Status :: rx_sigdet_ll [11:11] */
#define RX3_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_MASK              0x0800
#define RX3_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_ALIGN             0
#define RX3_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_BITS              1
#define RX3_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_SHIFT             11

/* RX3 :: Rx_Status :: cs4_sigdet_ll [10:10] */
#define RX3_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_MASK             0x0400
#define RX3_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_ALIGN            0
#define RX3_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_BITS             1
#define RX3_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_SHIFT            10

/* RX3 :: Rx_Status :: rx_reset [09:09] */
#define RX3_RX_STATUS_SIGDET_STATUS_RX_RESET_MASK                  0x0200
#define RX3_RX_STATUS_SIGDET_STATUS_RX_RESET_ALIGN                 0
#define RX3_RX_STATUS_SIGDET_STATUS_RX_RESET_BITS                  1
#define RX3_RX_STATUS_SIGDET_STATUS_RX_RESET_SHIFT                 9

/* RX3 :: Rx_Status :: rx_pwrdn [08:08] */
#define RX3_RX_STATUS_SIGDET_STATUS_RX_PWRDN_MASK                  0x0100
#define RX3_RX_STATUS_SIGDET_STATUS_RX_PWRDN_ALIGN                 0
#define RX3_RX_STATUS_SIGDET_STATUS_RX_PWRDN_BITS                  1
#define RX3_RX_STATUS_SIGDET_STATUS_RX_PWRDN_SHIFT                 8

/* RX3 :: Rx_Status :: reserved1 [07:00] */
#define RX3_RX_STATUS_SIGDET_STATUS_RESERVED1_MASK                 0x00ff
#define RX3_RX_STATUS_SIGDET_STATUS_RESERVED1_ALIGN                0
#define RX3_RX_STATUS_SIGDET_STATUS_RESERVED1_BITS                 8
#define RX3_RX_STATUS_SIGDET_STATUS_RESERVED1_SHIFT                0


/* union - case sync_Status [15:00] */
/* RX3 :: Rx_Status :: reserved0 [15:11] */
#define RX3_RX_STATUS_SYNC_STATUS_RESERVED0_MASK                   0xf800
#define RX3_RX_STATUS_SYNC_STATUS_RESERVED0_ALIGN                  0
#define RX3_RX_STATUS_SYNC_STATUS_RESERVED0_BITS                   5
#define RX3_RX_STATUS_SYNC_STATUS_RESERVED0_SHIFT                  11

/* RX3 :: Rx_Status :: test_acq_en [10:10] */
#define RX3_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_MASK                 0x0400
#define RX3_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_ALIGN                0
#define RX3_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_BITS                 1
#define RX3_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_SHIFT                10

/* RX3 :: Rx_Status :: reserved1 [09:09] */
#define RX3_RX_STATUS_SYNC_STATUS_RESERVED1_MASK                   0x0200
#define RX3_RX_STATUS_SYNC_STATUS_RESERVED1_ALIGN                  0
#define RX3_RX_STATUS_SYNC_STATUS_RESERVED1_BITS                   1
#define RX3_RX_STATUS_SYNC_STATUS_RESERVED1_SHIFT                  9

/* RX3 :: Rx_Status :: rxSeqStart [08:08] */
#define RX3_RX_STATUS_SYNC_STATUS_RXSEQSTART_MASK                  0x0100
#define RX3_RX_STATUS_SYNC_STATUS_RXSEQSTART_ALIGN                 0
#define RX3_RX_STATUS_SYNC_STATUS_RXSEQSTART_BITS                  1
#define RX3_RX_STATUS_SYNC_STATUS_RXSEQSTART_SHIFT                 8

/* RX3 :: Rx_Status :: mux_comadj_sync_status [07:07] */
#define RX3_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_MASK      0x0080
#define RX3_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_ALIGN     0
#define RX3_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_BITS      1
#define RX3_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_SHIFT     7

/* RX3 :: Rx_Status :: sync_status [06:06] */
#define RX3_RX_STATUS_SYNC_STATUS_SYNC_STATUS_MASK                 0x0040
#define RX3_RX_STATUS_SYNC_STATUS_SYNC_STATUS_ALIGN                0
#define RX3_RX_STATUS_SYNC_STATUS_SYNC_STATUS_BITS                 1
#define RX3_RX_STATUS_SYNC_STATUS_SYNC_STATUS_SHIFT                6

/* RX3 :: Rx_Status :: rx_sigdet [05:05] */
#define RX3_RX_STATUS_SYNC_STATUS_RX_SIGDET_MASK                   0x0020
#define RX3_RX_STATUS_SYNC_STATUS_RX_SIGDET_ALIGN                  0
#define RX3_RX_STATUS_SYNC_STATUS_RX_SIGDET_BITS                   1
#define RX3_RX_STATUS_SYNC_STATUS_RX_SIGDET_SHIFT                  5

/* RX3 :: Rx_Status :: reserved2 [04:03] */
#define RX3_RX_STATUS_SYNC_STATUS_RESERVED2_MASK                   0x0018
#define RX3_RX_STATUS_SYNC_STATUS_RESERVED2_ALIGN                  0
#define RX3_RX_STATUS_SYNC_STATUS_RESERVED2_BITS                   2
#define RX3_RX_STATUS_SYNC_STATUS_RESERVED2_SHIFT                  3

/* RX3 :: Rx_Status :: saturate_status [02:02] */
#define RX3_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_MASK             0x0004
#define RX3_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_ALIGN            0
#define RX3_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_BITS             1
#define RX3_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_SHIFT            2

/* RX3 :: Rx_Status :: cx4_sigdet [01:01] */
#define RX3_RX_STATUS_SYNC_STATUS_CX4_SIGDET_MASK                  0x0002
#define RX3_RX_STATUS_SYNC_STATUS_CX4_SIGDET_ALIGN                 0
#define RX3_RX_STATUS_SYNC_STATUS_CX4_SIGDET_BITS                  1
#define RX3_RX_STATUS_SYNC_STATUS_CX4_SIGDET_SHIFT                 1

/* RX3 :: Rx_Status :: rxSeqDone [00:00] */
#define RX3_RX_STATUS_SYNC_STATUS_RXSEQDONE_MASK                   0x0001
#define RX3_RX_STATUS_SYNC_STATUS_RXSEQDONE_ALIGN                  0
#define RX3_RX_STATUS_SYNC_STATUS_RXSEQDONE_BITS                   1
#define RX3_RX_STATUS_SYNC_STATUS_RXSEQDONE_SHIFT                  0


/* union - case rxTestSel_0 [15:00] */
/* RX3 :: Rx_Status :: reserved0 [15:10] */
#define RX3_RX_STATUS_RXTESTSEL_0_RESERVED0_MASK                   0xfc00
#define RX3_RX_STATUS_RXTESTSEL_0_RESERVED0_ALIGN                  0
#define RX3_RX_STATUS_RXTESTSEL_0_RESERVED0_BITS                   6
#define RX3_RX_STATUS_RXTESTSEL_0_RESERVED0_SHIFT                  10

/* RX3 :: Rx_Status :: indck_mode_en [09:09] */
#define RX3_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_MASK               0x0200
#define RX3_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_ALIGN              0
#define RX3_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_BITS               1
#define RX3_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_SHIFT              9

/* RX3 :: Rx_Status :: pci_mode_en [08:08] */
#define RX3_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_MASK                 0x0100
#define RX3_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_ALIGN                0
#define RX3_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_BITS                 1
#define RX3_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_SHIFT                8

/* RX3 :: Rx_Status :: rx_polarity [07:07] */
#define RX3_RX_STATUS_RXTESTSEL_0_RX_POLARITY_MASK                 0x0080
#define RX3_RX_STATUS_RXTESTSEL_0_RX_POLARITY_ALIGN                0
#define RX3_RX_STATUS_RXTESTSEL_0_RX_POLARITY_BITS                 1
#define RX3_RX_STATUS_RXTESTSEL_0_RX_POLARITY_SHIFT                7

/* RX3 :: Rx_Status :: rxpol_flip [06:06] */
#define RX3_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_MASK                  0x0040
#define RX3_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_ALIGN                 0
#define RX3_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_BITS                  1
#define RX3_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_SHIFT                 6

/* RX3 :: Rx_Status :: comma_mask [05:05] */
#define RX3_RX_STATUS_RXTESTSEL_0_COMMA_MASK_MASK                  0x0020
#define RX3_RX_STATUS_RXTESTSEL_0_COMMA_MASK_ALIGN                 0
#define RX3_RX_STATUS_RXTESTSEL_0_COMMA_MASK_BITS                  1
#define RX3_RX_STATUS_RXTESTSEL_0_COMMA_MASK_SHIFT                 5

/* RX3 :: Rx_Status :: link_en_r [04:04] */
#define RX3_RX_STATUS_RXTESTSEL_0_LINK_EN_R_MASK                   0x0010
#define RX3_RX_STATUS_RXTESTSEL_0_LINK_EN_R_ALIGN                  0
#define RX3_RX_STATUS_RXTESTSEL_0_LINK_EN_R_BITS                   1
#define RX3_RX_STATUS_RXTESTSEL_0_LINK_EN_R_SHIFT                  4

/* RX3 :: Rx_Status :: comma_adj_en [03:03] */
#define RX3_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_MASK                0x0008
#define RX3_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_ALIGN               0
#define RX3_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_BITS                1
#define RX3_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_SHIFT               3

/* RX3 :: Rx_Status :: comma_adj_en_ext [02:02] */
#define RX3_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_MASK            0x0004
#define RX3_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_ALIGN           0
#define RX3_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_BITS            1
#define RX3_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_SHIFT           2

/* RX3 :: Rx_Status :: reserved1 [01:00] */
#define RX3_RX_STATUS_RXTESTSEL_0_RESERVED1_MASK                   0x0003
#define RX3_RX_STATUS_RXTESTSEL_0_RESERVED1_ALIGN                  0
#define RX3_RX_STATUS_RXTESTSEL_0_RESERVED1_BITS                   2
#define RX3_RX_STATUS_RXTESTSEL_0_RESERVED1_SHIFT                  0


/* union - case rxTestSel_1 [15:00] */
/* RX3 :: Rx_Status :: reserved0 [15:05] */
#define RX3_RX_STATUS_RXTESTSEL_1_RESERVED0_MASK                   0xffe0
#define RX3_RX_STATUS_RXTESTSEL_1_RESERVED0_ALIGN                  0
#define RX3_RX_STATUS_RXTESTSEL_1_RESERVED0_BITS                   11
#define RX3_RX_STATUS_RXTESTSEL_1_RESERVED0_SHIFT                  5

/* RX3 :: Rx_Status :: cdrAcqDone_r2 [04:04] */
#define RX3_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_MASK               0x0010
#define RX3_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_ALIGN              0
#define RX3_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_BITS               1
#define RX3_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_SHIFT              4

/* RX3 :: Rx_Status :: freq_sel_PC [03:03] */
#define RX3_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_MASK                 0x0008
#define RX3_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_ALIGN                0
#define RX3_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_BITS                 1
#define RX3_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_SHIFT                3

/* RX3 :: Rx_Status :: freq_sel_SM [02:02] */
#define RX3_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_MASK                 0x0004
#define RX3_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_ALIGN                0
#define RX3_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_BITS                 1
#define RX3_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_SHIFT                2

/* RX3 :: Rx_Status :: integ_mode_SM [01:00] */
#define RX3_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_MASK               0x0003
#define RX3_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_ALIGN              0
#define RX3_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_BITS               2
#define RX3_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_SHIFT              0


/* union - case scale_Status [15:00] */
/* RX3 :: Rx_Status :: prop_scale [15:12] */
#define RX3_RX_STATUS_SCALE_STATUS_PROP_SCALE_MASK                 0xf000
#define RX3_RX_STATUS_SCALE_STATUS_PROP_SCALE_ALIGN                0
#define RX3_RX_STATUS_SCALE_STATUS_PROP_SCALE_BITS                 4
#define RX3_RX_STATUS_SCALE_STATUS_PROP_SCALE_SHIFT                12

/* RX3 :: Rx_Status :: integ_scale [11:08] */
#define RX3_RX_STATUS_SCALE_STATUS_INTEG_SCALE_MASK                0x0f00
#define RX3_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ALIGN               0
#define RX3_RX_STATUS_SCALE_STATUS_INTEG_SCALE_BITS                4
#define RX3_RX_STATUS_SCALE_STATUS_INTEG_SCALE_SHIFT               8

/* RX3 :: Rx_Status :: prop_scale_acq [07:04] */
#define RX3_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_MASK             0x00f0
#define RX3_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_ALIGN            0
#define RX3_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_BITS             4
#define RX3_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_SHIFT            4

/* RX3 :: Rx_Status :: integ_scale_acq [03:00] */
#define RX3_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_MASK            0x000f
#define RX3_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_ALIGN           0
#define RX3_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_BITS            4
#define RX3_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_SHIFT           0


/* union - case adc_CdrStatus1 [15:00] */
/* RX3 :: Rx_Status :: reserved0 [15:07] */
#define RX3_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_MASK                0xff80
#define RX3_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_ALIGN               0
#define RX3_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_BITS                9
#define RX3_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_SHIFT               7

/* RX3 :: Rx_Status :: rxMuxCkSel [06:06] */
#define RX3_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_MASK               0x0040
#define RX3_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_ALIGN              0
#define RX3_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_BITS               1
#define RX3_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_SHIFT              6

/* RX3 :: Rx_Status :: glpbk_combo [05:05] */
#define RX3_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_MASK              0x0020
#define RX3_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_ALIGN             0
#define RX3_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_BITS              1
#define RX3_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_SHIFT             5

/* RX3 :: Rx_Status :: clockSwitchSel [04:04] */
#define RX3_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_MASK           0x0010
#define RX3_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_ALIGN          0
#define RX3_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_BITS           1
#define RX3_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_SHIFT          4

/* RX3 :: Rx_Status :: rxck_tst [03:03] */
#define RX3_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_MASK                 0x0008
#define RX3_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_ALIGN                0
#define RX3_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_BITS                 1
#define RX3_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_SHIFT                3

/* RX3 :: Rx_Status :: rxck_i [02:02] */
#define RX3_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_MASK                   0x0004
#define RX3_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_ALIGN                  0
#define RX3_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_BITS                   1
#define RX3_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_SHIFT                  2

/* RX3 :: Rx_Status :: refclk [01:01] */
#define RX3_RX_STATUS_ADC_CDRSTATUS1_REFCLK_MASK                   0x0002
#define RX3_RX_STATUS_ADC_CDRSTATUS1_REFCLK_ALIGN                  0
#define RX3_RX_STATUS_ADC_CDRSTATUS1_REFCLK_BITS                   1
#define RX3_RX_STATUS_ADC_CDRSTATUS1_REFCLK_SHIFT                  1

/* RX3 :: Rx_Status :: pll_bypass [00:00] */
#define RX3_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_MASK               0x0001
#define RX3_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_ALIGN              0
#define RX3_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_BITS               1
#define RX3_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_SHIFT              0


/* union - case adc_CdrStatus2 [15:00] */
/* RX3 :: Rx_Status :: reserved0 [15:06] */
#define RX3_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_MASK                0xffc0
#define RX3_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_ALIGN               0
#define RX3_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_BITS                10
#define RX3_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_SHIFT               6

/* RX3 :: Rx_Status :: rxMuxCkSel [05:05] */
#define RX3_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_MASK               0x0020
#define RX3_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_ALIGN              0
#define RX3_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_BITS               1
#define RX3_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_SHIFT              5

/* RX3 :: Rx_Status :: rxSeqStart [04:04] */
#define RX3_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_MASK               0x0010
#define RX3_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_ALIGN              0
#define RX3_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_BITS               1
#define RX3_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_SHIFT              4

/* RX3 :: Rx_Status :: reserved1 [03:01] */
#define RX3_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_MASK                0x000e
#define RX3_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_ALIGN               0
#define RX3_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_BITS                3
#define RX3_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_SHIFT               1

/* RX3 :: Rx_Status :: rxSeqDone [00:00] */
#define RX3_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_MASK                0x0001
#define RX3_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_ALIGN               0
#define RX3_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_BITS                1
#define RX3_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_SHIFT               0


/* union - case adc_CdrStatus3 [15:00] */
/* RX3 :: Rx_Status :: reserved0 [15:04] */
#define RX3_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_MASK                0xfff0
#define RX3_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_ALIGN               0
#define RX3_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_BITS                12
#define RX3_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_SHIFT               4

/* RX3 :: Rx_Status :: rxSeqStart [03:03] */
#define RX3_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_MASK               0x0008
#define RX3_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_ALIGN              0
#define RX3_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_BITS               1
#define RX3_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_SHIFT              3

/* RX3 :: Rx_Status :: reserved1 [02:01] */
#define RX3_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_MASK                0x0006
#define RX3_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_ALIGN               0
#define RX3_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_BITS                2
#define RX3_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_SHIFT               1

/* RX3 :: Rx_Status :: allow_increment_PC [00:00] */
#define RX3_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_MASK       0x0001
#define RX3_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_ALIGN      0
#define RX3_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_BITS       1
#define RX3_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_SHIFT      0


/* union - case adc_CdrStatus4 [15:00] */
/* RX3 :: Rx_Status :: reserved0 [15:08] */
#define RX3_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_MASK                0xff00
#define RX3_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_ALIGN               0
#define RX3_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_BITS                8
#define RX3_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_SHIFT               8

/* RX3 :: Rx_Status :: rx_pwrdn [07:07] */
#define RX3_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_MASK                 0x0080
#define RX3_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_ALIGN                0
#define RX3_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_BITS                 1
#define RX3_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_SHIFT                7

/* RX3 :: Rx_Status :: freq_sel [06:06] */
#define RX3_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_MASK                 0x0040
#define RX3_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_ALIGN                0
#define RX3_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_BITS                 1
#define RX3_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_SHIFT                6

/* RX3 :: Rx_Status :: pll_lock_rstb [05:05] */
#define RX3_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_MASK            0x0020
#define RX3_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_ALIGN           0
#define RX3_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_BITS            1
#define RX3_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_SHIFT           5

/* RX3 :: Rx_Status :: pwrdn [04:04] */
#define RX3_RX_STATUS_ADC_CDRSTATUS4_PWRDN_MASK                    0x0010
#define RX3_RX_STATUS_ADC_CDRSTATUS4_PWRDN_ALIGN                   0
#define RX3_RX_STATUS_ADC_CDRSTATUS4_PWRDN_BITS                    1
#define RX3_RX_STATUS_ADC_CDRSTATUS4_PWRDN_SHIFT                   4

/* RX3 :: Rx_Status :: reserved1 [03:00] */
#define RX3_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_MASK                0x000f
#define RX3_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_ALIGN               0
#define RX3_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_BITS                4
#define RX3_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_SHIFT               0


/* union - case adc_CdrStatus5 [15:00] */
/* RX3 :: Rx_Status :: reserved0 [15:00] */
#define RX3_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_MASK                0xffff
#define RX3_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_ALIGN               0
#define RX3_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_BITS                16
#define RX3_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_SHIFT               0


/* union - case adc_CdrStatus6 [15:00] */
/* RX3 :: Rx_Status :: reserved0 [15:05] */
#define RX3_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_MASK                0xffe0
#define RX3_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_ALIGN               0
#define RX3_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_BITS                11
#define RX3_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_SHIFT               5

/* RX3 :: Rx_Status :: rx_reset [04:04] */
#define RX3_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_MASK                 0x0010
#define RX3_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_ALIGN                0
#define RX3_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_BITS                 1
#define RX3_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_SHIFT                4

/* RX3 :: Rx_Status :: rx_pwrdn [03:03] */
#define RX3_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_MASK                 0x0008
#define RX3_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_ALIGN                0
#define RX3_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_BITS                 1
#define RX3_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_SHIFT                3

/* RX3 :: Rx_Status :: reset_anlg [02:02] */
#define RX3_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_MASK               0x0004
#define RX3_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_ALIGN              0
#define RX3_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_BITS               1
#define RX3_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_SHIFT              2

/* RX3 :: Rx_Status :: pwrdn_rx [01:01] */
#define RX3_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_MASK                 0x0002
#define RX3_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_ALIGN                0
#define RX3_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_BITS                 1
#define RX3_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_SHIFT                1

/* RX3 :: Rx_Status :: pwrdn_pll [00:00] */
#define RX3_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_MASK                0x0001
#define RX3_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_ALIGN               0
#define RX3_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_BITS                1
#define RX3_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_SHIFT               0


/* union - case adc_CdrStatus7e [15:00] */
/* RX3 :: Rx_Status :: reserved0 [15:05] */
#define RX3_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_MASK               0xffe0
#define RX3_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_ALIGN              0
#define RX3_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_BITS               11
#define RX3_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_SHIFT              5

/* RX3 :: Rx_Status :: rxck0_even [04:04] */
#define RX3_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_MASK              0x0010
#define RX3_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_ALIGN             0
#define RX3_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_BITS              1
#define RX3_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_SHIFT             4

/* RX3 :: Rx_Status :: rxck1_even [03:03] */
#define RX3_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_MASK              0x0008
#define RX3_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_ALIGN             0
#define RX3_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_BITS              1
#define RX3_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_SHIFT             3

/* RX3 :: Rx_Status :: comdet_even [02:02] */
#define RX3_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_MASK             0x0004
#define RX3_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_ALIGN            0
#define RX3_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_BITS             1
#define RX3_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_SHIFT            2

/* RX3 :: Rx_Status :: en_cdet_even [01:01] */
#define RX3_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_MASK            0x0002
#define RX3_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_ALIGN           0
#define RX3_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_BITS            1
#define RX3_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_SHIFT           1

/* RX3 :: Rx_Status :: comma_adj_en_even [00:00] */
#define RX3_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_MASK       0x0001
#define RX3_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_ALIGN      0
#define RX3_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_BITS       1
#define RX3_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_SHIFT      0


/* union - case adc_CdrStatus7o [15:00] */
/* RX3 :: Rx_Status :: reserved0 [15:05] */
#define RX3_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_MASK               0xffe0
#define RX3_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_ALIGN              0
#define RX3_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_BITS               11
#define RX3_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_SHIFT              5

/* RX3 :: Rx_Status :: rxck0_odd [04:04] */
#define RX3_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_MASK               0x0010
#define RX3_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_ALIGN              0
#define RX3_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_BITS               1
#define RX3_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_SHIFT              4

/* RX3 :: Rx_Status :: rxck1_odd [03:03] */
#define RX3_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_MASK               0x0008
#define RX3_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_ALIGN              0
#define RX3_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_BITS               1
#define RX3_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_SHIFT              3

/* RX3 :: Rx_Status :: comdet_odd [02:02] */
#define RX3_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_MASK              0x0004
#define RX3_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_ALIGN             0
#define RX3_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_BITS              1
#define RX3_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_SHIFT             2

/* RX3 :: Rx_Status :: en_cdet_odd [01:01] */
#define RX3_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_MASK             0x0002
#define RX3_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_ALIGN            0
#define RX3_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_BITS             1
#define RX3_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_SHIFT            1

/* RX3 :: Rx_Status :: comma_adj_en_odd [00:00] */
#define RX3_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_MASK        0x0001
#define RX3_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_ALIGN       0
#define RX3_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_BITS        1
#define RX3_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_SHIFT       0


/* union - case adc_CdrStatus8 [15:00] */
/* RX3 :: Rx_Status :: reserved0 [15:01] */
#define RX3_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_MASK                0xfffe
#define RX3_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_ALIGN               0
#define RX3_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_BITS                15
#define RX3_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_SHIFT               1

/* RX3 :: Rx_Status :: sigdet [00:00] */
#define RX3_RX_STATUS_ADC_CDRSTATUS8_SIGDET_MASK                   0x0001
#define RX3_RX_STATUS_ADC_CDRSTATUS8_SIGDET_ALIGN                  0
#define RX3_RX_STATUS_ADC_CDRSTATUS8_SIGDET_BITS                   1
#define RX3_RX_STATUS_ADC_CDRSTATUS8_SIGDET_SHIFT                  0


/* union - case adc_CdrStatus9 [15:00] */
/* RX3 :: Rx_Status :: reserved0 [15:00] */
#define RX3_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_MASK                0xffff
#define RX3_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_ALIGN               0
#define RX3_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_BITS                16
#define RX3_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_SHIFT               0


/* union - case adc_CdrStatus10 [15:00] */
/* RX3 :: Rx_Status :: reserved0 [15:07] */
#define RX3_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_MASK               0xff80
#define RX3_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_ALIGN              0
#define RX3_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_BITS               9
#define RX3_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_SHIFT              7

/* RX3 :: Rx_Status :: prbs_en [06:06] */
#define RX3_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_MASK                 0x0040
#define RX3_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_ALIGN                0
#define RX3_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_BITS                 1
#define RX3_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_SHIFT                6

/* RX3 :: Rx_Status :: rstb_tst [05:05] */
#define RX3_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_MASK                0x0020
#define RX3_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_ALIGN               0
#define RX3_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_BITS                1
#define RX3_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_SHIFT               5

/* RX3 :: Rx_Status :: reserved1 [04:04] */
#define RX3_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_MASK               0x0010
#define RX3_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_ALIGN              0
#define RX3_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_BITS               1
#define RX3_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_SHIFT              4

/* RX3 :: Rx_Status :: prbs_state [03:00] */
#define RX3_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_MASK              0x000f
#define RX3_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_ALIGN             0
#define RX3_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_BITS              4
#define RX3_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_SHIFT             0


/* union - case adc_CdrStatus11 [15:00] */
/* RX3 :: Rx_Status :: reserved0 [15:00] */
#define RX3_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_MASK               0xffff
#define RX3_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_ALIGN              0
#define RX3_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_BITS               16
#define RX3_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_SHIFT              0


/* union - case adc_CdrStatus12_1 [15:00] */
/* RX3 :: Rx_Status :: reserved0 [15:06] */
#define RX3_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_MASK             0xffc0
#define RX3_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_ALIGN            0
#define RX3_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_BITS             10
#define RX3_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_SHIFT            6

/* RX3 :: Rx_Status :: enable4 [05:05] */
#define RX3_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_MASK               0x0020
#define RX3_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_ALIGN              0
#define RX3_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_BITS               1
#define RX3_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_SHIFT              5

/* RX3 :: Rx_Status :: radr_test [04:00] */
#define RX3_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_MASK             0x001f
#define RX3_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_ALIGN            0
#define RX3_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_BITS             5
#define RX3_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_SHIFT            0


/* union - case adc_CdrStatus12_2 [15:00] */
/* RX3 :: Rx_Status :: reserved0 [15:05] */
#define RX3_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_MASK             0xffe0
#define RX3_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_ALIGN            0
#define RX3_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_BITS             11
#define RX3_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_SHIFT            5

/* RX3 :: Rx_Status :: wadr_test [04:00] */
#define RX3_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_MASK             0x001f
#define RX3_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_ALIGN            0
#define RX3_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_BITS             5
#define RX3_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_SHIFT            0


/* union - case adc_CdrStatus12_3 [15:00] */
/* RX3 :: Rx_Status :: reserved0 [15:06] */
#define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_MASK             0xffc0
#define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_ALIGN            0
#define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_BITS             10
#define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_SHIFT            6

/* RX3 :: Rx_Status :: rxck_66B_tmux [05:05] */
#define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_MASK         0x0020
#define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_ALIGN        0
#define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_BITS         1
#define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_SHIFT        5

/* RX3 :: Rx_Status :: rstb_66B [04:04] */
#define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_MASK              0x0010
#define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_ALIGN             0
#define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_BITS              1
#define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_SHIFT             4

/* RX3 :: Rx_Status :: prstb_66B_mux [03:03] */
#define RX3_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_MASK         0x0008
#define RX3_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_ALIGN        0
#define RX3_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_BITS         1
#define RX3_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_SHIFT        3

/* RX3 :: Rx_Status :: rxck_i66_tmux [02:02] */
#define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_MASK         0x0004
#define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_ALIGN        0
#define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_BITS         1
#define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_SHIFT        2

/* RX3 :: Rx_Status :: rstb_i66 [01:01] */
#define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_MASK              0x0002
#define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_ALIGN             0
#define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_BITS              1
#define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_SHIFT             1

/* RX3 :: Rx_Status :: prstb_i66_mux [00:00] */
#define RX3_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_MASK         0x0001
#define RX3_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_ALIGN        0
#define RX3_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_BITS         1
#define RX3_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_SHIFT        0


/* union - case adc_CdrStatus12_4 [15:00] */
/* RX3 :: Rx_Status :: reserved0 [15:04] */
#define RX3_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_MASK             0xfff0
#define RX3_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_ALIGN            0
#define RX3_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_BITS             12
#define RX3_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_SHIFT            4

/* RX3 :: Rx_Status :: rfifo_error_r [03:02] */
#define RX3_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_MASK         0x000c
#define RX3_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_ALIGN        0
#define RX3_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_BITS         2
#define RX3_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_SHIFT        2

/* RX3 :: Rx_Status :: rfifo_unflow [01:01] */
#define RX3_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_MASK          0x0002
#define RX3_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_ALIGN         0
#define RX3_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_BITS          1
#define RX3_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_SHIFT         1

/* RX3 :: Rx_Status :: rfifo_ovflow [00:00] */
#define RX3_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_MASK          0x0001
#define RX3_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_ALIGN         0
#define RX3_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_BITS          1
#define RX3_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_SHIFT         0


/* union - case integ_Status [15:00] */
/* RX3 :: Rx_Status :: integ_status [15:00] */
#define RX3_RX_STATUS_INTEG_STATUS_INTEG_STATUS_MASK               0xffff
#define RX3_RX_STATUS_INTEG_STATUS_INTEG_STATUS_ALIGN              0
#define RX3_RX_STATUS_INTEG_STATUS_INTEG_STATUS_BITS               16
#define RX3_RX_STATUS_INTEG_STATUS_INTEG_STATUS_SHIFT              0


/* union - case vco_Status [15:00] */
/* RX3 :: Rx_Status :: vco_status [15:00] */
#define RX3_RX_STATUS_VCO_STATUS_VCO_STATUS_MASK                   0xffff
#define RX3_RX_STATUS_VCO_STATUS_VCO_STATUS_ALIGN                  0
#define RX3_RX_STATUS_VCO_STATUS_VCO_STATUS_BITS                   16
#define RX3_RX_STATUS_VCO_STATUS_VCO_STATUS_SHIFT                  0


/* union - case prbs_Status [15:00] */
/* RX3 :: Rx_Status :: prbs_lock [15:15] */
#define RX3_RX_STATUS_PRBS_STATUS_PRBS_LOCK_MASK                   0x8000
#define RX3_RX_STATUS_PRBS_STATUS_PRBS_LOCK_ALIGN                  0
#define RX3_RX_STATUS_PRBS_STATUS_PRBS_LOCK_BITS                   1
#define RX3_RX_STATUS_PRBS_STATUS_PRBS_LOCK_SHIFT                  15

/* RX3 :: Rx_Status :: prbs_stky [14:14] */
#define RX3_RX_STATUS_PRBS_STATUS_PRBS_STKY_MASK                   0x4000
#define RX3_RX_STATUS_PRBS_STATUS_PRBS_STKY_ALIGN                  0
#define RX3_RX_STATUS_PRBS_STATUS_PRBS_STKY_BITS                   1
#define RX3_RX_STATUS_PRBS_STATUS_PRBS_STKY_SHIFT                  14

/* RX3 :: Rx_Status :: ptbs_errors [13:00] */
#define RX3_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_MASK                 0x3fff
#define RX3_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_ALIGN                0
#define RX3_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_BITS                 14
#define RX3_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_SHIFT                0



/****************************************************************************
 * RX3 :: Rx_Control
 ***************************************************************************/
/* RX3 :: Rx_Control :: reserved0 [15:03] */
#define RX3_RX_CONTROL_RESERVED0_MASK                              0xfff8
#define RX3_RX_CONTROL_RESERVED0_ALIGN                             0
#define RX3_RX_CONTROL_RESERVED0_BITS                              13
#define RX3_RX_CONTROL_RESERVED0_SHIFT                             3

/* RX3 :: Rx_Control :: status_sel [02:00] */
#define RX3_RX_CONTROL_STATUS_SEL_MASK                             0x0007
#define RX3_RX_CONTROL_STATUS_SEL_ALIGN                            0
#define RX3_RX_CONTROL_STATUS_SEL_BITS                             3
#define RX3_RX_CONTROL_STATUS_SEL_SHIFT                            0
#define RX3_RX_CONTROL_STATUS_SEL_sigdetStatus                     0
#define RX3_RX_CONTROL_STATUS_SEL_syncStatus                       1
#define RX3_RX_CONTROL_STATUS_SEL_rxTestSel                        2
#define RX3_RX_CONTROL_STATUS_SEL_scaleStatus                      3
#define RX3_RX_CONTROL_STATUS_SEL_adcCdrStatus                     4
#define RX3_RX_CONTROL_STATUS_SEL_integStatus                      5
#define RX3_RX_CONTROL_STATUS_SEL_vcoStatus                        6
#define RX3_RX_CONTROL_STATUS_SEL_prbsStatus                       7


/****************************************************************************
 * RX3 :: Rx_Test
 ***************************************************************************/
/* RX3 :: Rx_Test :: sigdet_mux_SM [15:12] */
#define RX3_RX_TEST_SIGDET_MUX_SM_MASK                             0xf000
#define RX3_RX_TEST_SIGDET_MUX_SM_ALIGN                            0
#define RX3_RX_TEST_SIGDET_MUX_SM_BITS                             4
#define RX3_RX_TEST_SIGDET_MUX_SM_SHIFT                            12

/* RX3 :: Rx_Test :: reserved0 [11:09] */
#define RX3_RX_TEST_RESERVED0_MASK                                 0x0e00
#define RX3_RX_TEST_RESERVED0_ALIGN                                0
#define RX3_RX_TEST_RESERVED0_BITS                                 3
#define RX3_RX_TEST_RESERVED0_SHIFT                                9

/* RX3 :: Rx_Test :: tpctrl_SM [08:04] */
#define RX3_RX_TEST_TPCTRL_SM_MASK                                 0x01f0
#define RX3_RX_TEST_TPCTRL_SM_ALIGN                                0
#define RX3_RX_TEST_TPCTRL_SM_BITS                                 5
#define RX3_RX_TEST_TPCTRL_SM_SHIFT                                4

/* RX3 :: Rx_Test :: testMuxSelect_SM [03:00] */
#define RX3_RX_TEST_TESTMUXSELECT_SM_MASK                          0x000f
#define RX3_RX_TEST_TESTMUXSELECT_SM_ALIGN                         0
#define RX3_RX_TEST_TESTMUXSELECT_SM_BITS                          4
#define RX3_RX_TEST_TESTMUXSELECT_SM_SHIFT                         0


/****************************************************************************
 * RX3 :: Rx_Control_1G_type
 ***************************************************************************/
/* RX3 :: Rx_Control_1G_type :: fpat_md [15:15] */
#define RX3_RX_CONTROL_1G_TYPE_FPAT_MD_MASK                        0x8000
#define RX3_RX_CONTROL_1G_TYPE_FPAT_MD_ALIGN                       0
#define RX3_RX_CONTROL_1G_TYPE_FPAT_MD_BITS                        1
#define RX3_RX_CONTROL_1G_TYPE_FPAT_MD_SHIFT                       15

/* RX3 :: Rx_Control_1G_type :: pkt_count_en [14:14] */
#define RX3_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_MASK                   0x4000
#define RX3_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_ALIGN                  0
#define RX3_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_BITS                   1
#define RX3_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_SHIFT                  14

/* RX3 :: Rx_Control_1G_type :: staMuxRegDis [13:13] */
#define RX3_RX_CONTROL_1G_TYPE_STAMUXREGDIS_MASK                   0x2000
#define RX3_RX_CONTROL_1G_TYPE_STAMUXREGDIS_ALIGN                  0
#define RX3_RX_CONTROL_1G_TYPE_STAMUXREGDIS_BITS                   1
#define RX3_RX_CONTROL_1G_TYPE_STAMUXREGDIS_SHIFT                  13

/* RX3 :: Rx_Control_1G_type :: prbs_clr_dis [12:12] */
#define RX3_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_MASK                   0x1000
#define RX3_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_ALIGN                  0
#define RX3_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_BITS                   1
#define RX3_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_SHIFT                  12

/* RX3 :: Rx_Control_1G_type :: rxd_dec_sel [11:11] */
#define RX3_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_MASK                    0x0800
#define RX3_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_ALIGN                   0
#define RX3_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_BITS                    1
#define RX3_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_SHIFT                   11

/* RX3 :: Rx_Control_1G_type :: cgbad_tst [10:10] */
#define RX3_RX_CONTROL_1G_TYPE_CGBAD_TST_MASK                      0x0400
#define RX3_RX_CONTROL_1G_TYPE_CGBAD_TST_ALIGN                     0
#define RX3_RX_CONTROL_1G_TYPE_CGBAD_TST_BITS                      1
#define RX3_RX_CONTROL_1G_TYPE_CGBAD_TST_SHIFT                     10

/* RX3 :: Rx_Control_1G_type :: Emon_en [09:09] */
#define RX3_RX_CONTROL_1G_TYPE_EMON_EN_MASK                        0x0200
#define RX3_RX_CONTROL_1G_TYPE_EMON_EN_ALIGN                       0
#define RX3_RX_CONTROL_1G_TYPE_EMON_EN_BITS                        1
#define RX3_RX_CONTROL_1G_TYPE_EMON_EN_SHIFT                       9

/* RX3 :: Rx_Control_1G_type :: prbs_en [08:08] */
#define RX3_RX_CONTROL_1G_TYPE_PRBS_EN_MASK                        0x0100
#define RX3_RX_CONTROL_1G_TYPE_PRBS_EN_ALIGN                       0
#define RX3_RX_CONTROL_1G_TYPE_PRBS_EN_BITS                        1
#define RX3_RX_CONTROL_1G_TYPE_PRBS_EN_SHIFT                       8

/* RX3 :: Rx_Control_1G_type :: cgbad_en [07:07] */
#define RX3_RX_CONTROL_1G_TYPE_CGBAD_EN_MASK                       0x0080
#define RX3_RX_CONTROL_1G_TYPE_CGBAD_EN_ALIGN                      0
#define RX3_RX_CONTROL_1G_TYPE_CGBAD_EN_BITS                       1
#define RX3_RX_CONTROL_1G_TYPE_CGBAD_EN_SHIFT                      7

/* RX3 :: Rx_Control_1G_type :: cstretch [06:06] */
#define RX3_RX_CONTROL_1G_TYPE_CSTRETCH_MASK                       0x0040
#define RX3_RX_CONTROL_1G_TYPE_CSTRETCH_ALIGN                      0
#define RX3_RX_CONTROL_1G_TYPE_CSTRETCH_BITS                       1
#define RX3_RX_CONTROL_1G_TYPE_CSTRETCH_SHIFT                      6

/* RX3 :: Rx_Control_1G_type :: rtbi_ckflip [05:05] */
#define RX3_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_MASK                    0x0020
#define RX3_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_ALIGN                   0
#define RX3_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_BITS                    1
#define RX3_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_SHIFT                   5

/* RX3 :: Rx_Control_1G_type :: rtbi_flip [04:04] */
#define RX3_RX_CONTROL_1G_TYPE_RTBI_FLIP_MASK                      0x0010
#define RX3_RX_CONTROL_1G_TYPE_RTBI_FLIP_ALIGN                     0
#define RX3_RX_CONTROL_1G_TYPE_RTBI_FLIP_BITS                      1
#define RX3_RX_CONTROL_1G_TYPE_RTBI_FLIP_SHIFT                     4

/* RX3 :: Rx_Control_1G_type :: phase_sel [03:03] */
#define RX3_RX_CONTROL_1G_TYPE_PHASE_SEL_MASK                      0x0008
#define RX3_RX_CONTROL_1G_TYPE_PHASE_SEL_ALIGN                     0
#define RX3_RX_CONTROL_1G_TYPE_PHASE_SEL_BITS                      1
#define RX3_RX_CONTROL_1G_TYPE_PHASE_SEL_SHIFT                     3

/* RX3 :: Rx_Control_1G_type :: reserved0 [02:02] */
#define RX3_RX_CONTROL_1G_TYPE_RESERVED0_MASK                      0x0004
#define RX3_RX_CONTROL_1G_TYPE_RESERVED0_ALIGN                     0
#define RX3_RX_CONTROL_1G_TYPE_RESERVED0_BITS                      1
#define RX3_RX_CONTROL_1G_TYPE_RESERVED0_SHIFT                     2

/* RX3 :: Rx_Control_1G_type :: freq_sel_force [01:01] */
#define RX3_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_MASK                 0x0002
#define RX3_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_ALIGN                0
#define RX3_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_BITS                 1
#define RX3_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_SHIFT                1

/* RX3 :: Rx_Control_1G_type :: freq_sel [00:00] */
#define RX3_RX_CONTROL_1G_TYPE_FREQ_SEL_MASK                       0x0001
#define RX3_RX_CONTROL_1G_TYPE_FREQ_SEL_ALIGN                      0
#define RX3_RX_CONTROL_1G_TYPE_FREQ_SEL_BITS                       1
#define RX3_RX_CONTROL_1G_TYPE_FREQ_SEL_SHIFT                      0


/****************************************************************************
 * RX3 :: Rx_Astatus
 ***************************************************************************/
/* RX3 :: Rx_Astatus :: reserved0 [15:01] */
#define RX3_RX_ASTATUS_RESERVED0_MASK                              0xfffe
#define RX3_RX_ASTATUS_RESERVED0_ALIGN                             0
#define RX3_RX_ASTATUS_RESERVED0_BITS                              15
#define RX3_RX_ASTATUS_RESERVED0_SHIFT                             1

/* RX3 :: Rx_Astatus :: sigdet [00:00] */
#define RX3_RX_ASTATUS_SIGDET_MASK                                 0x0001
#define RX3_RX_ASTATUS_SIGDET_ALIGN                                0
#define RX3_RX_ASTATUS_SIGDET_BITS                                 1
#define RX3_RX_ASTATUS_SIGDET_SHIFT                                0


/****************************************************************************
 * RX3 :: Rx_analogBias0
 ***************************************************************************/
/* RX3 :: Rx_analogBias0 :: imode_vcm [15:15] */
#define RX3_RX_ANALOGBIAS0_IMODE_VCM_MASK                          0x8000
#define RX3_RX_ANALOGBIAS0_IMODE_VCM_ALIGN                         0
#define RX3_RX_ANALOGBIAS0_IMODE_VCM_BITS                          1
#define RX3_RX_ANALOGBIAS0_IMODE_VCM_SHIFT                         15

/* RX3 :: Rx_analogBias0 :: imin_vcm [14:14] */
#define RX3_RX_ANALOGBIAS0_IMIN_VCM_MASK                           0x4000
#define RX3_RX_ANALOGBIAS0_IMIN_VCM_ALIGN                          0
#define RX3_RX_ANALOGBIAS0_IMIN_VCM_BITS                           1
#define RX3_RX_ANALOGBIAS0_IMIN_VCM_SHIFT                          14

/* RX3 :: Rx_analogBias0 :: imax_sigdet [13:13] */
#define RX3_RX_ANALOGBIAS0_IMAX_SIGDET_MASK                        0x2000
#define RX3_RX_ANALOGBIAS0_IMAX_SIGDET_ALIGN                       0
#define RX3_RX_ANALOGBIAS0_IMAX_SIGDET_BITS                        1
#define RX3_RX_ANALOGBIAS0_IMAX_SIGDET_SHIFT                       13

/* RX3 :: Rx_analogBias0 :: imode_sigdet [12:12] */
#define RX3_RX_ANALOGBIAS0_IMODE_SIGDET_MASK                       0x1000
#define RX3_RX_ANALOGBIAS0_IMODE_SIGDET_ALIGN                      0
#define RX3_RX_ANALOGBIAS0_IMODE_SIGDET_BITS                       1
#define RX3_RX_ANALOGBIAS0_IMODE_SIGDET_SHIFT                      12

/* RX3 :: Rx_analogBias0 :: imin_sigdet [11:11] */
#define RX3_RX_ANALOGBIAS0_IMIN_SIGDET_MASK                        0x0800
#define RX3_RX_ANALOGBIAS0_IMIN_SIGDET_ALIGN                       0
#define RX3_RX_ANALOGBIAS0_IMIN_SIGDET_BITS                        1
#define RX3_RX_ANALOGBIAS0_IMIN_SIGDET_SHIFT                       11

/* RX3 :: Rx_analogBias0 :: refh_rx [10:10] */
#define RX3_RX_ANALOGBIAS0_REFH_RX_MASK                            0x0400
#define RX3_RX_ANALOGBIAS0_REFH_RX_ALIGN                           0
#define RX3_RX_ANALOGBIAS0_REFH_RX_BITS                            1
#define RX3_RX_ANALOGBIAS0_REFH_RX_SHIFT                           10

/* RX3 :: Rx_analogBias0 :: refl_rx [09:09] */
#define RX3_RX_ANALOGBIAS0_REFL_RX_MASK                            0x0200
#define RX3_RX_ANALOGBIAS0_REFL_RX_ALIGN                           0
#define RX3_RX_ANALOGBIAS0_REFL_RX_BITS                            1
#define RX3_RX_ANALOGBIAS0_REFL_RX_SHIFT                           9

/* RX3 :: Rx_analogBias0 :: tport_en [08:08] */
#define RX3_RX_ANALOGBIAS0_TPORT_EN_MASK                           0x0100
#define RX3_RX_ANALOGBIAS0_TPORT_EN_ALIGN                          0
#define RX3_RX_ANALOGBIAS0_TPORT_EN_BITS                           1
#define RX3_RX_ANALOGBIAS0_TPORT_EN_SHIFT                          8

/* RX3 :: Rx_analogBias0 :: vddr_bg [07:07] */
#define RX3_RX_ANALOGBIAS0_VDDR_BG_MASK                            0x0080
#define RX3_RX_ANALOGBIAS0_VDDR_BG_ALIGN                           0
#define RX3_RX_ANALOGBIAS0_VDDR_BG_BITS                            1
#define RX3_RX_ANALOGBIAS0_VDDR_BG_SHIFT                           7

/* RX3 :: Rx_analogBias0 :: sig_pwrdn [06:06] */
#define RX3_RX_ANALOGBIAS0_SIG_PWRDN_MASK                          0x0040
#define RX3_RX_ANALOGBIAS0_SIG_PWRDN_ALIGN                         0
#define RX3_RX_ANALOGBIAS0_SIG_PWRDN_BITS                          1
#define RX3_RX_ANALOGBIAS0_SIG_PWRDN_SHIFT                         6

/* RX3 :: Rx_analogBias0 :: offset_ctrl [05:03] */
#define RX3_RX_ANALOGBIAS0_OFFSET_CTRL_MASK                        0x0038
#define RX3_RX_ANALOGBIAS0_OFFSET_CTRL_ALIGN                       0
#define RX3_RX_ANALOGBIAS0_OFFSET_CTRL_BITS                        3
#define RX3_RX_ANALOGBIAS0_OFFSET_CTRL_SHIFT                       3

/* RX3 :: Rx_analogBias0 :: offset_sel [02:02] */
#define RX3_RX_ANALOGBIAS0_OFFSET_SEL_MASK                         0x0004
#define RX3_RX_ANALOGBIAS0_OFFSET_SEL_ALIGN                        0
#define RX3_RX_ANALOGBIAS0_OFFSET_SEL_BITS                         1
#define RX3_RX_ANALOGBIAS0_OFFSET_SEL_SHIFT                        2

/* RX3 :: Rx_analogBias0 :: reserved0 [01:00] */
#define RX3_RX_ANALOGBIAS0_RESERVED0_MASK                          0x0003
#define RX3_RX_ANALOGBIAS0_RESERVED0_ALIGN                         0
#define RX3_RX_ANALOGBIAS0_RESERVED0_BITS                          2
#define RX3_RX_ANALOGBIAS0_RESERVED0_SHIFT                         0


/****************************************************************************
 * RX3 :: Rx_analogBias1
 ***************************************************************************/
/* RX3 :: Rx_analogBias1 :: imax_clkbuf [15:15] */
#define RX3_RX_ANALOGBIAS1_IMAX_CLKBUF_MASK                        0x8000
#define RX3_RX_ANALOGBIAS1_IMAX_CLKBUF_ALIGN                       0
#define RX3_RX_ANALOGBIAS1_IMAX_CLKBUF_BITS                        1
#define RX3_RX_ANALOGBIAS1_IMAX_CLKBUF_SHIFT                       15

/* RX3 :: Rx_analogBias1 :: imode_clkbuf [14:14] */
#define RX3_RX_ANALOGBIAS1_IMODE_CLKBUF_MASK                       0x4000
#define RX3_RX_ANALOGBIAS1_IMODE_CLKBUF_ALIGN                      0
#define RX3_RX_ANALOGBIAS1_IMODE_CLKBUF_BITS                       1
#define RX3_RX_ANALOGBIAS1_IMODE_CLKBUF_SHIFT                      14

/* RX3 :: Rx_analogBias1 :: imin_clkbuf [13:13] */
#define RX3_RX_ANALOGBIAS1_IMIN_CLKBUF_MASK                        0x2000
#define RX3_RX_ANALOGBIAS1_IMIN_CLKBUF_ALIGN                       0
#define RX3_RX_ANALOGBIAS1_IMIN_CLKBUF_BITS                        1
#define RX3_RX_ANALOGBIAS1_IMIN_CLKBUF_SHIFT                       13

/* RX3 :: Rx_analogBias1 :: imax_eqfl [12:12] */
#define RX3_RX_ANALOGBIAS1_IMAX_EQFL_MASK                          0x1000
#define RX3_RX_ANALOGBIAS1_IMAX_EQFL_ALIGN                         0
#define RX3_RX_ANALOGBIAS1_IMAX_EQFL_BITS                          1
#define RX3_RX_ANALOGBIAS1_IMAX_EQFL_SHIFT                         12

/* RX3 :: Rx_analogBias1 :: imode_eqfl [11:11] */
#define RX3_RX_ANALOGBIAS1_IMODE_EQFL_MASK                         0x0800
#define RX3_RX_ANALOGBIAS1_IMODE_EQFL_ALIGN                        0
#define RX3_RX_ANALOGBIAS1_IMODE_EQFL_BITS                         1
#define RX3_RX_ANALOGBIAS1_IMODE_EQFL_SHIFT                        11

/* RX3 :: Rx_analogBias1 :: imin_eqfl [10:10] */
#define RX3_RX_ANALOGBIAS1_IMIN_EQFL_MASK                          0x0400
#define RX3_RX_ANALOGBIAS1_IMIN_EQFL_ALIGN                         0
#define RX3_RX_ANALOGBIAS1_IMIN_EQFL_BITS                          1
#define RX3_RX_ANALOGBIAS1_IMIN_EQFL_SHIFT                         10

/* RX3 :: Rx_analogBias1 :: imax_dfesum [09:09] */
#define RX3_RX_ANALOGBIAS1_IMAX_DFESUM_MASK                        0x0200
#define RX3_RX_ANALOGBIAS1_IMAX_DFESUM_ALIGN                       0
#define RX3_RX_ANALOGBIAS1_IMAX_DFESUM_BITS                        1
#define RX3_RX_ANALOGBIAS1_IMAX_DFESUM_SHIFT                       9

/* RX3 :: Rx_analogBias1 :: imode_dfesum [08:08] */
#define RX3_RX_ANALOGBIAS1_IMODE_DFESUM_MASK                       0x0100
#define RX3_RX_ANALOGBIAS1_IMODE_DFESUM_ALIGN                      0
#define RX3_RX_ANALOGBIAS1_IMODE_DFESUM_BITS                       1
#define RX3_RX_ANALOGBIAS1_IMODE_DFESUM_SHIFT                      8

/* RX3 :: Rx_analogBias1 :: imin_dfesum [07:07] */
#define RX3_RX_ANALOGBIAS1_IMIN_DFESUM_MASK                        0x0080
#define RX3_RX_ANALOGBIAS1_IMIN_DFESUM_ALIGN                       0
#define RX3_RX_ANALOGBIAS1_IMIN_DFESUM_BITS                        1
#define RX3_RX_ANALOGBIAS1_IMIN_DFESUM_SHIFT                       7

/* RX3 :: Rx_analogBias1 :: imax_vga [06:06] */
#define RX3_RX_ANALOGBIAS1_IMAX_VGA_MASK                           0x0040
#define RX3_RX_ANALOGBIAS1_IMAX_VGA_ALIGN                          0
#define RX3_RX_ANALOGBIAS1_IMAX_VGA_BITS                           1
#define RX3_RX_ANALOGBIAS1_IMAX_VGA_SHIFT                          6

/* RX3 :: Rx_analogBias1 :: imode_vga [05:05] */
#define RX3_RX_ANALOGBIAS1_IMODE_VGA_MASK                          0x0020
#define RX3_RX_ANALOGBIAS1_IMODE_VGA_ALIGN                         0
#define RX3_RX_ANALOGBIAS1_IMODE_VGA_BITS                          1
#define RX3_RX_ANALOGBIAS1_IMODE_VGA_SHIFT                         5

/* RX3 :: Rx_analogBias1 :: imin_vga [04:04] */
#define RX3_RX_ANALOGBIAS1_IMIN_VGA_MASK                           0x0010
#define RX3_RX_ANALOGBIAS1_IMIN_VGA_ALIGN                          0
#define RX3_RX_ANALOGBIAS1_IMIN_VGA_BITS                           1
#define RX3_RX_ANALOGBIAS1_IMIN_VGA_SHIFT                          4

/* RX3 :: Rx_analogBias1 :: imax_interp [03:03] */
#define RX3_RX_ANALOGBIAS1_IMAX_INTERP_MASK                        0x0008
#define RX3_RX_ANALOGBIAS1_IMAX_INTERP_ALIGN                       0
#define RX3_RX_ANALOGBIAS1_IMAX_INTERP_BITS                        1
#define RX3_RX_ANALOGBIAS1_IMAX_INTERP_SHIFT                       3

/* RX3 :: Rx_analogBias1 :: imode_interp [02:02] */
#define RX3_RX_ANALOGBIAS1_IMODE_INTERP_MASK                       0x0004
#define RX3_RX_ANALOGBIAS1_IMODE_INTERP_ALIGN                      0
#define RX3_RX_ANALOGBIAS1_IMODE_INTERP_BITS                       1
#define RX3_RX_ANALOGBIAS1_IMODE_INTERP_SHIFT                      2

/* RX3 :: Rx_analogBias1 :: imin_interp [01:01] */
#define RX3_RX_ANALOGBIAS1_IMIN_INTERP_MASK                        0x0002
#define RX3_RX_ANALOGBIAS1_IMIN_INTERP_ALIGN                       0
#define RX3_RX_ANALOGBIAS1_IMIN_INTERP_BITS                        1
#define RX3_RX_ANALOGBIAS1_IMIN_INTERP_SHIFT                       1

/* RX3 :: Rx_analogBias1 :: imax_vcm [00:00] */
#define RX3_RX_ANALOGBIAS1_IMAX_VCM_MASK                           0x0001
#define RX3_RX_ANALOGBIAS1_IMAX_VCM_ALIGN                          0
#define RX3_RX_ANALOGBIAS1_IMAX_VCM_BITS                           1
#define RX3_RX_ANALOGBIAS1_IMAX_VCM_SHIFT                          0


/****************************************************************************
 * RX3 :: Rx_analogBias2
 ***************************************************************************/
/* RX3 :: Rx_analogBias2 :: en_clk16 [15:15] */
#define RX3_RX_ANALOGBIAS2_EN_CLK16_MASK                           0x8000
#define RX3_RX_ANALOGBIAS2_EN_CLK16_ALIGN                          0
#define RX3_RX_ANALOGBIAS2_EN_CLK16_BITS                           1
#define RX3_RX_ANALOGBIAS2_EN_CLK16_SHIFT                          15

/* RX3 :: Rx_analogBias2 :: pd_ch_p1 [14:14] */
#define RX3_RX_ANALOGBIAS2_PD_CH_P1_MASK                           0x4000
#define RX3_RX_ANALOGBIAS2_PD_CH_P1_ALIGN                          0
#define RX3_RX_ANALOGBIAS2_PD_CH_P1_BITS                           1
#define RX3_RX_ANALOGBIAS2_PD_CH_P1_SHIFT                          14

/* RX3 :: Rx_analogBias2 :: en_vcctrl [13:13] */
#define RX3_RX_ANALOGBIAS2_EN_VCCTRL_MASK                          0x2000
#define RX3_RX_ANALOGBIAS2_EN_VCCTRL_ALIGN                         0
#define RX3_RX_ANALOGBIAS2_EN_VCCTRL_BITS                          1
#define RX3_RX_ANALOGBIAS2_EN_VCCTRL_SHIFT                         13

/* RX3 :: Rx_analogBias2 :: en_dfeclk [12:12] */
#define RX3_RX_ANALOGBIAS2_EN_DFECLK_MASK                          0x1000
#define RX3_RX_ANALOGBIAS2_EN_DFECLK_ALIGN                         0
#define RX3_RX_ANALOGBIAS2_EN_DFECLK_BITS                          1
#define RX3_RX_ANALOGBIAS2_EN_DFECLK_SHIFT                         12

/* RX3 :: Rx_analogBias2 :: en_hgain [11:11] */
#define RX3_RX_ANALOGBIAS2_EN_HGAIN_MASK                           0x0800
#define RX3_RX_ANALOGBIAS2_EN_HGAIN_ALIGN                          0
#define RX3_RX_ANALOGBIAS2_EN_HGAIN_BITS                           1
#define RX3_RX_ANALOGBIAS2_EN_HGAIN_SHIFT                          11

/* RX3 :: Rx_analogBias2 :: en_dfeckpwr [10:10] */
#define RX3_RX_ANALOGBIAS2_EN_DFECKPWR_MASK                        0x0400
#define RX3_RX_ANALOGBIAS2_EN_DFECKPWR_ALIGN                       0
#define RX3_RX_ANALOGBIAS2_EN_DFECKPWR_BITS                        1
#define RX3_RX_ANALOGBIAS2_EN_DFECKPWR_SHIFT                       10

/* RX3 :: Rx_analogBias2 :: offset_pd [09:09] */
#define RX3_RX_ANALOGBIAS2_OFFSET_PD_MASK                          0x0200
#define RX3_RX_ANALOGBIAS2_OFFSET_PD_ALIGN                         0
#define RX3_RX_ANALOGBIAS2_OFFSET_PD_BITS                          1
#define RX3_RX_ANALOGBIAS2_OFFSET_PD_SHIFT                         9

/* RX3 :: Rx_analogBias2 :: imax_dfetap [08:08] */
#define RX3_RX_ANALOGBIAS2_IMAX_DFETAP_MASK                        0x0100
#define RX3_RX_ANALOGBIAS2_IMAX_DFETAP_ALIGN                       0
#define RX3_RX_ANALOGBIAS2_IMAX_DFETAP_BITS                        1
#define RX3_RX_ANALOGBIAS2_IMAX_DFETAP_SHIFT                       8

/* RX3 :: Rx_analogBias2 :: imode_dfetap [07:07] */
#define RX3_RX_ANALOGBIAS2_IMODE_DFETAP_MASK                       0x0080
#define RX3_RX_ANALOGBIAS2_IMODE_DFETAP_ALIGN                      0
#define RX3_RX_ANALOGBIAS2_IMODE_DFETAP_BITS                       1
#define RX3_RX_ANALOGBIAS2_IMODE_DFETAP_SHIFT                      7

/* RX3 :: Rx_analogBias2 :: imin_dfetap [06:06] */
#define RX3_RX_ANALOGBIAS2_IMIN_DFETAP_MASK                        0x0040
#define RX3_RX_ANALOGBIAS2_IMIN_DFETAP_ALIGN                       0
#define RX3_RX_ANALOGBIAS2_IMIN_DFETAP_BITS                        1
#define RX3_RX_ANALOGBIAS2_IMIN_DFETAP_SHIFT                       6

/* RX3 :: Rx_analogBias2 :: imax_slcd2c [05:05] */
#define RX3_RX_ANALOGBIAS2_IMAX_SLCD2C_MASK                        0x0020
#define RX3_RX_ANALOGBIAS2_IMAX_SLCD2C_ALIGN                       0
#define RX3_RX_ANALOGBIAS2_IMAX_SLCD2C_BITS                        1
#define RX3_RX_ANALOGBIAS2_IMAX_SLCD2C_SHIFT                       5

/* RX3 :: Rx_analogBias2 :: imode_slcd2c [04:04] */
#define RX3_RX_ANALOGBIAS2_IMODE_SLCD2C_MASK                       0x0010
#define RX3_RX_ANALOGBIAS2_IMODE_SLCD2C_ALIGN                      0
#define RX3_RX_ANALOGBIAS2_IMODE_SLCD2C_BITS                       1
#define RX3_RX_ANALOGBIAS2_IMODE_SLCD2C_SHIFT                      4

/* RX3 :: Rx_analogBias2 :: imin_slcd2c [03:03] */
#define RX3_RX_ANALOGBIAS2_IMIN_SLCD2C_MASK                        0x0008
#define RX3_RX_ANALOGBIAS2_IMIN_SLCD2C_ALIGN                       0
#define RX3_RX_ANALOGBIAS2_IMIN_SLCD2C_BITS                        1
#define RX3_RX_ANALOGBIAS2_IMIN_SLCD2C_SHIFT                       3

/* RX3 :: Rx_analogBias2 :: imax_dfevref [02:02] */
#define RX3_RX_ANALOGBIAS2_IMAX_DFEVREF_MASK                       0x0004
#define RX3_RX_ANALOGBIAS2_IMAX_DFEVREF_ALIGN                      0
#define RX3_RX_ANALOGBIAS2_IMAX_DFEVREF_BITS                       1
#define RX3_RX_ANALOGBIAS2_IMAX_DFEVREF_SHIFT                      2

/* RX3 :: Rx_analogBias2 :: imode_dfevref [01:01] */
#define RX3_RX_ANALOGBIAS2_IMODE_DFEVREF_MASK                      0x0002
#define RX3_RX_ANALOGBIAS2_IMODE_DFEVREF_ALIGN                     0
#define RX3_RX_ANALOGBIAS2_IMODE_DFEVREF_BITS                      1
#define RX3_RX_ANALOGBIAS2_IMODE_DFEVREF_SHIFT                     1

/* RX3 :: Rx_analogBias2 :: imin_dfevref [00:00] */
#define RX3_RX_ANALOGBIAS2_IMIN_DFEVREF_MASK                       0x0001
#define RX3_RX_ANALOGBIAS2_IMIN_DFEVREF_ALIGN                      0
#define RX3_RX_ANALOGBIAS2_IMIN_DFEVREF_BITS                       1
#define RX3_RX_ANALOGBIAS2_IMIN_DFEVREF_SHIFT                      0


/****************************************************************************
 * XGXS16G_USER_RX_All
 ***************************************************************************/
/****************************************************************************
 * RX_All :: Rx_Status
 ***************************************************************************/
/* union - case sigdet_Status [15:00] */
/* RX_All :: Rx_Status :: cx4_sigdet [15:15] */
#define RX_ALL_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_MASK             0x8000
#define RX_ALL_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_ALIGN            0
#define RX_ALL_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_BITS             1
#define RX_ALL_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_SHIFT            15

/* RX_All :: Rx_Status :: reserved0 [14:13] */
#define RX_ALL_RX_STATUS_SIGDET_STATUS_RESERVED0_MASK              0x6000
#define RX_ALL_RX_STATUS_SIGDET_STATUS_RESERVED0_ALIGN             0
#define RX_ALL_RX_STATUS_SIGDET_STATUS_RESERVED0_BITS              2
#define RX_ALL_RX_STATUS_SIGDET_STATUS_RESERVED0_SHIFT             13

/* RX_All :: Rx_Status :: rxSeqDone [12:12] */
#define RX_ALL_RX_STATUS_SIGDET_STATUS_RXSEQDONE_MASK              0x1000
#define RX_ALL_RX_STATUS_SIGDET_STATUS_RXSEQDONE_ALIGN             0
#define RX_ALL_RX_STATUS_SIGDET_STATUS_RXSEQDONE_BITS              1
#define RX_ALL_RX_STATUS_SIGDET_STATUS_RXSEQDONE_SHIFT             12

/* RX_All :: Rx_Status :: rx_sigdet_ll [11:11] */
#define RX_ALL_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_MASK           0x0800
#define RX_ALL_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_ALIGN          0
#define RX_ALL_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_BITS           1
#define RX_ALL_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_SHIFT          11

/* RX_All :: Rx_Status :: cs4_sigdet_ll [10:10] */
#define RX_ALL_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_MASK          0x0400
#define RX_ALL_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_ALIGN         0
#define RX_ALL_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_BITS          1
#define RX_ALL_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_SHIFT         10

/* RX_All :: Rx_Status :: rx_reset [09:09] */
#define RX_ALL_RX_STATUS_SIGDET_STATUS_RX_RESET_MASK               0x0200
#define RX_ALL_RX_STATUS_SIGDET_STATUS_RX_RESET_ALIGN              0
#define RX_ALL_RX_STATUS_SIGDET_STATUS_RX_RESET_BITS               1
#define RX_ALL_RX_STATUS_SIGDET_STATUS_RX_RESET_SHIFT              9

/* RX_All :: Rx_Status :: rx_pwrdn [08:08] */
#define RX_ALL_RX_STATUS_SIGDET_STATUS_RX_PWRDN_MASK               0x0100
#define RX_ALL_RX_STATUS_SIGDET_STATUS_RX_PWRDN_ALIGN              0
#define RX_ALL_RX_STATUS_SIGDET_STATUS_RX_PWRDN_BITS               1
#define RX_ALL_RX_STATUS_SIGDET_STATUS_RX_PWRDN_SHIFT              8

/* RX_All :: Rx_Status :: reserved1 [07:00] */
#define RX_ALL_RX_STATUS_SIGDET_STATUS_RESERVED1_MASK              0x00ff
#define RX_ALL_RX_STATUS_SIGDET_STATUS_RESERVED1_ALIGN             0
#define RX_ALL_RX_STATUS_SIGDET_STATUS_RESERVED1_BITS              8
#define RX_ALL_RX_STATUS_SIGDET_STATUS_RESERVED1_SHIFT             0


/* union - case sync_Status [15:00] */
/* RX_All :: Rx_Status :: reserved0 [15:11] */
#define RX_ALL_RX_STATUS_SYNC_STATUS_RESERVED0_MASK                0xf800
#define RX_ALL_RX_STATUS_SYNC_STATUS_RESERVED0_ALIGN               0
#define RX_ALL_RX_STATUS_SYNC_STATUS_RESERVED0_BITS                5
#define RX_ALL_RX_STATUS_SYNC_STATUS_RESERVED0_SHIFT               11

/* RX_All :: Rx_Status :: test_acq_en [10:10] */
#define RX_ALL_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_MASK              0x0400
#define RX_ALL_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_ALIGN             0
#define RX_ALL_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_BITS              1
#define RX_ALL_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_SHIFT             10

/* RX_All :: Rx_Status :: reserved1 [09:09] */
#define RX_ALL_RX_STATUS_SYNC_STATUS_RESERVED1_MASK                0x0200
#define RX_ALL_RX_STATUS_SYNC_STATUS_RESERVED1_ALIGN               0
#define RX_ALL_RX_STATUS_SYNC_STATUS_RESERVED1_BITS                1
#define RX_ALL_RX_STATUS_SYNC_STATUS_RESERVED1_SHIFT               9

/* RX_All :: Rx_Status :: rxSeqStart [08:08] */
#define RX_ALL_RX_STATUS_SYNC_STATUS_RXSEQSTART_MASK               0x0100
#define RX_ALL_RX_STATUS_SYNC_STATUS_RXSEQSTART_ALIGN              0
#define RX_ALL_RX_STATUS_SYNC_STATUS_RXSEQSTART_BITS               1
#define RX_ALL_RX_STATUS_SYNC_STATUS_RXSEQSTART_SHIFT              8

/* RX_All :: Rx_Status :: mux_comadj_sync_status [07:07] */
#define RX_ALL_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_MASK   0x0080
#define RX_ALL_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_ALIGN  0
#define RX_ALL_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_BITS   1
#define RX_ALL_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_SHIFT  7

/* RX_All :: Rx_Status :: sync_status [06:06] */
#define RX_ALL_RX_STATUS_SYNC_STATUS_SYNC_STATUS_MASK              0x0040
#define RX_ALL_RX_STATUS_SYNC_STATUS_SYNC_STATUS_ALIGN             0
#define RX_ALL_RX_STATUS_SYNC_STATUS_SYNC_STATUS_BITS              1
#define RX_ALL_RX_STATUS_SYNC_STATUS_SYNC_STATUS_SHIFT             6

/* RX_All :: Rx_Status :: rx_sigdet [05:05] */
#define RX_ALL_RX_STATUS_SYNC_STATUS_RX_SIGDET_MASK                0x0020
#define RX_ALL_RX_STATUS_SYNC_STATUS_RX_SIGDET_ALIGN               0
#define RX_ALL_RX_STATUS_SYNC_STATUS_RX_SIGDET_BITS                1
#define RX_ALL_RX_STATUS_SYNC_STATUS_RX_SIGDET_SHIFT               5

/* RX_All :: Rx_Status :: reserved2 [04:03] */
#define RX_ALL_RX_STATUS_SYNC_STATUS_RESERVED2_MASK                0x0018
#define RX_ALL_RX_STATUS_SYNC_STATUS_RESERVED2_ALIGN               0
#define RX_ALL_RX_STATUS_SYNC_STATUS_RESERVED2_BITS                2
#define RX_ALL_RX_STATUS_SYNC_STATUS_RESERVED2_SHIFT               3

/* RX_All :: Rx_Status :: saturate_status [02:02] */
#define RX_ALL_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_MASK          0x0004
#define RX_ALL_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_ALIGN         0
#define RX_ALL_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_BITS          1
#define RX_ALL_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_SHIFT         2

/* RX_All :: Rx_Status :: cx4_sigdet [01:01] */
#define RX_ALL_RX_STATUS_SYNC_STATUS_CX4_SIGDET_MASK               0x0002
#define RX_ALL_RX_STATUS_SYNC_STATUS_CX4_SIGDET_ALIGN              0
#define RX_ALL_RX_STATUS_SYNC_STATUS_CX4_SIGDET_BITS               1
#define RX_ALL_RX_STATUS_SYNC_STATUS_CX4_SIGDET_SHIFT              1

/* RX_All :: Rx_Status :: rxSeqDone [00:00] */
#define RX_ALL_RX_STATUS_SYNC_STATUS_RXSEQDONE_MASK                0x0001
#define RX_ALL_RX_STATUS_SYNC_STATUS_RXSEQDONE_ALIGN               0
#define RX_ALL_RX_STATUS_SYNC_STATUS_RXSEQDONE_BITS                1
#define RX_ALL_RX_STATUS_SYNC_STATUS_RXSEQDONE_SHIFT               0


/* union - case rxTestSel_0 [15:00] */
/* RX_All :: Rx_Status :: reserved0 [15:10] */
#define RX_ALL_RX_STATUS_RXTESTSEL_0_RESERVED0_MASK                0xfc00
#define RX_ALL_RX_STATUS_RXTESTSEL_0_RESERVED0_ALIGN               0
#define RX_ALL_RX_STATUS_RXTESTSEL_0_RESERVED0_BITS                6
#define RX_ALL_RX_STATUS_RXTESTSEL_0_RESERVED0_SHIFT               10

/* RX_All :: Rx_Status :: indck_mode_en [09:09] */
#define RX_ALL_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_MASK            0x0200
#define RX_ALL_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_ALIGN           0
#define RX_ALL_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_BITS            1
#define RX_ALL_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_SHIFT           9

/* RX_All :: Rx_Status :: pci_mode_en [08:08] */
#define RX_ALL_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_MASK              0x0100
#define RX_ALL_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_ALIGN             0
#define RX_ALL_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_BITS              1
#define RX_ALL_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_SHIFT             8

/* RX_All :: Rx_Status :: rx_polarity [07:07] */
#define RX_ALL_RX_STATUS_RXTESTSEL_0_RX_POLARITY_MASK              0x0080
#define RX_ALL_RX_STATUS_RXTESTSEL_0_RX_POLARITY_ALIGN             0
#define RX_ALL_RX_STATUS_RXTESTSEL_0_RX_POLARITY_BITS              1
#define RX_ALL_RX_STATUS_RXTESTSEL_0_RX_POLARITY_SHIFT             7

/* RX_All :: Rx_Status :: rxpol_flip [06:06] */
#define RX_ALL_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_MASK               0x0040
#define RX_ALL_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_ALIGN              0
#define RX_ALL_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_BITS               1
#define RX_ALL_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_SHIFT              6

/* RX_All :: Rx_Status :: comma_mask [05:05] */
#define RX_ALL_RX_STATUS_RXTESTSEL_0_COMMA_MASK_MASK               0x0020
#define RX_ALL_RX_STATUS_RXTESTSEL_0_COMMA_MASK_ALIGN              0
#define RX_ALL_RX_STATUS_RXTESTSEL_0_COMMA_MASK_BITS               1
#define RX_ALL_RX_STATUS_RXTESTSEL_0_COMMA_MASK_SHIFT              5

/* RX_All :: Rx_Status :: link_en_r [04:04] */
#define RX_ALL_RX_STATUS_RXTESTSEL_0_LINK_EN_R_MASK                0x0010
#define RX_ALL_RX_STATUS_RXTESTSEL_0_LINK_EN_R_ALIGN               0
#define RX_ALL_RX_STATUS_RXTESTSEL_0_LINK_EN_R_BITS                1
#define RX_ALL_RX_STATUS_RXTESTSEL_0_LINK_EN_R_SHIFT               4

/* RX_All :: Rx_Status :: comma_adj_en [03:03] */
#define RX_ALL_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_MASK             0x0008
#define RX_ALL_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_ALIGN            0
#define RX_ALL_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_BITS             1
#define RX_ALL_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_SHIFT            3

/* RX_All :: Rx_Status :: comma_adj_en_ext [02:02] */
#define RX_ALL_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_MASK         0x0004
#define RX_ALL_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_ALIGN        0
#define RX_ALL_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_BITS         1
#define RX_ALL_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_SHIFT        2

/* RX_All :: Rx_Status :: reserved1 [01:00] */
#define RX_ALL_RX_STATUS_RXTESTSEL_0_RESERVED1_MASK                0x0003
#define RX_ALL_RX_STATUS_RXTESTSEL_0_RESERVED1_ALIGN               0
#define RX_ALL_RX_STATUS_RXTESTSEL_0_RESERVED1_BITS                2
#define RX_ALL_RX_STATUS_RXTESTSEL_0_RESERVED1_SHIFT               0


/* union - case rxTestSel_1 [15:00] */
/* RX_All :: Rx_Status :: reserved0 [15:05] */
#define RX_ALL_RX_STATUS_RXTESTSEL_1_RESERVED0_MASK                0xffe0
#define RX_ALL_RX_STATUS_RXTESTSEL_1_RESERVED0_ALIGN               0
#define RX_ALL_RX_STATUS_RXTESTSEL_1_RESERVED0_BITS                11
#define RX_ALL_RX_STATUS_RXTESTSEL_1_RESERVED0_SHIFT               5

/* RX_All :: Rx_Status :: cdrAcqDone_r2 [04:04] */
#define RX_ALL_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_MASK            0x0010
#define RX_ALL_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_ALIGN           0
#define RX_ALL_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_BITS            1
#define RX_ALL_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_SHIFT           4

/* RX_All :: Rx_Status :: freq_sel_PC [03:03] */
#define RX_ALL_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_MASK              0x0008
#define RX_ALL_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_ALIGN             0
#define RX_ALL_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_BITS              1
#define RX_ALL_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_SHIFT             3

/* RX_All :: Rx_Status :: freq_sel_SM [02:02] */
#define RX_ALL_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_MASK              0x0004
#define RX_ALL_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_ALIGN             0
#define RX_ALL_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_BITS              1
#define RX_ALL_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_SHIFT             2

/* RX_All :: Rx_Status :: integ_mode_SM [01:00] */
#define RX_ALL_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_MASK            0x0003
#define RX_ALL_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_ALIGN           0
#define RX_ALL_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_BITS            2
#define RX_ALL_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_SHIFT           0


/* union - case scale_Status [15:00] */
/* RX_All :: Rx_Status :: prop_scale [15:12] */
#define RX_ALL_RX_STATUS_SCALE_STATUS_PROP_SCALE_MASK              0xf000
#define RX_ALL_RX_STATUS_SCALE_STATUS_PROP_SCALE_ALIGN             0
#define RX_ALL_RX_STATUS_SCALE_STATUS_PROP_SCALE_BITS              4
#define RX_ALL_RX_STATUS_SCALE_STATUS_PROP_SCALE_SHIFT             12

/* RX_All :: Rx_Status :: integ_scale [11:08] */
#define RX_ALL_RX_STATUS_SCALE_STATUS_INTEG_SCALE_MASK             0x0f00
#define RX_ALL_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ALIGN            0
#define RX_ALL_RX_STATUS_SCALE_STATUS_INTEG_SCALE_BITS             4
#define RX_ALL_RX_STATUS_SCALE_STATUS_INTEG_SCALE_SHIFT            8

/* RX_All :: Rx_Status :: prop_scale_acq [07:04] */
#define RX_ALL_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_MASK          0x00f0
#define RX_ALL_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_ALIGN         0
#define RX_ALL_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_BITS          4
#define RX_ALL_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_SHIFT         4

/* RX_All :: Rx_Status :: integ_scale_acq [03:00] */
#define RX_ALL_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_MASK         0x000f
#define RX_ALL_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_ALIGN        0
#define RX_ALL_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_BITS         4
#define RX_ALL_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_SHIFT        0


/* union - case adc_CdrStatus1 [15:00] */
/* RX_All :: Rx_Status :: reserved0 [15:07] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_MASK             0xff80
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_ALIGN            0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_BITS             9
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_SHIFT            7

/* RX_All :: Rx_Status :: rxMuxCkSel [06:06] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_MASK            0x0040
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_ALIGN           0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_BITS            1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_SHIFT           6

/* RX_All :: Rx_Status :: glpbk_combo [05:05] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_MASK           0x0020
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_ALIGN          0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_BITS           1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_SHIFT          5

/* RX_All :: Rx_Status :: clockSwitchSel [04:04] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_MASK        0x0010
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_ALIGN       0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_BITS        1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_SHIFT       4

/* RX_All :: Rx_Status :: rxck_tst [03:03] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_MASK              0x0008
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_ALIGN             0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_BITS              1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_SHIFT             3

/* RX_All :: Rx_Status :: rxck_i [02:02] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_MASK                0x0004
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_ALIGN               0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_BITS                1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_SHIFT               2

/* RX_All :: Rx_Status :: refclk [01:01] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_REFCLK_MASK                0x0002
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_REFCLK_ALIGN               0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_REFCLK_BITS                1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_REFCLK_SHIFT               1

/* RX_All :: Rx_Status :: pll_bypass [00:00] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_MASK            0x0001
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_ALIGN           0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_BITS            1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_SHIFT           0


/* union - case adc_CdrStatus2 [15:00] */
/* RX_All :: Rx_Status :: reserved0 [15:06] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_MASK             0xffc0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_ALIGN            0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_BITS             10
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_SHIFT            6

/* RX_All :: Rx_Status :: rxMuxCkSel [05:05] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_MASK            0x0020
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_ALIGN           0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_BITS            1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_SHIFT           5

/* RX_All :: Rx_Status :: rxSeqStart [04:04] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_MASK            0x0010
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_ALIGN           0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_BITS            1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_SHIFT           4

/* RX_All :: Rx_Status :: reserved1 [03:01] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_MASK             0x000e
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_ALIGN            0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_BITS             3
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_SHIFT            1

/* RX_All :: Rx_Status :: rxSeqDone [00:00] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_MASK             0x0001
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_ALIGN            0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_BITS             1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_SHIFT            0


/* union - case adc_CdrStatus3 [15:00] */
/* RX_All :: Rx_Status :: reserved0 [15:04] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_MASK             0xfff0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_ALIGN            0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_BITS             12
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_SHIFT            4

/* RX_All :: Rx_Status :: rxSeqStart [03:03] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_MASK            0x0008
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_ALIGN           0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_BITS            1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_SHIFT           3

/* RX_All :: Rx_Status :: reserved1 [02:01] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_MASK             0x0006
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_ALIGN            0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_BITS             2
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_SHIFT            1

/* RX_All :: Rx_Status :: allow_increment_PC [00:00] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_MASK    0x0001
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_ALIGN   0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_BITS    1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_SHIFT   0


/* union - case adc_CdrStatus4 [15:00] */
/* RX_All :: Rx_Status :: reserved0 [15:08] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_MASK             0xff00
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_ALIGN            0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_BITS             8
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_SHIFT            8

/* RX_All :: Rx_Status :: rx_pwrdn [07:07] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_MASK              0x0080
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_ALIGN             0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_BITS              1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_SHIFT             7

/* RX_All :: Rx_Status :: freq_sel [06:06] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_MASK              0x0040
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_ALIGN             0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_BITS              1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_SHIFT             6

/* RX_All :: Rx_Status :: pll_lock_rstb [05:05] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_MASK         0x0020
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_ALIGN        0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_BITS         1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_SHIFT        5

/* RX_All :: Rx_Status :: pwrdn [04:04] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_PWRDN_MASK                 0x0010
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_PWRDN_ALIGN                0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_PWRDN_BITS                 1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_PWRDN_SHIFT                4

/* RX_All :: Rx_Status :: reserved1 [03:00] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_MASK             0x000f
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_ALIGN            0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_BITS             4
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_SHIFT            0


/* union - case adc_CdrStatus5 [15:00] */
/* RX_All :: Rx_Status :: reserved0 [15:00] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_MASK             0xffff
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_ALIGN            0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_BITS             16
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_SHIFT            0


/* union - case adc_CdrStatus6 [15:00] */
/* RX_All :: Rx_Status :: reserved0 [15:05] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_MASK             0xffe0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_ALIGN            0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_BITS             11
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_SHIFT            5

/* RX_All :: Rx_Status :: rx_reset [04:04] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_MASK              0x0010
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_ALIGN             0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_BITS              1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_SHIFT             4

/* RX_All :: Rx_Status :: rx_pwrdn [03:03] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_MASK              0x0008
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_ALIGN             0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_BITS              1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_SHIFT             3

/* RX_All :: Rx_Status :: reset_anlg [02:02] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_MASK            0x0004
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_ALIGN           0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_BITS            1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_SHIFT           2

/* RX_All :: Rx_Status :: pwrdn_rx [01:01] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_MASK              0x0002
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_ALIGN             0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_BITS              1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_SHIFT             1

/* RX_All :: Rx_Status :: pwrdn_pll [00:00] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_MASK             0x0001
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_ALIGN            0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_BITS             1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_SHIFT            0


/* union - case adc_CdrStatus7e [15:00] */
/* RX_All :: Rx_Status :: reserved0 [15:05] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_MASK            0xffe0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_ALIGN           0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_BITS            11
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_SHIFT           5

/* RX_All :: Rx_Status :: rxck0_even [04:04] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_MASK           0x0010
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_ALIGN          0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_BITS           1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_SHIFT          4

/* RX_All :: Rx_Status :: rxck1_even [03:03] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_MASK           0x0008
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_ALIGN          0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_BITS           1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_SHIFT          3

/* RX_All :: Rx_Status :: comdet_even [02:02] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_MASK          0x0004
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_ALIGN         0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_BITS          1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_SHIFT         2

/* RX_All :: Rx_Status :: en_cdet_even [01:01] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_MASK         0x0002
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_ALIGN        0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_BITS         1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_SHIFT        1

/* RX_All :: Rx_Status :: comma_adj_en_even [00:00] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_MASK    0x0001
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_ALIGN   0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_BITS    1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_SHIFT   0


/* union - case adc_CdrStatus7o [15:00] */
/* RX_All :: Rx_Status :: reserved0 [15:05] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_MASK            0xffe0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_ALIGN           0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_BITS            11
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_SHIFT           5

/* RX_All :: Rx_Status :: rxck0_odd [04:04] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_MASK            0x0010
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_ALIGN           0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_BITS            1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_SHIFT           4

/* RX_All :: Rx_Status :: rxck1_odd [03:03] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_MASK            0x0008
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_ALIGN           0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_BITS            1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_SHIFT           3

/* RX_All :: Rx_Status :: comdet_odd [02:02] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_MASK           0x0004
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_ALIGN          0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_BITS           1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_SHIFT          2

/* RX_All :: Rx_Status :: en_cdet_odd [01:01] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_MASK          0x0002
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_ALIGN         0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_BITS          1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_SHIFT         1

/* RX_All :: Rx_Status :: comma_adj_en_odd [00:00] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_MASK     0x0001
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_ALIGN    0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_BITS     1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_SHIFT    0


/* union - case adc_CdrStatus8 [15:00] */
/* RX_All :: Rx_Status :: reserved0 [15:01] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_MASK             0xfffe
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_ALIGN            0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_BITS             15
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_SHIFT            1

/* RX_All :: Rx_Status :: sigdet [00:00] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS8_SIGDET_MASK                0x0001
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS8_SIGDET_ALIGN               0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS8_SIGDET_BITS                1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS8_SIGDET_SHIFT               0


/* union - case adc_CdrStatus9 [15:00] */
/* RX_All :: Rx_Status :: reserved0 [15:00] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_MASK             0xffff
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_ALIGN            0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_BITS             16
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_SHIFT            0


/* union - case adc_CdrStatus10 [15:00] */
/* RX_All :: Rx_Status :: reserved0 [15:07] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_MASK            0xff80
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_ALIGN           0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_BITS            9
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_SHIFT           7

/* RX_All :: Rx_Status :: prbs_en [06:06] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_MASK              0x0040
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_ALIGN             0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_BITS              1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_SHIFT             6

/* RX_All :: Rx_Status :: rstb_tst [05:05] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_MASK             0x0020
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_ALIGN            0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_BITS             1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_SHIFT            5

/* RX_All :: Rx_Status :: reserved1 [04:04] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_MASK            0x0010
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_ALIGN           0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_BITS            1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_SHIFT           4

/* RX_All :: Rx_Status :: prbs_state [03:00] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_MASK           0x000f
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_ALIGN          0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_BITS           4
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_SHIFT          0


/* union - case adc_CdrStatus11 [15:00] */
/* RX_All :: Rx_Status :: reserved0 [15:00] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_MASK            0xffff
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_ALIGN           0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_BITS            16
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_SHIFT           0


/* union - case adc_CdrStatus12_1 [15:00] */
/* RX_All :: Rx_Status :: reserved0 [15:06] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_MASK          0xffc0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_ALIGN         0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_BITS          10
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_SHIFT         6

/* RX_All :: Rx_Status :: enable4 [05:05] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_MASK            0x0020
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_ALIGN           0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_BITS            1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_SHIFT           5

/* RX_All :: Rx_Status :: radr_test [04:00] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_MASK          0x001f
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_ALIGN         0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_BITS          5
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_SHIFT         0


/* union - case adc_CdrStatus12_2 [15:00] */
/* RX_All :: Rx_Status :: reserved0 [15:05] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_MASK          0xffe0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_ALIGN         0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_BITS          11
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_SHIFT         5

/* RX_All :: Rx_Status :: wadr_test [04:00] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_MASK          0x001f
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_ALIGN         0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_BITS          5
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_SHIFT         0


/* union - case adc_CdrStatus12_3 [15:00] */
/* RX_All :: Rx_Status :: reserved0 [15:06] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_MASK          0xffc0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_ALIGN         0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_BITS          10
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_SHIFT         6

/* RX_All :: Rx_Status :: rxck_66B_tmux [05:05] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_MASK      0x0020
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_ALIGN     0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_BITS      1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_SHIFT     5

/* RX_All :: Rx_Status :: rstb_66B [04:04] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_MASK           0x0010
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_ALIGN          0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_BITS           1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_SHIFT          4

/* RX_All :: Rx_Status :: prstb_66B_mux [03:03] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_MASK      0x0008
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_ALIGN     0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_BITS      1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_SHIFT     3

/* RX_All :: Rx_Status :: rxck_i66_tmux [02:02] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_MASK      0x0004
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_ALIGN     0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_BITS      1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_SHIFT     2

/* RX_All :: Rx_Status :: rstb_i66 [01:01] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_MASK           0x0002
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_ALIGN          0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_BITS           1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_SHIFT          1

/* RX_All :: Rx_Status :: prstb_i66_mux [00:00] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_MASK      0x0001
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_ALIGN     0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_BITS      1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_SHIFT     0


/* union - case adc_CdrStatus12_4 [15:00] */
/* RX_All :: Rx_Status :: reserved0 [15:04] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_MASK          0xfff0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_ALIGN         0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_BITS          12
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_SHIFT         4

/* RX_All :: Rx_Status :: rfifo_error_r [03:02] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_MASK      0x000c
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_ALIGN     0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_BITS      2
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_SHIFT     2

/* RX_All :: Rx_Status :: rfifo_unflow [01:01] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_MASK       0x0002
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_ALIGN      0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_BITS       1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_SHIFT      1

/* RX_All :: Rx_Status :: rfifo_ovflow [00:00] */
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_MASK       0x0001
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_ALIGN      0
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_BITS       1
#define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_SHIFT      0


/* union - case integ_Status [15:00] */
/* RX_All :: Rx_Status :: integ_status [15:00] */
#define RX_ALL_RX_STATUS_INTEG_STATUS_INTEG_STATUS_MASK            0xffff
#define RX_ALL_RX_STATUS_INTEG_STATUS_INTEG_STATUS_ALIGN           0
#define RX_ALL_RX_STATUS_INTEG_STATUS_INTEG_STATUS_BITS            16
#define RX_ALL_RX_STATUS_INTEG_STATUS_INTEG_STATUS_SHIFT           0


/* union - case vco_Status [15:00] */
/* RX_All :: Rx_Status :: vco_status [15:00] */
#define RX_ALL_RX_STATUS_VCO_STATUS_VCO_STATUS_MASK                0xffff
#define RX_ALL_RX_STATUS_VCO_STATUS_VCO_STATUS_ALIGN               0
#define RX_ALL_RX_STATUS_VCO_STATUS_VCO_STATUS_BITS                16
#define RX_ALL_RX_STATUS_VCO_STATUS_VCO_STATUS_SHIFT               0


/* union - case prbs_Status [15:00] */
/* RX_All :: Rx_Status :: prbs_lock [15:15] */
#define RX_ALL_RX_STATUS_PRBS_STATUS_PRBS_LOCK_MASK                0x8000
#define RX_ALL_RX_STATUS_PRBS_STATUS_PRBS_LOCK_ALIGN               0
#define RX_ALL_RX_STATUS_PRBS_STATUS_PRBS_LOCK_BITS                1
#define RX_ALL_RX_STATUS_PRBS_STATUS_PRBS_LOCK_SHIFT               15

/* RX_All :: Rx_Status :: prbs_stky [14:14] */
#define RX_ALL_RX_STATUS_PRBS_STATUS_PRBS_STKY_MASK                0x4000
#define RX_ALL_RX_STATUS_PRBS_STATUS_PRBS_STKY_ALIGN               0
#define RX_ALL_RX_STATUS_PRBS_STATUS_PRBS_STKY_BITS                1
#define RX_ALL_RX_STATUS_PRBS_STATUS_PRBS_STKY_SHIFT               14

/* RX_All :: Rx_Status :: ptbs_errors [13:00] */
#define RX_ALL_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_MASK              0x3fff
#define RX_ALL_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_ALIGN             0
#define RX_ALL_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_BITS              14
#define RX_ALL_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_SHIFT             0



/****************************************************************************
 * RX_All :: Rx_Control
 ***************************************************************************/
/* RX_All :: Rx_Control :: reserved0 [15:03] */
#define RX_ALL_RX_CONTROL_RESERVED0_MASK                           0xfff8
#define RX_ALL_RX_CONTROL_RESERVED0_ALIGN                          0
#define RX_ALL_RX_CONTROL_RESERVED0_BITS                           13
#define RX_ALL_RX_CONTROL_RESERVED0_SHIFT                          3

/* RX_All :: Rx_Control :: status_sel [02:00] */
#define RX_ALL_RX_CONTROL_STATUS_SEL_MASK                          0x0007
#define RX_ALL_RX_CONTROL_STATUS_SEL_ALIGN                         0
#define RX_ALL_RX_CONTROL_STATUS_SEL_BITS                          3
#define RX_ALL_RX_CONTROL_STATUS_SEL_SHIFT                         0
#define RX_ALL_RX_CONTROL_STATUS_SEL_sigdetStatus                  0
#define RX_ALL_RX_CONTROL_STATUS_SEL_syncStatus                    1
#define RX_ALL_RX_CONTROL_STATUS_SEL_rxTestSel                     2
#define RX_ALL_RX_CONTROL_STATUS_SEL_scaleStatus                   3
#define RX_ALL_RX_CONTROL_STATUS_SEL_adcCdrStatus                  4
#define RX_ALL_RX_CONTROL_STATUS_SEL_integStatus                   5
#define RX_ALL_RX_CONTROL_STATUS_SEL_vcoStatus                     6
#define RX_ALL_RX_CONTROL_STATUS_SEL_prbsStatus                    7


/****************************************************************************
 * RX_All :: Rx_Test
 ***************************************************************************/
/* RX_All :: Rx_Test :: sigdet_mux_SM [15:12] */
#define RX_ALL_RX_TEST_SIGDET_MUX_SM_MASK                          0xf000
#define RX_ALL_RX_TEST_SIGDET_MUX_SM_ALIGN                         0
#define RX_ALL_RX_TEST_SIGDET_MUX_SM_BITS                          4
#define RX_ALL_RX_TEST_SIGDET_MUX_SM_SHIFT                         12

/* RX_All :: Rx_Test :: reserved0 [11:09] */
#define RX_ALL_RX_TEST_RESERVED0_MASK                              0x0e00
#define RX_ALL_RX_TEST_RESERVED0_ALIGN                             0
#define RX_ALL_RX_TEST_RESERVED0_BITS                              3
#define RX_ALL_RX_TEST_RESERVED0_SHIFT                             9

/* RX_All :: Rx_Test :: tpctrl_SM [08:04] */
#define RX_ALL_RX_TEST_TPCTRL_SM_MASK                              0x01f0
#define RX_ALL_RX_TEST_TPCTRL_SM_ALIGN                             0
#define RX_ALL_RX_TEST_TPCTRL_SM_BITS                              5
#define RX_ALL_RX_TEST_TPCTRL_SM_SHIFT                             4

/* RX_All :: Rx_Test :: testMuxSelect_SM [03:00] */
#define RX_ALL_RX_TEST_TESTMUXSELECT_SM_MASK                       0x000f
#define RX_ALL_RX_TEST_TESTMUXSELECT_SM_ALIGN                      0
#define RX_ALL_RX_TEST_TESTMUXSELECT_SM_BITS                       4
#define RX_ALL_RX_TEST_TESTMUXSELECT_SM_SHIFT                      0


/****************************************************************************
 * RX_All :: Rx_Control_1G_type
 ***************************************************************************/
/* RX_All :: Rx_Control_1G_type :: fpat_md [15:15] */
#define RX_ALL_RX_CONTROL_1G_TYPE_FPAT_MD_MASK                     0x8000
#define RX_ALL_RX_CONTROL_1G_TYPE_FPAT_MD_ALIGN                    0
#define RX_ALL_RX_CONTROL_1G_TYPE_FPAT_MD_BITS                     1
#define RX_ALL_RX_CONTROL_1G_TYPE_FPAT_MD_SHIFT                    15

/* RX_All :: Rx_Control_1G_type :: pkt_count_en [14:14] */
#define RX_ALL_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_MASK                0x4000
#define RX_ALL_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_ALIGN               0
#define RX_ALL_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_BITS                1
#define RX_ALL_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_SHIFT               14

/* RX_All :: Rx_Control_1G_type :: staMuxRegDis [13:13] */
#define RX_ALL_RX_CONTROL_1G_TYPE_STAMUXREGDIS_MASK                0x2000
#define RX_ALL_RX_CONTROL_1G_TYPE_STAMUXREGDIS_ALIGN               0
#define RX_ALL_RX_CONTROL_1G_TYPE_STAMUXREGDIS_BITS                1
#define RX_ALL_RX_CONTROL_1G_TYPE_STAMUXREGDIS_SHIFT               13

/* RX_All :: Rx_Control_1G_type :: prbs_clr_dis [12:12] */
#define RX_ALL_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_MASK                0x1000
#define RX_ALL_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_ALIGN               0
#define RX_ALL_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_BITS                1
#define RX_ALL_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_SHIFT               12

/* RX_All :: Rx_Control_1G_type :: rxd_dec_sel [11:11] */
#define RX_ALL_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_MASK                 0x0800
#define RX_ALL_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_ALIGN                0
#define RX_ALL_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_BITS                 1
#define RX_ALL_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_SHIFT                11

/* RX_All :: Rx_Control_1G_type :: cgbad_tst [10:10] */
#define RX_ALL_RX_CONTROL_1G_TYPE_CGBAD_TST_MASK                   0x0400
#define RX_ALL_RX_CONTROL_1G_TYPE_CGBAD_TST_ALIGN                  0
#define RX_ALL_RX_CONTROL_1G_TYPE_CGBAD_TST_BITS                   1
#define RX_ALL_RX_CONTROL_1G_TYPE_CGBAD_TST_SHIFT                  10

/* RX_All :: Rx_Control_1G_type :: Emon_en [09:09] */
#define RX_ALL_RX_CONTROL_1G_TYPE_EMON_EN_MASK                     0x0200
#define RX_ALL_RX_CONTROL_1G_TYPE_EMON_EN_ALIGN                    0
#define RX_ALL_RX_CONTROL_1G_TYPE_EMON_EN_BITS                     1
#define RX_ALL_RX_CONTROL_1G_TYPE_EMON_EN_SHIFT                    9

/* RX_All :: Rx_Control_1G_type :: prbs_en [08:08] */
#define RX_ALL_RX_CONTROL_1G_TYPE_PRBS_EN_MASK                     0x0100
#define RX_ALL_RX_CONTROL_1G_TYPE_PRBS_EN_ALIGN                    0
#define RX_ALL_RX_CONTROL_1G_TYPE_PRBS_EN_BITS                     1
#define RX_ALL_RX_CONTROL_1G_TYPE_PRBS_EN_SHIFT                    8

/* RX_All :: Rx_Control_1G_type :: cgbad_en [07:07] */
#define RX_ALL_RX_CONTROL_1G_TYPE_CGBAD_EN_MASK                    0x0080
#define RX_ALL_RX_CONTROL_1G_TYPE_CGBAD_EN_ALIGN                   0
#define RX_ALL_RX_CONTROL_1G_TYPE_CGBAD_EN_BITS                    1
#define RX_ALL_RX_CONTROL_1G_TYPE_CGBAD_EN_SHIFT                   7

/* RX_All :: Rx_Control_1G_type :: cstretch [06:06] */
#define RX_ALL_RX_CONTROL_1G_TYPE_CSTRETCH_MASK                    0x0040
#define RX_ALL_RX_CONTROL_1G_TYPE_CSTRETCH_ALIGN                   0
#define RX_ALL_RX_CONTROL_1G_TYPE_CSTRETCH_BITS                    1
#define RX_ALL_RX_CONTROL_1G_TYPE_CSTRETCH_SHIFT                   6

/* RX_All :: Rx_Control_1G_type :: rtbi_ckflip [05:05] */
#define RX_ALL_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_MASK                 0x0020
#define RX_ALL_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_ALIGN                0
#define RX_ALL_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_BITS                 1
#define RX_ALL_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_SHIFT                5

/* RX_All :: Rx_Control_1G_type :: rtbi_flip [04:04] */
#define RX_ALL_RX_CONTROL_1G_TYPE_RTBI_FLIP_MASK                   0x0010
#define RX_ALL_RX_CONTROL_1G_TYPE_RTBI_FLIP_ALIGN                  0
#define RX_ALL_RX_CONTROL_1G_TYPE_RTBI_FLIP_BITS                   1
#define RX_ALL_RX_CONTROL_1G_TYPE_RTBI_FLIP_SHIFT                  4

/* RX_All :: Rx_Control_1G_type :: phase_sel [03:03] */
#define RX_ALL_RX_CONTROL_1G_TYPE_PHASE_SEL_MASK                   0x0008
#define RX_ALL_RX_CONTROL_1G_TYPE_PHASE_SEL_ALIGN                  0
#define RX_ALL_RX_CONTROL_1G_TYPE_PHASE_SEL_BITS                   1
#define RX_ALL_RX_CONTROL_1G_TYPE_PHASE_SEL_SHIFT                  3

/* RX_All :: Rx_Control_1G_type :: reserved0 [02:02] */
#define RX_ALL_RX_CONTROL_1G_TYPE_RESERVED0_MASK                   0x0004
#define RX_ALL_RX_CONTROL_1G_TYPE_RESERVED0_ALIGN                  0
#define RX_ALL_RX_CONTROL_1G_TYPE_RESERVED0_BITS                   1
#define RX_ALL_RX_CONTROL_1G_TYPE_RESERVED0_SHIFT                  2

/* RX_All :: Rx_Control_1G_type :: freq_sel_force [01:01] */
#define RX_ALL_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_MASK              0x0002
#define RX_ALL_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_ALIGN             0
#define RX_ALL_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_BITS              1
#define RX_ALL_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_SHIFT             1

/* RX_All :: Rx_Control_1G_type :: freq_sel [00:00] */
#define RX_ALL_RX_CONTROL_1G_TYPE_FREQ_SEL_MASK                    0x0001
#define RX_ALL_RX_CONTROL_1G_TYPE_FREQ_SEL_ALIGN                   0
#define RX_ALL_RX_CONTROL_1G_TYPE_FREQ_SEL_BITS                    1
#define RX_ALL_RX_CONTROL_1G_TYPE_FREQ_SEL_SHIFT                   0


/****************************************************************************
 * RX_All :: Rx_Astatus
 ***************************************************************************/
/* RX_All :: Rx_Astatus :: reserved0 [15:01] */
#define RX_ALL_RX_ASTATUS_RESERVED0_MASK                           0xfffe
#define RX_ALL_RX_ASTATUS_RESERVED0_ALIGN                          0
#define RX_ALL_RX_ASTATUS_RESERVED0_BITS                           15
#define RX_ALL_RX_ASTATUS_RESERVED0_SHIFT                          1

/* RX_All :: Rx_Astatus :: sigdet [00:00] */
#define RX_ALL_RX_ASTATUS_SIGDET_MASK                              0x0001
#define RX_ALL_RX_ASTATUS_SIGDET_ALIGN                             0
#define RX_ALL_RX_ASTATUS_SIGDET_BITS                              1
#define RX_ALL_RX_ASTATUS_SIGDET_SHIFT                             0


/****************************************************************************
 * RX_All :: Rx_analogBias0
 ***************************************************************************/
/* RX_All :: Rx_analogBias0 :: imode_vcm [15:15] */
#define RX_ALL_RX_ANALOGBIAS0_IMODE_VCM_MASK                       0x8000
#define RX_ALL_RX_ANALOGBIAS0_IMODE_VCM_ALIGN                      0
#define RX_ALL_RX_ANALOGBIAS0_IMODE_VCM_BITS                       1
#define RX_ALL_RX_ANALOGBIAS0_IMODE_VCM_SHIFT                      15

/* RX_All :: Rx_analogBias0 :: imin_vcm [14:14] */
#define RX_ALL_RX_ANALOGBIAS0_IMIN_VCM_MASK                        0x4000
#define RX_ALL_RX_ANALOGBIAS0_IMIN_VCM_ALIGN                       0
#define RX_ALL_RX_ANALOGBIAS0_IMIN_VCM_BITS                        1
#define RX_ALL_RX_ANALOGBIAS0_IMIN_VCM_SHIFT                       14

/* RX_All :: Rx_analogBias0 :: imax_sigdet [13:13] */
#define RX_ALL_RX_ANALOGBIAS0_IMAX_SIGDET_MASK                     0x2000
#define RX_ALL_RX_ANALOGBIAS0_IMAX_SIGDET_ALIGN                    0
#define RX_ALL_RX_ANALOGBIAS0_IMAX_SIGDET_BITS                     1
#define RX_ALL_RX_ANALOGBIAS0_IMAX_SIGDET_SHIFT                    13

/* RX_All :: Rx_analogBias0 :: imode_sigdet [12:12] */
#define RX_ALL_RX_ANALOGBIAS0_IMODE_SIGDET_MASK                    0x1000
#define RX_ALL_RX_ANALOGBIAS0_IMODE_SIGDET_ALIGN                   0
#define RX_ALL_RX_ANALOGBIAS0_IMODE_SIGDET_BITS                    1
#define RX_ALL_RX_ANALOGBIAS0_IMODE_SIGDET_SHIFT                   12

/* RX_All :: Rx_analogBias0 :: imin_sigdet [11:11] */
#define RX_ALL_RX_ANALOGBIAS0_IMIN_SIGDET_MASK                     0x0800
#define RX_ALL_RX_ANALOGBIAS0_IMIN_SIGDET_ALIGN                    0
#define RX_ALL_RX_ANALOGBIAS0_IMIN_SIGDET_BITS                     1
#define RX_ALL_RX_ANALOGBIAS0_IMIN_SIGDET_SHIFT                    11

/* RX_All :: Rx_analogBias0 :: refh_rx [10:10] */
#define RX_ALL_RX_ANALOGBIAS0_REFH_RX_MASK                         0x0400
#define RX_ALL_RX_ANALOGBIAS0_REFH_RX_ALIGN                        0
#define RX_ALL_RX_ANALOGBIAS0_REFH_RX_BITS                         1
#define RX_ALL_RX_ANALOGBIAS0_REFH_RX_SHIFT                        10

/* RX_All :: Rx_analogBias0 :: refl_rx [09:09] */
#define RX_ALL_RX_ANALOGBIAS0_REFL_RX_MASK                         0x0200
#define RX_ALL_RX_ANALOGBIAS0_REFL_RX_ALIGN                        0
#define RX_ALL_RX_ANALOGBIAS0_REFL_RX_BITS                         1
#define RX_ALL_RX_ANALOGBIAS0_REFL_RX_SHIFT                        9

/* RX_All :: Rx_analogBias0 :: tport_en [08:08] */
#define RX_ALL_RX_ANALOGBIAS0_TPORT_EN_MASK                        0x0100
#define RX_ALL_RX_ANALOGBIAS0_TPORT_EN_ALIGN                       0
#define RX_ALL_RX_ANALOGBIAS0_TPORT_EN_BITS                        1
#define RX_ALL_RX_ANALOGBIAS0_TPORT_EN_SHIFT                       8

/* RX_All :: Rx_analogBias0 :: vddr_bg [07:07] */
#define RX_ALL_RX_ANALOGBIAS0_VDDR_BG_MASK                         0x0080
#define RX_ALL_RX_ANALOGBIAS0_VDDR_BG_ALIGN                        0
#define RX_ALL_RX_ANALOGBIAS0_VDDR_BG_BITS                         1
#define RX_ALL_RX_ANALOGBIAS0_VDDR_BG_SHIFT                        7

/* RX_All :: Rx_analogBias0 :: sig_pwrdn [06:06] */
#define RX_ALL_RX_ANALOGBIAS0_SIG_PWRDN_MASK                       0x0040
#define RX_ALL_RX_ANALOGBIAS0_SIG_PWRDN_ALIGN                      0
#define RX_ALL_RX_ANALOGBIAS0_SIG_PWRDN_BITS                       1
#define RX_ALL_RX_ANALOGBIAS0_SIG_PWRDN_SHIFT                      6

/* RX_All :: Rx_analogBias0 :: offset_ctrl [05:03] */
#define RX_ALL_RX_ANALOGBIAS0_OFFSET_CTRL_MASK                     0x0038
#define RX_ALL_RX_ANALOGBIAS0_OFFSET_CTRL_ALIGN                    0
#define RX_ALL_RX_ANALOGBIAS0_OFFSET_CTRL_BITS                     3
#define RX_ALL_RX_ANALOGBIAS0_OFFSET_CTRL_SHIFT                    3

/* RX_All :: Rx_analogBias0 :: offset_sel [02:02] */
#define RX_ALL_RX_ANALOGBIAS0_OFFSET_SEL_MASK                      0x0004
#define RX_ALL_RX_ANALOGBIAS0_OFFSET_SEL_ALIGN                     0
#define RX_ALL_RX_ANALOGBIAS0_OFFSET_SEL_BITS                      1
#define RX_ALL_RX_ANALOGBIAS0_OFFSET_SEL_SHIFT                     2

/* RX_All :: Rx_analogBias0 :: reserved0 [01:00] */
#define RX_ALL_RX_ANALOGBIAS0_RESERVED0_MASK                       0x0003
#define RX_ALL_RX_ANALOGBIAS0_RESERVED0_ALIGN                      0
#define RX_ALL_RX_ANALOGBIAS0_RESERVED0_BITS                       2
#define RX_ALL_RX_ANALOGBIAS0_RESERVED0_SHIFT                      0

#define RX_ALL_RX_EQ_BOOST_EQUALIZER_CONTROL_MASK                  0x7

/****************************************************************************
 * RX_All :: Rx_analogBias1
 ***************************************************************************/
/* RX_All :: Rx_analogBias1 :: imax_clkbuf [15:15] */
#define RX_ALL_RX_ANALOGBIAS1_IMAX_CLKBUF_MASK                     0x8000
#define RX_ALL_RX_ANALOGBIAS1_IMAX_CLKBUF_ALIGN                    0
#define RX_ALL_RX_ANALOGBIAS1_IMAX_CLKBUF_BITS                     1
#define RX_ALL_RX_ANALOGBIAS1_IMAX_CLKBUF_SHIFT                    15

/* RX_All :: Rx_analogBias1 :: imode_clkbuf [14:14] */
#define RX_ALL_RX_ANALOGBIAS1_IMODE_CLKBUF_MASK                    0x4000
#define RX_ALL_RX_ANALOGBIAS1_IMODE_CLKBUF_ALIGN                   0
#define RX_ALL_RX_ANALOGBIAS1_IMODE_CLKBUF_BITS                    1
#define RX_ALL_RX_ANALOGBIAS1_IMODE_CLKBUF_SHIFT                   14

/* RX_All :: Rx_analogBias1 :: imin_clkbuf [13:13] */
#define RX_ALL_RX_ANALOGBIAS1_IMIN_CLKBUF_MASK                     0x2000
#define RX_ALL_RX_ANALOGBIAS1_IMIN_CLKBUF_ALIGN                    0
#define RX_ALL_RX_ANALOGBIAS1_IMIN_CLKBUF_BITS                     1
#define RX_ALL_RX_ANALOGBIAS1_IMIN_CLKBUF_SHIFT                    13

/* RX_All :: Rx_analogBias1 :: imax_eqfl [12:12] */
#define RX_ALL_RX_ANALOGBIAS1_IMAX_EQFL_MASK                       0x1000
#define RX_ALL_RX_ANALOGBIAS1_IMAX_EQFL_ALIGN                      0
#define RX_ALL_RX_ANALOGBIAS1_IMAX_EQFL_BITS                       1
#define RX_ALL_RX_ANALOGBIAS1_IMAX_EQFL_SHIFT                      12

/* RX_All :: Rx_analogBias1 :: imode_eqfl [11:11] */
#define RX_ALL_RX_ANALOGBIAS1_IMODE_EQFL_MASK                      0x0800
#define RX_ALL_RX_ANALOGBIAS1_IMODE_EQFL_ALIGN                     0
#define RX_ALL_RX_ANALOGBIAS1_IMODE_EQFL_BITS                      1
#define RX_ALL_RX_ANALOGBIAS1_IMODE_EQFL_SHIFT                     11

/* RX_All :: Rx_analogBias1 :: imin_eqfl [10:10] */
#define RX_ALL_RX_ANALOGBIAS1_IMIN_EQFL_MASK                       0x0400
#define RX_ALL_RX_ANALOGBIAS1_IMIN_EQFL_ALIGN                      0
#define RX_ALL_RX_ANALOGBIAS1_IMIN_EQFL_BITS                       1
#define RX_ALL_RX_ANALOGBIAS1_IMIN_EQFL_SHIFT                      10

/* RX_All :: Rx_analogBias1 :: imax_dfesum [09:09] */
#define RX_ALL_RX_ANALOGBIAS1_IMAX_DFESUM_MASK                     0x0200
#define RX_ALL_RX_ANALOGBIAS1_IMAX_DFESUM_ALIGN                    0
#define RX_ALL_RX_ANALOGBIAS1_IMAX_DFESUM_BITS                     1
#define RX_ALL_RX_ANALOGBIAS1_IMAX_DFESUM_SHIFT                    9

/* RX_All :: Rx_analogBias1 :: imode_dfesum [08:08] */
#define RX_ALL_RX_ANALOGBIAS1_IMODE_DFESUM_MASK                    0x0100
#define RX_ALL_RX_ANALOGBIAS1_IMODE_DFESUM_ALIGN                   0
#define RX_ALL_RX_ANALOGBIAS1_IMODE_DFESUM_BITS                    1
#define RX_ALL_RX_ANALOGBIAS1_IMODE_DFESUM_SHIFT                   8

/* RX_All :: Rx_analogBias1 :: imin_dfesum [07:07] */
#define RX_ALL_RX_ANALOGBIAS1_IMIN_DFESUM_MASK                     0x0080
#define RX_ALL_RX_ANALOGBIAS1_IMIN_DFESUM_ALIGN                    0
#define RX_ALL_RX_ANALOGBIAS1_IMIN_DFESUM_BITS                     1
#define RX_ALL_RX_ANALOGBIAS1_IMIN_DFESUM_SHIFT                    7

/* RX_All :: Rx_analogBias1 :: imax_vga [06:06] */
#define RX_ALL_RX_ANALOGBIAS1_IMAX_VGA_MASK                        0x0040
#define RX_ALL_RX_ANALOGBIAS1_IMAX_VGA_ALIGN                       0
#define RX_ALL_RX_ANALOGBIAS1_IMAX_VGA_BITS                        1
#define RX_ALL_RX_ANALOGBIAS1_IMAX_VGA_SHIFT                       6

/* RX_All :: Rx_analogBias1 :: imode_vga [05:05] */
#define RX_ALL_RX_ANALOGBIAS1_IMODE_VGA_MASK                       0x0020
#define RX_ALL_RX_ANALOGBIAS1_IMODE_VGA_ALIGN                      0
#define RX_ALL_RX_ANALOGBIAS1_IMODE_VGA_BITS                       1
#define RX_ALL_RX_ANALOGBIAS1_IMODE_VGA_SHIFT                      5

/* RX_All :: Rx_analogBias1 :: imin_vga [04:04] */
#define RX_ALL_RX_ANALOGBIAS1_IMIN_VGA_MASK                        0x0010
#define RX_ALL_RX_ANALOGBIAS1_IMIN_VGA_ALIGN                       0
#define RX_ALL_RX_ANALOGBIAS1_IMIN_VGA_BITS                        1
#define RX_ALL_RX_ANALOGBIAS1_IMIN_VGA_SHIFT                       4

/* RX_All :: Rx_analogBias1 :: imax_interp [03:03] */
#define RX_ALL_RX_ANALOGBIAS1_IMAX_INTERP_MASK                     0x0008
#define RX_ALL_RX_ANALOGBIAS1_IMAX_INTERP_ALIGN                    0
#define RX_ALL_RX_ANALOGBIAS1_IMAX_INTERP_BITS                     1
#define RX_ALL_RX_ANALOGBIAS1_IMAX_INTERP_SHIFT                    3

/* RX_All :: Rx_analogBias1 :: imode_interp [02:02] */
#define RX_ALL_RX_ANALOGBIAS1_IMODE_INTERP_MASK                    0x0004
#define RX_ALL_RX_ANALOGBIAS1_IMODE_INTERP_ALIGN                   0
#define RX_ALL_RX_ANALOGBIAS1_IMODE_INTERP_BITS                    1
#define RX_ALL_RX_ANALOGBIAS1_IMODE_INTERP_SHIFT                   2

/* RX_All :: Rx_analogBias1 :: imin_interp [01:01] */
#define RX_ALL_RX_ANALOGBIAS1_IMIN_INTERP_MASK                     0x0002
#define RX_ALL_RX_ANALOGBIAS1_IMIN_INTERP_ALIGN                    0
#define RX_ALL_RX_ANALOGBIAS1_IMIN_INTERP_BITS                     1
#define RX_ALL_RX_ANALOGBIAS1_IMIN_INTERP_SHIFT                    1

/* RX_All :: Rx_analogBias1 :: imax_vcm [00:00] */
#define RX_ALL_RX_ANALOGBIAS1_IMAX_VCM_MASK                        0x0001
#define RX_ALL_RX_ANALOGBIAS1_IMAX_VCM_ALIGN                       0
#define RX_ALL_RX_ANALOGBIAS1_IMAX_VCM_BITS                        1
#define RX_ALL_RX_ANALOGBIAS1_IMAX_VCM_SHIFT                       0


/****************************************************************************
 * RX_All :: Rx_analogBias2
 ***************************************************************************/
/* RX_All :: Rx_analogBias2 :: en_clk16 [15:15] */
#define RX_ALL_RX_ANALOGBIAS2_EN_CLK16_MASK                        0x8000
#define RX_ALL_RX_ANALOGBIAS2_EN_CLK16_ALIGN                       0
#define RX_ALL_RX_ANALOGBIAS2_EN_CLK16_BITS                        1
#define RX_ALL_RX_ANALOGBIAS2_EN_CLK16_SHIFT                       15

/* RX_All :: Rx_analogBias2 :: pd_ch_p1 [14:14] */
#define RX_ALL_RX_ANALOGBIAS2_PD_CH_P1_MASK                        0x4000
#define RX_ALL_RX_ANALOGBIAS2_PD_CH_P1_ALIGN                       0
#define RX_ALL_RX_ANALOGBIAS2_PD_CH_P1_BITS                        1
#define RX_ALL_RX_ANALOGBIAS2_PD_CH_P1_SHIFT                       14

/* RX_All :: Rx_analogBias2 :: en_vcctrl [13:13] */
#define RX_ALL_RX_ANALOGBIAS2_EN_VCCTRL_MASK                       0x2000
#define RX_ALL_RX_ANALOGBIAS2_EN_VCCTRL_ALIGN                      0
#define RX_ALL_RX_ANALOGBIAS2_EN_VCCTRL_BITS                       1
#define RX_ALL_RX_ANALOGBIAS2_EN_VCCTRL_SHIFT                      13

/* RX_All :: Rx_analogBias2 :: en_dfeclk [12:12] */
#define RX_ALL_RX_ANALOGBIAS2_EN_DFECLK_MASK                       0x1000
#define RX_ALL_RX_ANALOGBIAS2_EN_DFECLK_ALIGN                      0
#define RX_ALL_RX_ANALOGBIAS2_EN_DFECLK_BITS                       1
#define RX_ALL_RX_ANALOGBIAS2_EN_DFECLK_SHIFT                      12

/* RX_All :: Rx_analogBias2 :: en_hgain [11:11] */
#define RX_ALL_RX_ANALOGBIAS2_EN_HGAIN_MASK                        0x0800
#define RX_ALL_RX_ANALOGBIAS2_EN_HGAIN_ALIGN                       0
#define RX_ALL_RX_ANALOGBIAS2_EN_HGAIN_BITS                        1
#define RX_ALL_RX_ANALOGBIAS2_EN_HGAIN_SHIFT                       11

/* RX_All :: Rx_analogBias2 :: en_dfeckpwr [10:10] */
#define RX_ALL_RX_ANALOGBIAS2_EN_DFECKPWR_MASK                     0x0400
#define RX_ALL_RX_ANALOGBIAS2_EN_DFECKPWR_ALIGN                    0
#define RX_ALL_RX_ANALOGBIAS2_EN_DFECKPWR_BITS                     1
#define RX_ALL_RX_ANALOGBIAS2_EN_DFECKPWR_SHIFT                    10

/* RX_All :: Rx_analogBias2 :: offset_pd [09:09] */
#define RX_ALL_RX_ANALOGBIAS2_OFFSET_PD_MASK                       0x0200
#define RX_ALL_RX_ANALOGBIAS2_OFFSET_PD_ALIGN                      0
#define RX_ALL_RX_ANALOGBIAS2_OFFSET_PD_BITS                       1
#define RX_ALL_RX_ANALOGBIAS2_OFFSET_PD_SHIFT                      9

/* RX_All :: Rx_analogBias2 :: imax_dfetap [08:08] */
#define RX_ALL_RX_ANALOGBIAS2_IMAX_DFETAP_MASK                     0x0100
#define RX_ALL_RX_ANALOGBIAS2_IMAX_DFETAP_ALIGN                    0
#define RX_ALL_RX_ANALOGBIAS2_IMAX_DFETAP_BITS                     1
#define RX_ALL_RX_ANALOGBIAS2_IMAX_DFETAP_SHIFT                    8

/* RX_All :: Rx_analogBias2 :: imode_dfetap [07:07] */
#define RX_ALL_RX_ANALOGBIAS2_IMODE_DFETAP_MASK                    0x0080
#define RX_ALL_RX_ANALOGBIAS2_IMODE_DFETAP_ALIGN                   0
#define RX_ALL_RX_ANALOGBIAS2_IMODE_DFETAP_BITS                    1
#define RX_ALL_RX_ANALOGBIAS2_IMODE_DFETAP_SHIFT                   7

/* RX_All :: Rx_analogBias2 :: imin_dfetap [06:06] */
#define RX_ALL_RX_ANALOGBIAS2_IMIN_DFETAP_MASK                     0x0040
#define RX_ALL_RX_ANALOGBIAS2_IMIN_DFETAP_ALIGN                    0
#define RX_ALL_RX_ANALOGBIAS2_IMIN_DFETAP_BITS                     1
#define RX_ALL_RX_ANALOGBIAS2_IMIN_DFETAP_SHIFT                    6

/* RX_All :: Rx_analogBias2 :: imax_slcd2c [05:05] */
#define RX_ALL_RX_ANALOGBIAS2_IMAX_SLCD2C_MASK                     0x0020
#define RX_ALL_RX_ANALOGBIAS2_IMAX_SLCD2C_ALIGN                    0
#define RX_ALL_RX_ANALOGBIAS2_IMAX_SLCD2C_BITS                     1
#define RX_ALL_RX_ANALOGBIAS2_IMAX_SLCD2C_SHIFT                    5

/* RX_All :: Rx_analogBias2 :: imode_slcd2c [04:04] */
#define RX_ALL_RX_ANALOGBIAS2_IMODE_SLCD2C_MASK                    0x0010
#define RX_ALL_RX_ANALOGBIAS2_IMODE_SLCD2C_ALIGN                   0
#define RX_ALL_RX_ANALOGBIAS2_IMODE_SLCD2C_BITS                    1
#define RX_ALL_RX_ANALOGBIAS2_IMODE_SLCD2C_SHIFT                   4

/* RX_All :: Rx_analogBias2 :: imin_slcd2c [03:03] */
#define RX_ALL_RX_ANALOGBIAS2_IMIN_SLCD2C_MASK                     0x0008
#define RX_ALL_RX_ANALOGBIAS2_IMIN_SLCD2C_ALIGN                    0
#define RX_ALL_RX_ANALOGBIAS2_IMIN_SLCD2C_BITS                     1
#define RX_ALL_RX_ANALOGBIAS2_IMIN_SLCD2C_SHIFT                    3

/* RX_All :: Rx_analogBias2 :: imax_dfevref [02:02] */
#define RX_ALL_RX_ANALOGBIAS2_IMAX_DFEVREF_MASK                    0x0004
#define RX_ALL_RX_ANALOGBIAS2_IMAX_DFEVREF_ALIGN                   0
#define RX_ALL_RX_ANALOGBIAS2_IMAX_DFEVREF_BITS                    1
#define RX_ALL_RX_ANALOGBIAS2_IMAX_DFEVREF_SHIFT                   2

/* RX_All :: Rx_analogBias2 :: imode_dfevref [01:01] */
#define RX_ALL_RX_ANALOGBIAS2_IMODE_DFEVREF_MASK                   0x0002
#define RX_ALL_RX_ANALOGBIAS2_IMODE_DFEVREF_ALIGN                  0
#define RX_ALL_RX_ANALOGBIAS2_IMODE_DFEVREF_BITS                   1
#define RX_ALL_RX_ANALOGBIAS2_IMODE_DFEVREF_SHIFT                  1

/* RX_All :: Rx_analogBias2 :: imin_dfevref [00:00] */
#define RX_ALL_RX_ANALOGBIAS2_IMIN_DFEVREF_MASK                    0x0001
#define RX_ALL_RX_ANALOGBIAS2_IMIN_DFEVREF_ALIGN                   0
#define RX_ALL_RX_ANALOGBIAS2_IMIN_DFEVREF_BITS                    1
#define RX_ALL_RX_ANALOGBIAS2_IMIN_DFEVREF_SHIFT                   0


/****************************************************************************
 * XGXS16G_USER_XgxsBlk2
 ***************************************************************************/
/****************************************************************************
 * XgxsBlk2 :: rxLnSwap
 ***************************************************************************/
/* XgxsBlk2 :: rxLnSwap :: rx_lnswap_en [15:15] */
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_EN_MASK                        0x8000
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_EN_ALIGN                       0
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_EN_BITS                        1
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_EN_SHIFT                       15

/* XgxsBlk2 :: rxLnSwap :: rx_lnswap_force_en [14:14] */
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE_EN_MASK                  0x4000
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE_EN_ALIGN                 0
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE_EN_BITS                  1
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE_EN_SHIFT                 14

/* XgxsBlk2 :: rxLnSwap :: Qset_prog_en [13:13] */
#define XGXSBLK2_RXLNSWAP_QSET_PROG_EN_MASK                        0x2000
#define XGXSBLK2_RXLNSWAP_QSET_PROG_EN_ALIGN                       0
#define XGXSBLK2_RXLNSWAP_QSET_PROG_EN_BITS                        1
#define XGXSBLK2_RXLNSWAP_QSET_PROG_EN_SHIFT                       13

/* XgxsBlk2 :: rxLnSwap :: rx_lnswap_link_en [12:12] */
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_LINK_EN_MASK                   0x1000
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_LINK_EN_ALIGN                  0
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_LINK_EN_BITS                   1
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_LINK_EN_SHIFT                  12

/* XgxsBlk2 :: rxLnSwap :: Q0_msb [11:11] */
#define XGXSBLK2_RXLNSWAP_Q0_MSB_MASK                              0x0800
#define XGXSBLK2_RXLNSWAP_Q0_MSB_ALIGN                             0
#define XGXSBLK2_RXLNSWAP_Q0_MSB_BITS                              1
#define XGXSBLK2_RXLNSWAP_Q0_MSB_SHIFT                             11

/* XgxsBlk2 :: rxLnSwap :: Q1_msb [10:10] */
#define XGXSBLK2_RXLNSWAP_Q1_MSB_MASK                              0x0400
#define XGXSBLK2_RXLNSWAP_Q1_MSB_ALIGN                             0
#define XGXSBLK2_RXLNSWAP_Q1_MSB_BITS                              1
#define XGXSBLK2_RXLNSWAP_Q1_MSB_SHIFT                             10

/* XgxsBlk2 :: rxLnSwap :: Q2_msb [09:09] */
#define XGXSBLK2_RXLNSWAP_Q2_MSB_MASK                              0x0200
#define XGXSBLK2_RXLNSWAP_Q2_MSB_ALIGN                             0
#define XGXSBLK2_RXLNSWAP_Q2_MSB_BITS                              1
#define XGXSBLK2_RXLNSWAP_Q2_MSB_SHIFT                             9

/* XgxsBlk2 :: rxLnSwap :: Q3_msb [08:08] */
#define XGXSBLK2_RXLNSWAP_Q3_MSB_MASK                              0x0100
#define XGXSBLK2_RXLNSWAP_Q3_MSB_ALIGN                             0
#define XGXSBLK2_RXLNSWAP_Q3_MSB_BITS                              1
#define XGXSBLK2_RXLNSWAP_Q3_MSB_SHIFT                             8

/* XgxsBlk2 :: rxLnSwap :: rx_lnSwap_force0 [07:06] */
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE0_MASK                    0x00c0
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE0_ALIGN                   0
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE0_BITS                    2
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE0_SHIFT                   6

/* XgxsBlk2 :: rxLnSwap :: rx_lnSwap_force1 [05:04] */
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE1_MASK                    0x0030
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE1_ALIGN                   0
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE1_BITS                    2
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE1_SHIFT                   4

/* XgxsBlk2 :: rxLnSwap :: rx_lnSwap_force2 [03:02] */
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE2_MASK                    0x000c
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE2_ALIGN                   0
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE2_BITS                    2
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE2_SHIFT                   2

/* XgxsBlk2 :: rxLnSwap :: rx_lnSwap_force3 [01:00] */
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE3_MASK                    0x0003
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE3_ALIGN                   0
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE3_BITS                    2
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE3_SHIFT                   0


/****************************************************************************
 * XgxsBlk2 :: txLnSwap
 ***************************************************************************/
/* XgxsBlk2 :: txLnSwap :: tx_lnswap_en [15:15] */
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_EN_MASK                        0x8000
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_EN_ALIGN                       0
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_EN_BITS                        1
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_EN_SHIFT                       15

/* XgxsBlk2 :: txLnSwap :: reserved0 [14:08] */
#define XGXSBLK2_TXLNSWAP_RESERVED0_MASK                           0x7f00
#define XGXSBLK2_TXLNSWAP_RESERVED0_ALIGN                          0
#define XGXSBLK2_TXLNSWAP_RESERVED0_BITS                           7
#define XGXSBLK2_TXLNSWAP_RESERVED0_SHIFT                          8

/* XgxsBlk2 :: txLnSwap :: tx_lnSwap_force0 [07:06] */
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE0_MASK                    0x00c0
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE0_ALIGN                   0
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE0_BITS                    2
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE0_SHIFT                   6

/* XgxsBlk2 :: txLnSwap :: tx_lnSwap_force1 [05:04] */
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE1_MASK                    0x0030
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE1_ALIGN                   0
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE1_BITS                    2
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE1_SHIFT                   4

/* XgxsBlk2 :: txLnSwap :: tx_lnSwap_force2 [03:02] */
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE2_MASK                    0x000c
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE2_ALIGN                   0
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE2_BITS                    2
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE2_SHIFT                   2

/* XgxsBlk2 :: txLnSwap :: tx_lnSwap_force3 [01:00] */
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE3_MASK                    0x0003
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE3_ALIGN                   0
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE3_BITS                    2
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE3_SHIFT                   0


/****************************************************************************
 * XgxsBlk2 :: QsetLns01
 ***************************************************************************/
/* XgxsBlk2 :: QsetLns01 :: Q1 [15:08] */
#define XGXSBLK2_QSETLNS01_Q1_MASK                                 0xff00
#define XGXSBLK2_QSETLNS01_Q1_ALIGN                                0
#define XGXSBLK2_QSETLNS01_Q1_BITS                                 8
#define XGXSBLK2_QSETLNS01_Q1_SHIFT                                8

/* XgxsBlk2 :: QsetLns01 :: Q0 [07:00] */
#define XGXSBLK2_QSETLNS01_Q0_MASK                                 0x00ff
#define XGXSBLK2_QSETLNS01_Q0_ALIGN                                0
#define XGXSBLK2_QSETLNS01_Q0_BITS                                 8
#define XGXSBLK2_QSETLNS01_Q0_SHIFT                                0


/****************************************************************************
 * XgxsBlk2 :: QsetLns23
 ***************************************************************************/
/* XgxsBlk2 :: QsetLns23 :: Q3 [15:08] */
#define XGXSBLK2_QSETLNS23_Q3_MASK                                 0xff00
#define XGXSBLK2_QSETLNS23_Q3_ALIGN                                0
#define XGXSBLK2_QSETLNS23_Q3_BITS                                 8
#define XGXSBLK2_QSETLNS23_Q3_SHIFT                                8

/* XgxsBlk2 :: QsetLns23 :: Q2 [07:00] */
#define XGXSBLK2_QSETLNS23_Q2_MASK                                 0x00ff
#define XGXSBLK2_QSETLNS23_Q2_ALIGN                                0
#define XGXSBLK2_QSETLNS23_Q2_BITS                                 8
#define XGXSBLK2_QSETLNS23_Q2_SHIFT                                0


/****************************************************************************
 * XgxsBlk2 :: unicoreMode10g
 ***************************************************************************/
/* XgxsBlk2 :: unicoreMode10g :: reserved0 [15:08] */
#define XGXSBLK2_UNICOREMODE10G_RESERVED0_MASK                     0xff00
#define XGXSBLK2_UNICOREMODE10G_RESERVED0_ALIGN                    0
#define XGXSBLK2_UNICOREMODE10G_RESERVED0_BITS                     8
#define XGXSBLK2_UNICOREMODE10G_RESERVED0_SHIFT                    8

/* XgxsBlk2 :: unicoreMode10g :: unicoreMode10gHiG [07:04] */
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_MASK             0x00f0
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_ALIGN            0
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_BITS             4
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_SHIFT            4

/* XgxsBlk2 :: unicoreMode10g :: unicoreMode10gCx4 [03:00] */
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_MASK             0x000f
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_ALIGN            0
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_BITS             4
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_SHIFT            0


/****************************************************************************
 * XgxsBlk2 :: TestModeLane
 ***************************************************************************/
/* XgxsBlk2 :: TestModeLane :: reserved0 [15:02] */
#define XGXSBLK2_TESTMODELANE_RESERVED0_MASK                       0xfffc
#define XGXSBLK2_TESTMODELANE_RESERVED0_ALIGN                      0
#define XGXSBLK2_TESTMODELANE_RESERVED0_BITS                       14
#define XGXSBLK2_TESTMODELANE_RESERVED0_SHIFT                      2

/* XgxsBlk2 :: TestModeLane :: slice_selector [01:00] */
#define XGXSBLK2_TESTMODELANE_SLICE_SELECTOR_MASK                  0x0003
#define XGXSBLK2_TESTMODELANE_SLICE_SELECTOR_ALIGN                 0
#define XGXSBLK2_TESTMODELANE_SLICE_SELECTOR_BITS                  2
#define XGXSBLK2_TESTMODELANE_SLICE_SELECTOR_SHIFT                 0


/****************************************************************************
 * XgxsBlk2 :: TestModeCombo
 ***************************************************************************/
/* XgxsBlk2 :: TestModeCombo :: reserved0 [15:12] */
#define XGXSBLK2_TESTMODECOMBO_RESERVED0_MASK                      0xf000
#define XGXSBLK2_TESTMODECOMBO_RESERVED0_ALIGN                     0
#define XGXSBLK2_TESTMODECOMBO_RESERVED0_BITS                      4
#define XGXSBLK2_TESTMODECOMBO_RESERVED0_SHIFT                     12

/* XgxsBlk2 :: TestModeCombo :: test_monitor_mode2 [11:06] */
#define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE2_MASK             0x0fc0
#define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE2_ALIGN            0
#define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE2_BITS             6
#define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE2_SHIFT            6

/* XgxsBlk2 :: TestModeCombo :: test_monitor_mode1 [05:00] */
#define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE1_MASK             0x003f
#define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE1_ALIGN            0
#define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE1_BITS             6
#define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE1_SHIFT            0


/****************************************************************************
 * XgxsBlk2 :: TestModeMux
 ***************************************************************************/
/* XgxsBlk2 :: TestModeMux :: reserved0 [15:03] */
#define XGXSBLK2_TESTMODEMUX_RESERVED0_MASK                        0xfff8
#define XGXSBLK2_TESTMODEMUX_RESERVED0_ALIGN                       0
#define XGXSBLK2_TESTMODEMUX_RESERVED0_BITS                        13
#define XGXSBLK2_TESTMODEMUX_RESERVED0_SHIFT                       3

/* XgxsBlk2 :: TestModeMux :: tmux_sel [02:00] */
#define XGXSBLK2_TESTMODEMUX_TMUX_SEL_MASK                         0x0007
#define XGXSBLK2_TESTMODEMUX_TMUX_SEL_ALIGN                        0
#define XGXSBLK2_TESTMODEMUX_TMUX_SEL_BITS                         3
#define XGXSBLK2_TESTMODEMUX_TMUX_SEL_SHIFT                        0


/****************************************************************************
 * XgxsBlk2 :: cx4SigdetCnt
 ***************************************************************************/
/* XgxsBlk2 :: cx4SigdetCnt :: cx4SigdetCnt [15:00] */
#define XGXSBLK2_CX4SIGDETCNT_CX4SIGDETCNT_MASK                    0xffff
#define XGXSBLK2_CX4SIGDETCNT_CX4SIGDETCNT_ALIGN                   0
#define XGXSBLK2_CX4SIGDETCNT_CX4SIGDETCNT_BITS                    16
#define XGXSBLK2_CX4SIGDETCNT_CX4SIGDETCNT_SHIFT                   0


/****************************************************************************
 * XGXS16G_USER_GP_Status
 ***************************************************************************/
/****************************************************************************
 * GP_Status :: MiscRxStatus
 ***************************************************************************/
/* union - case statusSelect0 [15:00] */
/* GP_Status :: MiscRxStatus :: capture_NP_lh [15:15] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_MASK    0x8000
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_ALIGN   0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_BITS    1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_SHIFT   15

/* GP_Status :: MiscRxStatus :: teton_brk_link_lh [14:14] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_MASK 0x4000
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_ALIGN 0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_BITS 1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_SHIFT 14

/* GP_Status :: MiscRxStatus :: UP3_lh [13:13] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_UP3_LH_MASK           0x2000
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_UP3_LH_ALIGN          0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_UP3_LH_BITS           1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_UP3_LH_SHIFT          13

/* GP_Status :: MiscRxStatus :: MP5_lh [12:12] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MP5_LH_MASK           0x1000
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MP5_LH_ALIGN          0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MP5_LH_BITS           1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MP5_LH_SHIFT          12

/* GP_Status :: MiscRxStatus :: nonMatchingOUI_lh [11:11] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_MASK 0x0800
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_ALIGN 0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_BITS 1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_SHIFT 11

/* GP_Status :: MiscRxStatus :: matchingOUI_msb_lh [10:10] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_MASK 0x0400
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_ALIGN 0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_BITS 1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_SHIFT 10

/* GP_Status :: MiscRxStatus :: matchingOUI_lsb_lh [09:09] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_MASK 0x0200
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_ALIGN 0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_BITS 1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_SHIFT 9

/* GP_Status :: MiscRxStatus :: invalidSeq_lh [08:08] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_MASK    0x0100
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_ALIGN   0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_BITS    1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_SHIFT   8

/* GP_Status :: MiscRxStatus :: nullMP_lh [07:07] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_MASK        0x0080
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_ALIGN       0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_BITS        1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_SHIFT       7

/* GP_Status :: MiscRxStatus :: remotePhyMP_lh [06:06] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_MASK   0x0040
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_ALIGN  0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_BITS   1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_SHIFT  6

/* GP_Status :: MiscRxStatus :: nonMatchingMP_lh [05:05] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_MASK 0x0020
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_ALIGN 0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_BITS 1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_SHIFT 5

/* GP_Status :: MiscRxStatus :: over1gMP_lh [04:04] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_MASK      0x0010
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_ALIGN     0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_BITS      1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_SHIFT     4

/* GP_Status :: MiscRxStatus :: rx_config_is_0_lh [03:03] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_MASK 0x0008
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_ALIGN 0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_BITS 1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_SHIFT 3

/* GP_Status :: MiscRxStatus :: np_toggle_err_lh [02:02] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_MASK 0x0004
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_ALIGN 0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_BITS 1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_SHIFT 2

/* GP_Status :: MiscRxStatus :: mr_np_lh [01:01] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_MASK         0x0002
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_ALIGN        0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_BITS         1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_SHIFT        1

/* GP_Status :: MiscRxStatus :: mr_bp_lh [00:00] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_MASK         0x0001
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_ALIGN        0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_BITS         1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_SHIFT        0


/* union - case statusSelect1 [15:00] */
/* GP_Status :: MiscRxStatus :: reserved0 [15:04] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT1_RESERVED0_MASK        0xfff0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT1_RESERVED0_ALIGN       0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT1_RESERVED0_BITS        12
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT1_RESERVED0_SHIFT       4

/* GP_Status :: MiscRxStatus :: np_count [03:00] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_MASK         0x000f
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_ALIGN        0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_BITS         4
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_SHIFT        0


/* union - case statusSelect2 [15:00] */
/* GP_Status :: MiscRxStatus :: reserved0 [15:06] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_RESERVED0_MASK        0xffc0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_RESERVED0_ALIGN       0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_RESERVED0_BITS        10
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_RESERVED0_SHIFT       6

/* GP_Status :: MiscRxStatus :: remote_phy_enable [05:05] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_MASK 0x0020
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_ALIGN 0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_BITS 1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_SHIFT 5

/* GP_Status :: MiscRxStatus :: det_teton_mode [04:04] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_MASK   0x0010
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_ALIGN  0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_BITS   1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_SHIFT  4

/* GP_Status :: MiscRxStatus :: cu_linkdown [03:03] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_MASK      0x0008
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_ALIGN     0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_BITS      1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_SHIFT     3

/* GP_Status :: MiscRxStatus :: cu_resolution_error [02:02] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_MASK 0x0004
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_ALIGN 0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_BITS 1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_SHIFT 2

/* GP_Status :: MiscRxStatus :: remotePhy_autosel [01:01] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_MASK 0x0002
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_ALIGN 0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_BITS 1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_SHIFT 1

/* GP_Status :: MiscRxStatus :: rx_config_isNot_0_lh [00:00] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_MASK 0x0001
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_ALIGN 0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_BITS 1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_SHIFT 0



/****************************************************************************
 * GP_Status :: xgxsStatus0
 ***************************************************************************/
/* GP_Status :: xgxsStatus0 :: status_en [15:15] */
#define GP_STATUS_XGXSSTATUS0_STATUS_EN_MASK                       0x8000
#define GP_STATUS_XGXSSTATUS0_STATUS_EN_ALIGN                      0
#define GP_STATUS_XGXSSTATUS0_STATUS_EN_BITS                       1
#define GP_STATUS_XGXSSTATUS0_STATUS_EN_SHIFT                      15

/* GP_Status :: xgxsStatus0 :: reserved0 [14:14] */
#define GP_STATUS_XGXSSTATUS0_RESERVED0_MASK                       0x4000
#define GP_STATUS_XGXSSTATUS0_RESERVED0_ALIGN                      0
#define GP_STATUS_XGXSSTATUS0_RESERVED0_BITS                       1
#define GP_STATUS_XGXSSTATUS0_RESERVED0_SHIFT                      14

/* GP_Status :: xgxsStatus0 :: tx_remote_fault [13:13] */
#define GP_STATUS_XGXSSTATUS0_TX_REMOTE_FAULT_MASK                 0x2000
#define GP_STATUS_XGXSSTATUS0_TX_REMOTE_FAULT_ALIGN                0
#define GP_STATUS_XGXSSTATUS0_TX_REMOTE_FAULT_BITS                 1
#define GP_STATUS_XGXSSTATUS0_TX_REMOTE_FAULT_SHIFT                13

/* GP_Status :: xgxsStatus0 :: rx_remote_fault [12:12] */
#define GP_STATUS_XGXSSTATUS0_RX_REMOTE_FAULT_MASK                 0x1000
#define GP_STATUS_XGXSSTATUS0_RX_REMOTE_FAULT_ALIGN                0
#define GP_STATUS_XGXSSTATUS0_RX_REMOTE_FAULT_BITS                 1
#define GP_STATUS_XGXSSTATUS0_RX_REMOTE_FAULT_SHIFT                12

/* GP_Status :: xgxsStatus0 :: txpll_lock [11:11] */
#define GP_STATUS_XGXSSTATUS0_TXPLL_LOCK_MASK                      0x0800
#define GP_STATUS_XGXSSTATUS0_TXPLL_LOCK_ALIGN                     0
#define GP_STATUS_XGXSSTATUS0_TXPLL_LOCK_BITS                      1
#define GP_STATUS_XGXSSTATUS0_TXPLL_LOCK_SHIFT                     11

/* GP_Status :: xgxsStatus0 :: txd_fifo_err [10:10] */
#define GP_STATUS_XGXSSTATUS0_TXD_FIFO_ERR_MASK                    0x0400
#define GP_STATUS_XGXSSTATUS0_TXD_FIFO_ERR_ALIGN                   0
#define GP_STATUS_XGXSSTATUS0_TXD_FIFO_ERR_BITS                    1
#define GP_STATUS_XGXSSTATUS0_TXD_FIFO_ERR_SHIFT                   10

/* GP_Status :: xgxsStatus0 :: sequencer_done [09:09] */
#define GP_STATUS_XGXSSTATUS0_SEQUENCER_DONE_MASK                  0x0200
#define GP_STATUS_XGXSSTATUS0_SEQUENCER_DONE_ALIGN                 0
#define GP_STATUS_XGXSSTATUS0_SEQUENCER_DONE_BITS                  1
#define GP_STATUS_XGXSSTATUS0_SEQUENCER_DONE_SHIFT                 9

/* GP_Status :: xgxsStatus0 :: sequencer_pass [08:08] */
#define GP_STATUS_XGXSSTATUS0_SEQUENCER_PASS_MASK                  0x0100
#define GP_STATUS_XGXSSTATUS0_SEQUENCER_PASS_ALIGN                 0
#define GP_STATUS_XGXSSTATUS0_SEQUENCER_PASS_BITS                  1
#define GP_STATUS_XGXSSTATUS0_SEQUENCER_PASS_SHIFT                 8

/* GP_Status :: xgxsStatus0 :: rxferr [07:04] */
#define GP_STATUS_XGXSSTATUS0_RXFERR_MASK                          0x00f0
#define GP_STATUS_XGXSSTATUS0_RXFERR_ALIGN                         0
#define GP_STATUS_XGXSSTATUS0_RXFERR_BITS                          4
#define GP_STATUS_XGXSSTATUS0_RXFERR_SHIFT                         4

/* GP_Status :: xgxsStatus0 :: pll_mode_afe [03:03] */
#define GP_STATUS_XGXSSTATUS0_PLL_MODE_AFE_MASK                    0x0008
#define GP_STATUS_XGXSSTATUS0_PLL_MODE_AFE_ALIGN                   0
#define GP_STATUS_XGXSSTATUS0_PLL_MODE_AFE_BITS                    1
#define GP_STATUS_XGXSSTATUS0_PLL_MODE_AFE_SHIFT                   3

/* GP_Status :: xgxsStatus0 :: ckcmp_unflow [02:02] */
#define GP_STATUS_XGXSSTATUS0_CKCMP_UNFLOW_MASK                    0x0004
#define GP_STATUS_XGXSSTATUS0_CKCMP_UNFLOW_ALIGN                   0
#define GP_STATUS_XGXSSTATUS0_CKCMP_UNFLOW_BITS                    1
#define GP_STATUS_XGXSSTATUS0_CKCMP_UNFLOW_SHIFT                   2

/* GP_Status :: xgxsStatus0 :: ckcmp_ovflow [01:01] */
#define GP_STATUS_XGXSSTATUS0_CKCMP_OVFLOW_MASK                    0x0002
#define GP_STATUS_XGXSSTATUS0_CKCMP_OVFLOW_ALIGN                   0
#define GP_STATUS_XGXSSTATUS0_CKCMP_OVFLOW_BITS                    1
#define GP_STATUS_XGXSSTATUS0_CKCMP_OVFLOW_SHIFT                   1

/* GP_Status :: xgxsStatus0 :: skew_status [00:00] */
#define GP_STATUS_XGXSSTATUS0_SKEW_STATUS_MASK                     0x0001
#define GP_STATUS_XGXSSTATUS0_SKEW_STATUS_ALIGN                    0
#define GP_STATUS_XGXSSTATUS0_SKEW_STATUS_BITS                     1
#define GP_STATUS_XGXSSTATUS0_SKEW_STATUS_SHIFT                    0


/****************************************************************************
 * GP_Status :: xgxsStatus1
 ***************************************************************************/
/* GP_Status :: xgxsStatus1 :: mode_10g_tx [15:12] */
#define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_MASK                     0xf000
#define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_ALIGN                    0
#define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_BITS                     4
#define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_SHIFT                    12
#define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_XGXS                     0
#define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_XGXG_nCC                 1
#define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_Indlanes                 6
#define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_PCI                      7
#define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_XGXS_nLQ                 8
#define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_XGXS_nLQnCC              9
#define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_PBypass                  10
#define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_PBypass_nDSK             11
#define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_ComboCoreMode            12
#define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_Clocks_off               15

/* GP_Status :: xgxsStatus1 :: serdesMode_en_tx [11:11] */
#define GP_STATUS_XGXSSTATUS1_SERDESMODE_EN_TX_MASK                0x0800
#define GP_STATUS_XGXSSTATUS1_SERDESMODE_EN_TX_ALIGN               0
#define GP_STATUS_XGXSSTATUS1_SERDESMODE_EN_TX_BITS                1
#define GP_STATUS_XGXSSTATUS1_SERDESMODE_EN_TX_SHIFT               11

/* GP_Status :: xgxsStatus1 :: sgmii_mode [10:10] */
#define GP_STATUS_XGXSSTATUS1_SGMII_MODE_MASK                      0x0400
#define GP_STATUS_XGXSSTATUS1_SGMII_MODE_ALIGN                     0
#define GP_STATUS_XGXSSTATUS1_SGMII_MODE_BITS                      1
#define GP_STATUS_XGXSSTATUS1_SGMII_MODE_SHIFT                     10

/* GP_Status :: xgxsStatus1 :: link10g [09:09] */
#define GP_STATUS_XGXSSTATUS1_LINK10G_MASK                         0x0200
#define GP_STATUS_XGXSSTATUS1_LINK10G_ALIGN                        0
#define GP_STATUS_XGXSSTATUS1_LINK10G_BITS                         1
#define GP_STATUS_XGXSSTATUS1_LINK10G_SHIFT                        9

/* GP_Status :: xgxsStatus1 :: linkstat [08:08] */
#define GP_STATUS_XGXSSTATUS1_LINKSTAT_MASK                        0x0100
#define GP_STATUS_XGXSSTATUS1_LINKSTAT_ALIGN                       0
#define GP_STATUS_XGXSSTATUS1_LINKSTAT_BITS                        1
#define GP_STATUS_XGXSSTATUS1_LINKSTAT_SHIFT                       8

/* GP_Status :: xgxsStatus1 :: autoneg_complete [07:07] */
#define GP_STATUS_XGXSSTATUS1_AUTONEG_COMPLETE_MASK                0x0080
#define GP_STATUS_XGXSSTATUS1_AUTONEG_COMPLETE_ALIGN               0
#define GP_STATUS_XGXSSTATUS1_AUTONEG_COMPLETE_BITS                1
#define GP_STATUS_XGXSSTATUS1_AUTONEG_COMPLETE_SHIFT               7

/* GP_Status :: xgxsStatus1 :: reserved0 [06:06] */
#define GP_STATUS_XGXSSTATUS1_RESERVED0_MASK                       0x0040
#define GP_STATUS_XGXSSTATUS1_RESERVED0_ALIGN                      0
#define GP_STATUS_XGXSSTATUS1_RESERVED0_BITS                       1
#define GP_STATUS_XGXSSTATUS1_RESERVED0_SHIFT                      6

/* GP_Status :: xgxsStatus1 :: pll_mode_afe [05:04] */
#define GP_STATUS_XGXSSTATUS1_PLL_MODE_AFE_MASK                    0x0030
#define GP_STATUS_XGXSSTATUS1_PLL_MODE_AFE_ALIGN                   0
#define GP_STATUS_XGXSSTATUS1_PLL_MODE_AFE_BITS                    2
#define GP_STATUS_XGXSSTATUS1_PLL_MODE_AFE_SHIFT                   4

/* GP_Status :: xgxsStatus1 :: actual_speed_ln0 [03:00] */
#define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_MASK                0x000f
#define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_ALIGN               0
#define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_BITS                4
#define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_SHIFT               0
#define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_10M              0
#define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_100M             1
#define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_1G               2
#define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_2p5G             3
#define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_5G               4
#define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_6G               5
#define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_10G_HiG          6
#define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_10G_CX4          7
#define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_12G_HiG          8
#define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_12p5G            9
#define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_13G              10
#define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_15G              11
#define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_16G              12


/****************************************************************************
 * GP_Status :: xgxsStatus2
 ***************************************************************************/
/* GP_Status :: xgxsStatus2 :: gpwrdwn_rx [15:12] */
#define GP_STATUS_XGXSSTATUS2_GPWRDWN_RX_MASK                      0xf000
#define GP_STATUS_XGXSSTATUS2_GPWRDWN_RX_ALIGN                     0
#define GP_STATUS_XGXSSTATUS2_GPWRDWN_RX_BITS                      4
#define GP_STATUS_XGXSSTATUS2_GPWRDWN_RX_SHIFT                     12

/* GP_Status :: xgxsStatus2 :: gpwrdwn_tx [11:08] */
#define GP_STATUS_XGXSSTATUS2_GPWRDWN_TX_MASK                      0x0f00
#define GP_STATUS_XGXSSTATUS2_GPWRDWN_TX_ALIGN                     0
#define GP_STATUS_XGXSSTATUS2_GPWRDWN_TX_BITS                      4
#define GP_STATUS_XGXSSTATUS2_GPWRDWN_TX_SHIFT                     8

/* GP_Status :: xgxsStatus2 :: freq_sel_rx [07:04] */
#define GP_STATUS_XGXSSTATUS2_FREQ_SEL_RX_MASK                     0x00f0
#define GP_STATUS_XGXSSTATUS2_FREQ_SEL_RX_ALIGN                    0
#define GP_STATUS_XGXSSTATUS2_FREQ_SEL_RX_BITS                     4
#define GP_STATUS_XGXSSTATUS2_FREQ_SEL_RX_SHIFT                    4

/* GP_Status :: xgxsStatus2 :: freq_sel_tx [03:00] */
#define GP_STATUS_XGXSSTATUS2_FREQ_SEL_TX_MASK                     0x000f
#define GP_STATUS_XGXSSTATUS2_FREQ_SEL_TX_ALIGN                    0
#define GP_STATUS_XGXSSTATUS2_FREQ_SEL_TX_BITS                     4
#define GP_STATUS_XGXSSTATUS2_FREQ_SEL_TX_SHIFT                    0


/****************************************************************************
 * GP_Status :: Status1000X1
 ***************************************************************************/
/* GP_Status :: Status1000X1 :: txfifo_err_detected [15:15] */
#define GP_STATUS_STATUS1000X1_TXFIFO_ERR_DETECTED_MASK            0x8000
#define GP_STATUS_STATUS1000X1_TXFIFO_ERR_DETECTED_ALIGN           0
#define GP_STATUS_STATUS1000X1_TXFIFO_ERR_DETECTED_BITS            1
#define GP_STATUS_STATUS1000X1_TXFIFO_ERR_DETECTED_SHIFT           15

/* GP_Status :: Status1000X1 :: rxfifo_err_detected [14:14] */
#define GP_STATUS_STATUS1000X1_RXFIFO_ERR_DETECTED_MASK            0x4000
#define GP_STATUS_STATUS1000X1_RXFIFO_ERR_DETECTED_ALIGN           0
#define GP_STATUS_STATUS1000X1_RXFIFO_ERR_DETECTED_BITS            1
#define GP_STATUS_STATUS1000X1_RXFIFO_ERR_DETECTED_SHIFT           14

/* GP_Status :: Status1000X1 :: false_carrier_detected [13:13] */
#define GP_STATUS_STATUS1000X1_FALSE_CARRIER_DETECTED_MASK         0x2000
#define GP_STATUS_STATUS1000X1_FALSE_CARRIER_DETECTED_ALIGN        0
#define GP_STATUS_STATUS1000X1_FALSE_CARRIER_DETECTED_BITS         1
#define GP_STATUS_STATUS1000X1_FALSE_CARRIER_DETECTED_SHIFT        13

/* GP_Status :: Status1000X1 :: crc_err_detected [12:12] */
#define GP_STATUS_STATUS1000X1_CRC_ERR_DETECTED_MASK               0x1000
#define GP_STATUS_STATUS1000X1_CRC_ERR_DETECTED_ALIGN              0
#define GP_STATUS_STATUS1000X1_CRC_ERR_DETECTED_BITS               1
#define GP_STATUS_STATUS1000X1_CRC_ERR_DETECTED_SHIFT              12

/* GP_Status :: Status1000X1 :: tx_err_detected [11:11] */
#define GP_STATUS_STATUS1000X1_TX_ERR_DETECTED_MASK                0x0800
#define GP_STATUS_STATUS1000X1_TX_ERR_DETECTED_ALIGN               0
#define GP_STATUS_STATUS1000X1_TX_ERR_DETECTED_BITS                1
#define GP_STATUS_STATUS1000X1_TX_ERR_DETECTED_SHIFT               11

/* GP_Status :: Status1000X1 :: rx_err_detected [10:10] */
#define GP_STATUS_STATUS1000X1_RX_ERR_DETECTED_MASK                0x0400
#define GP_STATUS_STATUS1000X1_RX_ERR_DETECTED_ALIGN               0
#define GP_STATUS_STATUS1000X1_RX_ERR_DETECTED_BITS                1
#define GP_STATUS_STATUS1000X1_RX_ERR_DETECTED_SHIFT               10

/* GP_Status :: Status1000X1 :: carrier_extend_err_detected [09:09] */
#define GP_STATUS_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_MASK    0x0200
#define GP_STATUS_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_ALIGN   0
#define GP_STATUS_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_BITS    1
#define GP_STATUS_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_SHIFT   9

/* GP_Status :: Status1000X1 :: early_end_extension_detected [08:08] */
#define GP_STATUS_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_MASK   0x0100
#define GP_STATUS_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_ALIGN  0
#define GP_STATUS_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_BITS   1
#define GP_STATUS_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_SHIFT  8

/* GP_Status :: Status1000X1 :: link_status_change [07:07] */
#define GP_STATUS_STATUS1000X1_LINK_STATUS_CHANGE_MASK             0x0080
#define GP_STATUS_STATUS1000X1_LINK_STATUS_CHANGE_ALIGN            0
#define GP_STATUS_STATUS1000X1_LINK_STATUS_CHANGE_BITS             1
#define GP_STATUS_STATUS1000X1_LINK_STATUS_CHANGE_SHIFT            7

/* GP_Status :: Status1000X1 :: pause_resolution_rxside [06:06] */
#define GP_STATUS_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_MASK        0x0040
#define GP_STATUS_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_ALIGN       0
#define GP_STATUS_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_BITS        1
#define GP_STATUS_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_SHIFT       6

/* GP_Status :: Status1000X1 :: pause_resolution_txside [05:05] */
#define GP_STATUS_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_MASK        0x0020
#define GP_STATUS_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_ALIGN       0
#define GP_STATUS_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_BITS        1
#define GP_STATUS_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_SHIFT       5

/* GP_Status :: Status1000X1 :: speed_status [04:03] */
#define GP_STATUS_STATUS1000X1_SPEED_STATUS_MASK                   0x0018
#define GP_STATUS_STATUS1000X1_SPEED_STATUS_ALIGN                  0
#define GP_STATUS_STATUS1000X1_SPEED_STATUS_BITS                   2
#define GP_STATUS_STATUS1000X1_SPEED_STATUS_SHIFT                  3

/* GP_Status :: Status1000X1 :: duplex_status [02:02] */
#define GP_STATUS_STATUS1000X1_DUPLEX_STATUS_MASK                  0x0004
#define GP_STATUS_STATUS1000X1_DUPLEX_STATUS_ALIGN                 0
#define GP_STATUS_STATUS1000X1_DUPLEX_STATUS_BITS                  1
#define GP_STATUS_STATUS1000X1_DUPLEX_STATUS_SHIFT                 2

/* GP_Status :: Status1000X1 :: link_status [01:01] */
#define GP_STATUS_STATUS1000X1_LINK_STATUS_MASK                    0x0002
#define GP_STATUS_STATUS1000X1_LINK_STATUS_ALIGN                   0
#define GP_STATUS_STATUS1000X1_LINK_STATUS_BITS                    1
#define GP_STATUS_STATUS1000X1_LINK_STATUS_SHIFT                   1

/* GP_Status :: Status1000X1 :: sgmii_mode [00:00] */
#define GP_STATUS_STATUS1000X1_SGMII_MODE_MASK                     0x0001
#define GP_STATUS_STATUS1000X1_SGMII_MODE_ALIGN                    0
#define GP_STATUS_STATUS1000X1_SGMII_MODE_BITS                     1
#define GP_STATUS_STATUS1000X1_SGMII_MODE_SHIFT                    0


/****************************************************************************
 * GP_Status :: Status1000X2
 ***************************************************************************/
/* GP_Status :: Status1000X2 :: sgmii_mode_change [15:15] */
#define GP_STATUS_STATUS1000X2_SGMII_MODE_CHANGE_MASK              0x8000
#define GP_STATUS_STATUS1000X2_SGMII_MODE_CHANGE_ALIGN             0
#define GP_STATUS_STATUS1000X2_SGMII_MODE_CHANGE_BITS              1
#define GP_STATUS_STATUS1000X2_SGMII_MODE_CHANGE_SHIFT             15

/* GP_Status :: Status1000X2 :: consistency_mismatch [14:14] */
#define GP_STATUS_STATUS1000X2_CONSISTENCY_MISMATCH_MASK           0x4000
#define GP_STATUS_STATUS1000X2_CONSISTENCY_MISMATCH_ALIGN          0
#define GP_STATUS_STATUS1000X2_CONSISTENCY_MISMATCH_BITS           1
#define GP_STATUS_STATUS1000X2_CONSISTENCY_MISMATCH_SHIFT          14

/* GP_Status :: Status1000X2 :: autoneg_resolution_err [13:13] */
#define GP_STATUS_STATUS1000X2_AUTONEG_RESOLUTION_ERR_MASK         0x2000
#define GP_STATUS_STATUS1000X2_AUTONEG_RESOLUTION_ERR_ALIGN        0
#define GP_STATUS_STATUS1000X2_AUTONEG_RESOLUTION_ERR_BITS         1
#define GP_STATUS_STATUS1000X2_AUTONEG_RESOLUTION_ERR_SHIFT        13

/* GP_Status :: Status1000X2 :: sgmii_selector_mismatch [12:12] */
#define GP_STATUS_STATUS1000X2_SGMII_SELECTOR_MISMATCH_MASK        0x1000
#define GP_STATUS_STATUS1000X2_SGMII_SELECTOR_MISMATCH_ALIGN       0
#define GP_STATUS_STATUS1000X2_SGMII_SELECTOR_MISMATCH_BITS        1
#define GP_STATUS_STATUS1000X2_SGMII_SELECTOR_MISMATCH_SHIFT       12

/* GP_Status :: Status1000X2 :: sync_status_fail [11:11] */
#define GP_STATUS_STATUS1000X2_SYNC_STATUS_FAIL_MASK               0x0800
#define GP_STATUS_STATUS1000X2_SYNC_STATUS_FAIL_ALIGN              0
#define GP_STATUS_STATUS1000X2_SYNC_STATUS_FAIL_BITS               1
#define GP_STATUS_STATUS1000X2_SYNC_STATUS_FAIL_SHIFT              11

/* GP_Status :: Status1000X2 :: sync_status_ok [10:10] */
#define GP_STATUS_STATUS1000X2_SYNC_STATUS_OK_MASK                 0x0400
#define GP_STATUS_STATUS1000X2_SYNC_STATUS_OK_ALIGN                0
#define GP_STATUS_STATUS1000X2_SYNC_STATUS_OK_BITS                 1
#define GP_STATUS_STATUS1000X2_SYNC_STATUS_OK_SHIFT                10

/* GP_Status :: Status1000X2 :: rudi_c [09:09] */
#define GP_STATUS_STATUS1000X2_RUDI_C_MASK                         0x0200
#define GP_STATUS_STATUS1000X2_RUDI_C_ALIGN                        0
#define GP_STATUS_STATUS1000X2_RUDI_C_BITS                         1
#define GP_STATUS_STATUS1000X2_RUDI_C_SHIFT                        9

/* GP_Status :: Status1000X2 :: rudi_I [08:08] */
#define GP_STATUS_STATUS1000X2_RUDI_I_MASK                         0x0100
#define GP_STATUS_STATUS1000X2_RUDI_I_ALIGN                        0
#define GP_STATUS_STATUS1000X2_RUDI_I_BITS                         1
#define GP_STATUS_STATUS1000X2_RUDI_I_SHIFT                        8

/* GP_Status :: Status1000X2 :: rudi_invalid [07:07] */
#define GP_STATUS_STATUS1000X2_RUDI_INVALID_MASK                   0x0080
#define GP_STATUS_STATUS1000X2_RUDI_INVALID_ALIGN                  0
#define GP_STATUS_STATUS1000X2_RUDI_INVALID_BITS                   1
#define GP_STATUS_STATUS1000X2_RUDI_INVALID_SHIFT                  7

/* GP_Status :: Status1000X2 :: linkDown_syncLoss [06:06] */
#define GP_STATUS_STATUS1000X2_LINKDOWN_SYNCLOSS_MASK              0x0040
#define GP_STATUS_STATUS1000X2_LINKDOWN_SYNCLOSS_ALIGN             0
#define GP_STATUS_STATUS1000X2_LINKDOWN_SYNCLOSS_BITS              1
#define GP_STATUS_STATUS1000X2_LINKDOWN_SYNCLOSS_SHIFT             6

/* GP_Status :: Status1000X2 :: idle_detect_state [05:05] */
#define GP_STATUS_STATUS1000X2_IDLE_DETECT_STATE_MASK              0x0020
#define GP_STATUS_STATUS1000X2_IDLE_DETECT_STATE_ALIGN             0
#define GP_STATUS_STATUS1000X2_IDLE_DETECT_STATE_BITS              1
#define GP_STATUS_STATUS1000X2_IDLE_DETECT_STATE_SHIFT             5

/* GP_Status :: Status1000X2 :: complete_acknowledge_state [04:04] */
#define GP_STATUS_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_MASK     0x0010
#define GP_STATUS_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_ALIGN    0
#define GP_STATUS_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_BITS     1
#define GP_STATUS_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_SHIFT    4

/* GP_Status :: Status1000X2 :: acknowledge_detect_state [03:03] */
#define GP_STATUS_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_MASK       0x0008
#define GP_STATUS_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_ALIGN      0
#define GP_STATUS_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_BITS       1
#define GP_STATUS_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_SHIFT      3

/* GP_Status :: Status1000X2 :: ability_detect_state [02:02] */
#define GP_STATUS_STATUS1000X2_ABILITY_DETECT_STATE_MASK           0x0004
#define GP_STATUS_STATUS1000X2_ABILITY_DETECT_STATE_ALIGN          0
#define GP_STATUS_STATUS1000X2_ABILITY_DETECT_STATE_BITS           1
#define GP_STATUS_STATUS1000X2_ABILITY_DETECT_STATE_SHIFT          2

/* union - case anError [01:01] */
/* GP_Status :: Status1000X2 :: an_error_state [01:01] */
#define GP_STATUS_STATUS1000X2_ANERROR_AN_ERROR_STATE_MASK         0x0002
#define GP_STATUS_STATUS1000X2_ANERROR_AN_ERROR_STATE_ALIGN        0
#define GP_STATUS_STATUS1000X2_ANERROR_AN_ERROR_STATE_BITS         1
#define GP_STATUS_STATUS1000X2_ANERROR_AN_ERROR_STATE_SHIFT        1


/* union - case anDisableLink [01:01] */
/* GP_Status :: Status1000X2 :: an_disable_link_ok_state [01:01] */
#define GP_STATUS_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_MASK 0x0002
#define GP_STATUS_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_ALIGN 0
#define GP_STATUS_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_BITS 1
#define GP_STATUS_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_SHIFT 1


/* GP_Status :: Status1000X2 :: an_enable_state [00:00] */
#define GP_STATUS_STATUS1000X2_AN_ENABLE_STATE_MASK                0x0001
#define GP_STATUS_STATUS1000X2_AN_ENABLE_STATE_ALIGN               0
#define GP_STATUS_STATUS1000X2_AN_ENABLE_STATE_BITS                1
#define GP_STATUS_STATUS1000X2_AN_ENABLE_STATE_SHIFT               0


/****************************************************************************
 * GP_Status :: Status1000X3
 ***************************************************************************/
/* GP_Status :: Status1000X3 :: reserved0 [15:13] */
#define GP_STATUS_STATUS1000X3_RESERVED0_MASK                      0xe000
#define GP_STATUS_STATUS1000X3_RESERVED0_ALIGN                     0
#define GP_STATUS_STATUS1000X3_RESERVED0_BITS                      3
#define GP_STATUS_STATUS1000X3_RESERVED0_SHIFT                     13

/* GP_Status :: Status1000X3 :: pd_park_an [12:12] */
#define GP_STATUS_STATUS1000X3_PD_PARK_AN_MASK                     0x1000
#define GP_STATUS_STATUS1000X3_PD_PARK_AN_ALIGN                    0
#define GP_STATUS_STATUS1000X3_PD_PARK_AN_BITS                     1
#define GP_STATUS_STATUS1000X3_PD_PARK_AN_SHIFT                    12

/* GP_Status :: Status1000X3 :: remotePhy_autosel [11:11] */
#define GP_STATUS_STATUS1000X3_REMOTEPHY_AUTOSEL_MASK              0x0800
#define GP_STATUS_STATUS1000X3_REMOTEPHY_AUTOSEL_ALIGN             0
#define GP_STATUS_STATUS1000X3_REMOTEPHY_AUTOSEL_BITS              1
#define GP_STATUS_STATUS1000X3_REMOTEPHY_AUTOSEL_SHIFT             11

/* GP_Status :: Status1000X3 :: latch_linkdown [10:10] */
#define GP_STATUS_STATUS1000X3_LATCH_LINKDOWN_MASK                 0x0400
#define GP_STATUS_STATUS1000X3_LATCH_LINKDOWN_ALIGN                0
#define GP_STATUS_STATUS1000X3_LATCH_LINKDOWN_BITS                 1
#define GP_STATUS_STATUS1000X3_LATCH_LINKDOWN_SHIFT                10

/* GP_Status :: Status1000X3 :: sd_filter [09:09] */
#define GP_STATUS_STATUS1000X3_SD_FILTER_MASK                      0x0200
#define GP_STATUS_STATUS1000X3_SD_FILTER_ALIGN                     0
#define GP_STATUS_STATUS1000X3_SD_FILTER_BITS                      1
#define GP_STATUS_STATUS1000X3_SD_FILTER_SHIFT                     9

/* GP_Status :: Status1000X3 :: sd_mux [08:08] */
#define GP_STATUS_STATUS1000X3_SD_MUX_MASK                         0x0100
#define GP_STATUS_STATUS1000X3_SD_MUX_ALIGN                        0
#define GP_STATUS_STATUS1000X3_SD_MUX_BITS                         1
#define GP_STATUS_STATUS1000X3_SD_MUX_SHIFT                        8

/* GP_Status :: Status1000X3 :: sd_filter_chg [07:07] */
#define GP_STATUS_STATUS1000X3_SD_FILTER_CHG_MASK                  0x0080
#define GP_STATUS_STATUS1000X3_SD_FILTER_CHG_ALIGN                 0
#define GP_STATUS_STATUS1000X3_SD_FILTER_CHG_BITS                  1
#define GP_STATUS_STATUS1000X3_SD_FILTER_CHG_SHIFT                 7

/* GP_Status :: Status1000X3 :: reserved1 [06:00] */
#define GP_STATUS_STATUS1000X3_RESERVED1_MASK                      0x007f
#define GP_STATUS_STATUS1000X3_RESERVED1_ALIGN                     0
#define GP_STATUS_STATUS1000X3_RESERVED1_BITS                      7
#define GP_STATUS_STATUS1000X3_RESERVED1_SHIFT                     0


/****************************************************************************
 * GP_Status :: TPOUT_1
 ***************************************************************************/
/* GP_Status :: TPOUT_1 :: tpout1 [15:00] */
#define GP_STATUS_TPOUT_1_TPOUT1_MASK                              0xffff
#define GP_STATUS_TPOUT_1_TPOUT1_ALIGN                             0
#define GP_STATUS_TPOUT_1_TPOUT1_BITS                              16
#define GP_STATUS_TPOUT_1_TPOUT1_SHIFT                             0


/****************************************************************************
 * GP_Status :: TPOUT_2
 ***************************************************************************/
/* GP_Status :: TPOUT_2 :: tpout2 [15:00] */
#define GP_STATUS_TPOUT_2_TPOUT2_MASK                              0xffff
#define GP_STATUS_TPOUT_2_TPOUT2_ALIGN                             0
#define GP_STATUS_TPOUT_2_TPOUT2_BITS                              16
#define GP_STATUS_TPOUT_2_TPOUT2_SHIFT                             0


/****************************************************************************
 * GP_Status :: xgxsStatus3
 ***************************************************************************/
/* GP_Status :: xgxsStatus3 :: link [15:15] */
#define GP_STATUS_XGXSSTATUS3_LINK_MASK                            0x8000
#define GP_STATUS_XGXSSTATUS3_LINK_ALIGN                           0
#define GP_STATUS_XGXSSTATUS3_LINK_BITS                            1
#define GP_STATUS_XGXSSTATUS3_LINK_SHIFT                           15

/* GP_Status :: xgxsStatus3 :: link_latchdown [14:14] */
#define GP_STATUS_XGXSSTATUS3_LINK_LATCHDOWN_MASK                  0x4000
#define GP_STATUS_XGXSSTATUS3_LINK_LATCHDOWN_ALIGN                 0
#define GP_STATUS_XGXSSTATUS3_LINK_LATCHDOWN_BITS                  1
#define GP_STATUS_XGXSSTATUS3_LINK_LATCHDOWN_SHIFT                 14

/* GP_Status :: xgxsStatus3 :: latch_linkdown_10g_o [13:13] */
#define GP_STATUS_XGXSSTATUS3_LATCH_LINKDOWN_10G_O_MASK            0x2000
#define GP_STATUS_XGXSSTATUS3_LATCH_LINKDOWN_10G_O_ALIGN           0
#define GP_STATUS_XGXSSTATUS3_LATCH_LINKDOWN_10G_O_BITS            1
#define GP_STATUS_XGXSSTATUS3_LATCH_LINKDOWN_10G_O_SHIFT           13

/* GP_Status :: xgxsStatus3 :: pd_park_an [12:12] */
#define GP_STATUS_XGXSSTATUS3_PD_PARK_AN_MASK                      0x1000
#define GP_STATUS_XGXSSTATUS3_PD_PARK_AN_ALIGN                     0
#define GP_STATUS_XGXSSTATUS3_PD_PARK_AN_BITS                      1
#define GP_STATUS_XGXSSTATUS3_PD_PARK_AN_SHIFT                     12

/* GP_Status :: xgxsStatus3 :: gpwrdwn_pll [11:11] */
#define GP_STATUS_XGXSSTATUS3_GPWRDWN_PLL_MASK                     0x0800
#define GP_STATUS_XGXSSTATUS3_GPWRDWN_PLL_ALIGN                    0
#define GP_STATUS_XGXSSTATUS3_GPWRDWN_PLL_BITS                     1
#define GP_STATUS_XGXSSTATUS3_GPWRDWN_PLL_SHIFT                    11

/* GP_Status :: xgxsStatus3 :: hcd_over_1g [10:00] */
#define GP_STATUS_XGXSSTATUS3_HCD_OVER_1G_MASK                     0x07ff
#define GP_STATUS_XGXSSTATUS3_HCD_OVER_1G_ALIGN                    0
#define GP_STATUS_XGXSSTATUS3_HCD_OVER_1G_BITS                     11
#define GP_STATUS_XGXSSTATUS3_HCD_OVER_1G_SHIFT                    0


/****************************************************************************
 * GP_Status :: x2500Status1
 ***************************************************************************/
/* GP_Status :: x2500Status1 :: hcd_over_1g_or [15:15] */
#define GP_STATUS_X2500STATUS1_HCD_OVER_1G_OR_MASK                 0x8000
#define GP_STATUS_X2500STATUS1_HCD_OVER_1G_OR_ALIGN                0
#define GP_STATUS_X2500STATUS1_HCD_OVER_1G_OR_BITS                 1
#define GP_STATUS_X2500STATUS1_HCD_OVER_1G_OR_SHIFT                15

/* GP_Status :: x2500Status1 :: latch_hcd_over_1g [14:14] */
#define GP_STATUS_X2500STATUS1_LATCH_HCD_OVER_1G_MASK              0x4000
#define GP_STATUS_X2500STATUS1_LATCH_HCD_OVER_1G_ALIGN             0
#define GP_STATUS_X2500STATUS1_LATCH_HCD_OVER_1G_BITS              1
#define GP_STATUS_X2500STATUS1_LATCH_HCD_OVER_1G_SHIFT             14

/* GP_Status :: x2500Status1 :: latchmdio [13:13] */
#define GP_STATUS_X2500STATUS1_LATCHMDIO_MASK                      0x2000
#define GP_STATUS_X2500STATUS1_LATCHMDIO_ALIGN                     0
#define GP_STATUS_X2500STATUS1_LATCHMDIO_BITS                      1
#define GP_STATUS_X2500STATUS1_LATCHMDIO_SHIFT                     13

/* GP_Status :: x2500Status1 :: s_bc_reg_rst [12:12] */
#define GP_STATUS_X2500STATUS1_S_BC_REG_RST_MASK                   0x1000
#define GP_STATUS_X2500STATUS1_S_BC_REG_RST_ALIGN                  0
#define GP_STATUS_X2500STATUS1_S_BC_REG_RST_BITS                   1
#define GP_STATUS_X2500STATUS1_S_BC_REG_RST_SHIFT                  12

/* GP_Status :: x2500Status1 :: s_wait2res [11:11] */
#define GP_STATUS_X2500STATUS1_S_WAIT2RES_MASK                     0x0800
#define GP_STATUS_X2500STATUS1_S_WAIT2RES_ALIGN                    0
#define GP_STATUS_X2500STATUS1_S_WAIT2RES_BITS                     1
#define GP_STATUS_X2500STATUS1_S_WAIT2RES_SHIFT                    11

/* GP_Status :: x2500Status1 :: s_wait30ms [10:10] */
#define GP_STATUS_X2500STATUS1_S_WAIT30MS_MASK                     0x0400
#define GP_STATUS_X2500STATUS1_S_WAIT30MS_ALIGN                    0
#define GP_STATUS_X2500STATUS1_S_WAIT30MS_BITS                     1
#define GP_STATUS_X2500STATUS1_S_WAIT30MS_SHIFT                    10

/* GP_Status :: x2500Status1 :: s_clockswit [09:09] */
#define GP_STATUS_X2500STATUS1_S_CLOCKSWIT_MASK                    0x0200
#define GP_STATUS_X2500STATUS1_S_CLOCKSWIT_ALIGN                   0
#define GP_STATUS_X2500STATUS1_S_CLOCKSWIT_BITS                    1
#define GP_STATUS_X2500STATUS1_S_CLOCKSWIT_SHIFT                   9

/* GP_Status :: x2500Status1 :: s_pllswit [08:08] */
#define GP_STATUS_X2500STATUS1_S_PLLSWIT_MASK                      0x0100
#define GP_STATUS_X2500STATUS1_S_PLLSWIT_ALIGN                     0
#define GP_STATUS_X2500STATUS1_S_PLLSWIT_BITS                      1
#define GP_STATUS_X2500STATUS1_S_PLLSWIT_SHIFT                     8

/* GP_Status :: x2500Status1 :: s_wait4link [07:07] */
#define GP_STATUS_X2500STATUS1_S_WAIT4LINK_MASK                    0x0080
#define GP_STATUS_X2500STATUS1_S_WAIT4LINK_ALIGN                   0
#define GP_STATUS_X2500STATUS1_S_WAIT4LINK_BITS                    1
#define GP_STATUS_X2500STATUS1_S_WAIT4LINK_SHIFT                   7

/* GP_Status :: x2500Status1 :: s_complete [06:06] */
#define GP_STATUS_X2500STATUS1_S_COMPLETE_MASK                     0x0040
#define GP_STATUS_X2500STATUS1_S_COMPLETE_ALIGN                    0
#define GP_STATUS_X2500STATUS1_S_COMPLETE_BITS                     1
#define GP_STATUS_X2500STATUS1_S_COMPLETE_SHIFT                    6

/* GP_Status :: x2500Status1 :: s_lostlink [05:05] */
#define GP_STATUS_X2500STATUS1_S_LOSTLINK_MASK                     0x0020
#define GP_STATUS_X2500STATUS1_S_LOSTLINK_ALIGN                    0
#define GP_STATUS_X2500STATUS1_S_LOSTLINK_BITS                     1
#define GP_STATUS_X2500STATUS1_S_LOSTLINK_SHIFT                    5

/* GP_Status :: x2500Status1 :: s_dead [04:04] */
#define GP_STATUS_X2500STATUS1_S_DEAD_MASK                         0x0010
#define GP_STATUS_X2500STATUS1_S_DEAD_ALIGN                        0
#define GP_STATUS_X2500STATUS1_S_DEAD_BITS                         1
#define GP_STATUS_X2500STATUS1_S_DEAD_SHIFT                        4

/* GP_Status :: x2500Status1 :: fail_cnt [03:00] */
#define GP_STATUS_X2500STATUS1_FAIL_CNT_MASK                       0x000f
#define GP_STATUS_X2500STATUS1_FAIL_CNT_ALIGN                      0
#define GP_STATUS_X2500STATUS1_FAIL_CNT_BITS                       4
#define GP_STATUS_X2500STATUS1_FAIL_CNT_SHIFT                      0


/****************************************************************************
 * GP_Status :: topANStatus1
 ***************************************************************************/
/* GP_Status :: topANStatus1 :: reserved0 [15:14] */
#define GP_STATUS_TOPANSTATUS1_RESERVED0_MASK                      0xc000
#define GP_STATUS_TOPANSTATUS1_RESERVED0_ALIGN                     0
#define GP_STATUS_TOPANSTATUS1_RESERVED0_BITS                      2
#define GP_STATUS_TOPANSTATUS1_RESERVED0_SHIFT                     14

/* GP_Status :: topANStatus1 :: actual_speed [13:08] */
#define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_MASK                   0x3f00
#define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_ALIGN                  0
#define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_BITS                   6
#define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_SHIFT                  8

/* GP_Status :: topANStatus1 :: pause_resolution_rxside [07:07] */
#define GP_STATUS_TOPANSTATUS1_PAUSE_RESOLUTION_RXSIDE_MASK        0x0080
#define GP_STATUS_TOPANSTATUS1_PAUSE_RESOLUTION_RXSIDE_ALIGN       0
#define GP_STATUS_TOPANSTATUS1_PAUSE_RESOLUTION_RXSIDE_BITS        1
#define GP_STATUS_TOPANSTATUS1_PAUSE_RESOLUTION_RXSIDE_SHIFT       7

/* GP_Status :: topANStatus1 :: pause_resolution_txside [06:06] */
#define GP_STATUS_TOPANSTATUS1_PAUSE_RESOLUTION_TXSIDE_MASK        0x0040
#define GP_STATUS_TOPANSTATUS1_PAUSE_RESOLUTION_TXSIDE_ALIGN       0
#define GP_STATUS_TOPANSTATUS1_PAUSE_RESOLUTION_TXSIDE_BITS        1
#define GP_STATUS_TOPANSTATUS1_PAUSE_RESOLUTION_TXSIDE_SHIFT       6

/* GP_Status :: topANStatus1 :: cl73_lp_np_BAM_able [05:05] */
#define GP_STATUS_TOPANSTATUS1_CL73_LP_NP_BAM_ABLE_MASK            0x0020
#define GP_STATUS_TOPANSTATUS1_CL73_LP_NP_BAM_ABLE_ALIGN           0
#define GP_STATUS_TOPANSTATUS1_CL73_LP_NP_BAM_ABLE_BITS            1
#define GP_STATUS_TOPANSTATUS1_CL73_LP_NP_BAM_ABLE_SHIFT           5

/* GP_Status :: topANStatus1 :: cl73_mr_lp_autoneg_able [04:04] */
#define GP_STATUS_TOPANSTATUS1_CL73_MR_LP_AUTONEG_ABLE_MASK        0x0010
#define GP_STATUS_TOPANSTATUS1_CL73_MR_LP_AUTONEG_ABLE_ALIGN       0
#define GP_STATUS_TOPANSTATUS1_CL73_MR_LP_AUTONEG_ABLE_BITS        1
#define GP_STATUS_TOPANSTATUS1_CL73_MR_LP_AUTONEG_ABLE_SHIFT       4

/* GP_Status :: topANStatus1 :: duplex_status [03:03] */
#define GP_STATUS_TOPANSTATUS1_DUPLEX_STATUS_MASK                  0x0008
#define GP_STATUS_TOPANSTATUS1_DUPLEX_STATUS_ALIGN                 0
#define GP_STATUS_TOPANSTATUS1_DUPLEX_STATUS_BITS                  1
#define GP_STATUS_TOPANSTATUS1_DUPLEX_STATUS_SHIFT                 3

/* GP_Status :: topANStatus1 :: link_status [02:02] */
#define GP_STATUS_TOPANSTATUS1_LINK_STATUS_MASK                    0x0004
#define GP_STATUS_TOPANSTATUS1_LINK_STATUS_ALIGN                   0
#define GP_STATUS_TOPANSTATUS1_LINK_STATUS_BITS                    1
#define GP_STATUS_TOPANSTATUS1_LINK_STATUS_SHIFT                   2

/* GP_Status :: topANStatus1 :: cl37_autoneg_complete [01:01] */
#define GP_STATUS_TOPANSTATUS1_CL37_AUTONEG_COMPLETE_MASK          0x0002
#define GP_STATUS_TOPANSTATUS1_CL37_AUTONEG_COMPLETE_ALIGN         0
#define GP_STATUS_TOPANSTATUS1_CL37_AUTONEG_COMPLETE_BITS          1
#define GP_STATUS_TOPANSTATUS1_CL37_AUTONEG_COMPLETE_SHIFT         1

/* GP_Status :: topANStatus1 :: cl73_autoneg_complete [00:00] */
#define GP_STATUS_TOPANSTATUS1_CL73_AUTONEG_COMPLETE_MASK          0x0001
#define GP_STATUS_TOPANSTATUS1_CL73_AUTONEG_COMPLETE_ALIGN         0
#define GP_STATUS_TOPANSTATUS1_CL73_AUTONEG_COMPLETE_BITS          1
#define GP_STATUS_TOPANSTATUS1_CL73_AUTONEG_COMPLETE_SHIFT         0


/****************************************************************************
 * GP_Status :: LP_UP1
 ***************************************************************************/
/* GP_Status :: LP_UP1 :: reserved0 [15:11] */
#define GP_STATUS_LP_UP1_RESERVED0_MASK                            0xf800
#define GP_STATUS_LP_UP1_RESERVED0_ALIGN                           0
#define GP_STATUS_LP_UP1_RESERVED0_BITS                            5
#define GP_STATUS_LP_UP1_RESERVED0_SHIFT                           11

/* GP_Status :: LP_UP1 :: dataRate_rsvd [10:10] */
#define GP_STATUS_LP_UP1_DATARATE_RSVD_MASK                        0x0400
#define GP_STATUS_LP_UP1_DATARATE_RSVD_ALIGN                       0
#define GP_STATUS_LP_UP1_DATARATE_RSVD_BITS                        1
#define GP_STATUS_LP_UP1_DATARATE_RSVD_SHIFT                       10

/* GP_Status :: LP_UP1 :: dataRate_16GX4 [09:09] */
#define GP_STATUS_LP_UP1_DATARATE_16GX4_MASK                       0x0200
#define GP_STATUS_LP_UP1_DATARATE_16GX4_ALIGN                      0
#define GP_STATUS_LP_UP1_DATARATE_16GX4_BITS                       1
#define GP_STATUS_LP_UP1_DATARATE_16GX4_SHIFT                      9

/* GP_Status :: LP_UP1 :: dataRate_15GX4 [08:08] */
#define GP_STATUS_LP_UP1_DATARATE_15GX4_MASK                       0x0100
#define GP_STATUS_LP_UP1_DATARATE_15GX4_ALIGN                      0
#define GP_STATUS_LP_UP1_DATARATE_15GX4_BITS                       1
#define GP_STATUS_LP_UP1_DATARATE_15GX4_SHIFT                      8

/* GP_Status :: LP_UP1 :: dataRate_13GX4 [07:07] */
#define GP_STATUS_LP_UP1_DATARATE_13GX4_MASK                       0x0080
#define GP_STATUS_LP_UP1_DATARATE_13GX4_ALIGN                      0
#define GP_STATUS_LP_UP1_DATARATE_13GX4_BITS                       1
#define GP_STATUS_LP_UP1_DATARATE_13GX4_SHIFT                      7

/* GP_Status :: LP_UP1 :: dataRate_12p5GX4 [06:06] */
#define GP_STATUS_LP_UP1_DATARATE_12P5GX4_MASK                     0x0040
#define GP_STATUS_LP_UP1_DATARATE_12P5GX4_ALIGN                    0
#define GP_STATUS_LP_UP1_DATARATE_12P5GX4_BITS                     1
#define GP_STATUS_LP_UP1_DATARATE_12P5GX4_SHIFT                    6

/* GP_Status :: LP_UP1 :: dataRate_12GX4 [05:05] */
#define GP_STATUS_LP_UP1_DATARATE_12GX4_MASK                       0x0020
#define GP_STATUS_LP_UP1_DATARATE_12GX4_ALIGN                      0
#define GP_STATUS_LP_UP1_DATARATE_12GX4_BITS                       1
#define GP_STATUS_LP_UP1_DATARATE_12GX4_SHIFT                      5

/* GP_Status :: LP_UP1 :: dataRate_10GCX4 [04:04] */
#define GP_STATUS_LP_UP1_DATARATE_10GCX4_MASK                      0x0010
#define GP_STATUS_LP_UP1_DATARATE_10GCX4_ALIGN                     0
#define GP_STATUS_LP_UP1_DATARATE_10GCX4_BITS                      1
#define GP_STATUS_LP_UP1_DATARATE_10GCX4_SHIFT                     4

/* GP_Status :: LP_UP1 :: dataRate_10GX4 [03:03] */
#define GP_STATUS_LP_UP1_DATARATE_10GX4_MASK                       0x0008
#define GP_STATUS_LP_UP1_DATARATE_10GX4_ALIGN                      0
#define GP_STATUS_LP_UP1_DATARATE_10GX4_BITS                       1
#define GP_STATUS_LP_UP1_DATARATE_10GX4_SHIFT                      3

/* GP_Status :: LP_UP1 :: dataRate_6GX4 [02:02] */
#define GP_STATUS_LP_UP1_DATARATE_6GX4_MASK                        0x0004
#define GP_STATUS_LP_UP1_DATARATE_6GX4_ALIGN                       0
#define GP_STATUS_LP_UP1_DATARATE_6GX4_BITS                        1
#define GP_STATUS_LP_UP1_DATARATE_6GX4_SHIFT                       2

/* GP_Status :: LP_UP1 :: dataRate_5GX4 [01:01] */
#define GP_STATUS_LP_UP1_DATARATE_5GX4_MASK                        0x0002
#define GP_STATUS_LP_UP1_DATARATE_5GX4_ALIGN                       0
#define GP_STATUS_LP_UP1_DATARATE_5GX4_BITS                        1
#define GP_STATUS_LP_UP1_DATARATE_5GX4_SHIFT                       1

/* GP_Status :: LP_UP1 :: dataRate_2p5GX1 [00:00] */
#define GP_STATUS_LP_UP1_DATARATE_2P5GX1_MASK                      0x0001
#define GP_STATUS_LP_UP1_DATARATE_2P5GX1_ALIGN                     0
#define GP_STATUS_LP_UP1_DATARATE_2P5GX1_BITS                      1
#define GP_STATUS_LP_UP1_DATARATE_2P5GX1_SHIFT                     0


/****************************************************************************
 * GP_Status :: LP_UP2
 ***************************************************************************/
/* GP_Status :: LP_UP2 :: reserved0 [15:11] */
#define GP_STATUS_LP_UP2_RESERVED0_MASK                            0xf800
#define GP_STATUS_LP_UP2_RESERVED0_ALIGN                           0
#define GP_STATUS_LP_UP2_RESERVED0_BITS                            5
#define GP_STATUS_LP_UP2_RESERVED0_SHIFT                           11

/* GP_Status :: LP_UP2 :: valid [10:10] */
#define GP_STATUS_LP_UP2_VALID_MASK                                0x0400
#define GP_STATUS_LP_UP2_VALID_ALIGN                               0
#define GP_STATUS_LP_UP2_VALID_BITS                                1
#define GP_STATUS_LP_UP2_VALID_SHIFT                               10

/* GP_Status :: LP_UP2 :: preemphasis [09:06] */
#define GP_STATUS_LP_UP2_PREEMPHASIS_MASK                          0x03c0
#define GP_STATUS_LP_UP2_PREEMPHASIS_ALIGN                         0
#define GP_STATUS_LP_UP2_PREEMPHASIS_BITS                          4
#define GP_STATUS_LP_UP2_PREEMPHASIS_SHIFT                         6

/* GP_Status :: LP_UP2 :: idriver [05:03] */
#define GP_STATUS_LP_UP2_IDRIVER_MASK                              0x0038
#define GP_STATUS_LP_UP2_IDRIVER_ALIGN                             0
#define GP_STATUS_LP_UP2_IDRIVER_BITS                              3
#define GP_STATUS_LP_UP2_IDRIVER_SHIFT                             3

/* GP_Status :: LP_UP2 :: ipredriver [02:00] */
#define GP_STATUS_LP_UP2_IPREDRIVER_MASK                           0x0007
#define GP_STATUS_LP_UP2_IPREDRIVER_ALIGN                          0
#define GP_STATUS_LP_UP2_IPREDRIVER_BITS                           3
#define GP_STATUS_LP_UP2_IPREDRIVER_SHIFT                          0


/****************************************************************************
 * GP_Status :: LP_UP3
 ***************************************************************************/
/* GP_Status :: LP_UP3 :: reserved0 [15:11] */
#define GP_STATUS_LP_UP3_RESERVED0_MASK                            0xf800
#define GP_STATUS_LP_UP3_RESERVED0_ALIGN                           0
#define GP_STATUS_LP_UP3_RESERVED0_BITS                            5
#define GP_STATUS_LP_UP3_RESERVED0_SHIFT                           11

/* GP_Status :: LP_UP3 :: last [10:10] */
#define GP_STATUS_LP_UP3_LAST_MASK                                 0x0400
#define GP_STATUS_LP_UP3_LAST_ALIGN                                0
#define GP_STATUS_LP_UP3_LAST_BITS                                 1
#define GP_STATUS_LP_UP3_LAST_SHIFT                                10

/* GP_Status :: LP_UP3 :: reserved1 [09:02] */
#define GP_STATUS_LP_UP3_RESERVED1_MASK                            0x03fc
#define GP_STATUS_LP_UP3_RESERVED1_ALIGN                           0
#define GP_STATUS_LP_UP3_RESERVED1_BITS                            8
#define GP_STATUS_LP_UP3_RESERVED1_SHIFT                           2

/* GP_Status :: LP_UP3 :: scramble_8B10B [01:01] */
#define GP_STATUS_LP_UP3_SCRAMBLE_8B10B_MASK                       0x0002
#define GP_STATUS_LP_UP3_SCRAMBLE_8B10B_ALIGN                      0
#define GP_STATUS_LP_UP3_SCRAMBLE_8B10B_BITS                       1
#define GP_STATUS_LP_UP3_SCRAMBLE_8B10B_SHIFT                      1

/* GP_Status :: LP_UP3 :: HiGig2 [00:00] */
#define GP_STATUS_LP_UP3_HIGIG2_MASK                               0x0001
#define GP_STATUS_LP_UP3_HIGIG2_ALIGN                              0
#define GP_STATUS_LP_UP3_HIGIG2_BITS                               1
#define GP_STATUS_LP_UP3_HIGIG2_SHIFT                              0


/****************************************************************************
 * XGXS16G_USER_AN73_pdet
 ***************************************************************************/
/****************************************************************************
 * AN73_pdet :: parDet10GStatus
 ***************************************************************************/
/* union - case pdStatus0 [15:00] */
/* AN73_pdet :: parDet10GStatus :: pd_link [15:15] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LINK_MASK           0x8000
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LINK_ALIGN          0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LINK_BITS           1
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LINK_SHIFT          15

/* AN73_pdet :: parDet10GStatus :: pd_CX4_en [14:14] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_CX4_EN_MASK         0x4000
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_CX4_EN_ALIGN        0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_CX4_EN_BITS         1
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_CX4_EN_SHIFT        14

/* AN73_pdet :: parDet10GStatus :: pd_lssFaultCount_en [13:13] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_EN_MASK 0x2000
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_EN_ALIGN 0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_EN_BITS 1
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_EN_SHIFT 13

/* AN73_pdet :: parDet10GStatus :: pd_tunePll12g [12:12] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL12G_MASK     0x1000
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL12G_ALIGN    0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL12G_BITS     1
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL12G_SHIFT    12

/* AN73_pdet :: parDet10GStatus :: pd_tunePll10g [11:11] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL10G_MASK     0x0800
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL10G_ALIGN    0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL10G_BITS     1
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL10G_SHIFT    11

/* AN73_pdet :: parDet10GStatus :: pd_txdLaneOff [10:10] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TXDLANEOFF_MASK     0x0400
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TXDLANEOFF_ALIGN    0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TXDLANEOFF_BITS     1
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TXDLANEOFF_SHIFT    10

/* AN73_pdet :: parDet10GStatus :: pd_busy [09:09] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_BUSY_MASK           0x0200
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_BUSY_ALIGN          0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_BUSY_BITS           1
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_BUSY_SHIFT          9

/* AN73_pdet :: parDet10GStatus :: pd_park_an [08:08] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_PARK_AN_MASK        0x0100
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_PARK_AN_ALIGN       0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_PARK_AN_BITS        1
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_PARK_AN_SHIFT       8

/* AN73_pdet :: parDet10GStatus :: pd_lssFaultCount [07:04] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_MASK  0x00f0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_ALIGN 0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_BITS  4
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_SHIFT 4

/* AN73_pdet :: parDet10GStatus :: rxSeqDone [03:00] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_RXSEQDONE_MASK         0x000f
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_RXSEQDONE_ALIGN        0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_RXSEQDONE_BITS         4
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_RXSEQDONE_SHIFT        0


/* union - case pdStatus1 [15:00] */
/* AN73_pdet :: parDet10GStatus :: reserved0 [15:09] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_RESERVED0_MASK         0xfe00
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_RESERVED0_ALIGN        0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_RESERVED0_BITS         7
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_RESERVED0_SHIFT        9

/* AN73_pdet :: parDet10GStatus :: fail_lh [08:08] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_FAIL_LH_MASK           0x0100
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_FAIL_LH_ALIGN          0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_FAIL_LH_BITS           1
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_FAIL_LH_SHIFT          8

/* AN73_pdet :: parDet10GStatus :: complete_lh [07:07] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_COMPLETE_LH_MASK       0x0080
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_COMPLETE_LH_ALIGN      0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_COMPLETE_LH_BITS       1
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_COMPLETE_LH_SHIFT      7

/* AN73_pdet :: parDet10GStatus :: link12gretry_lh [06:06] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_LINK12GRETRY_LH_MASK   0x0040
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_LINK12GRETRY_LH_ALIGN  0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_LINK12GRETRY_LH_BITS   1
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_LINK12GRETRY_LH_SHIFT  6

/* AN73_pdet :: parDet10GStatus :: wait4link12g_lh [05:05] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK12G_LH_MASK   0x0020
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK12G_LH_ALIGN  0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK12G_LH_BITS   1
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK12G_LH_SHIFT  5

/* AN73_pdet :: parDet10GStatus :: samplefault_lh [04:04] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_SAMPLEFAULT_LH_MASK    0x0010
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_SAMPLEFAULT_LH_ALIGN   0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_SAMPLEFAULT_LH_BITS    1
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_SAMPLEFAULT_LH_SHIFT   4

/* AN73_pdet :: parDet10GStatus :: link10gretry_lh [03:03] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_LINK10GRETRY_LH_MASK   0x0008
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_LINK10GRETRY_LH_ALIGN  0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_LINK10GRETRY_LH_BITS   1
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_LINK10GRETRY_LH_SHIFT  3

/* AN73_pdet :: parDet10GStatus :: wait4link10g_lh [02:02] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK10G_LH_MASK   0x0004
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK10G_LH_ALIGN  0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK10G_LH_BITS   1
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK10G_LH_SHIFT  2

/* AN73_pdet :: parDet10GStatus :: wait4sigdet_lh [01:01] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4SIGDET_LH_MASK    0x0002
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4SIGDET_LH_ALIGN   0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4SIGDET_LH_BITS    1
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4SIGDET_LH_SHIFT   1

/* AN73_pdet :: parDet10GStatus :: wait4lock_lh [00:00] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LOCK_LH_MASK      0x0001
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LOCK_LH_ALIGN     0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LOCK_LH_BITS      1
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LOCK_LH_SHIFT     0



/****************************************************************************
 * AN73_pdet :: parDet10GControl
 ***************************************************************************/
/* AN73_pdet :: parDet10GControl :: force_parDet10g_en [15:15] */
#define AN73_PDET_PARDET10GCONTROL_FORCE_PARDET10G_EN_MASK         0x8000
#define AN73_PDET_PARDET10GCONTROL_FORCE_PARDET10G_EN_ALIGN        0
#define AN73_PDET_PARDET10GCONTROL_FORCE_PARDET10G_EN_BITS         1
#define AN73_PDET_PARDET10GCONTROL_FORCE_PARDET10G_EN_SHIFT        15

/* AN73_pdet :: parDet10GControl :: pd_cx4_init [14:14] */
#define AN73_PDET_PARDET10GCONTROL_PD_CX4_INIT_MASK                0x4000
#define AN73_PDET_PARDET10GCONTROL_PD_CX4_INIT_ALIGN               0
#define AN73_PDET_PARDET10GCONTROL_PD_CX4_INIT_BITS                1
#define AN73_PDET_PARDET10GCONTROL_PD_CX4_INIT_SHIFT               14

/* AN73_pdet :: parDet10GControl :: pd_sw_overide [13:13] */
#define AN73_PDET_PARDET10GCONTROL_PD_SW_OVERIDE_MASK              0x2000
#define AN73_PDET_PARDET10GCONTROL_PD_SW_OVERIDE_ALIGN             0
#define AN73_PDET_PARDET10GCONTROL_PD_SW_OVERIDE_BITS              1
#define AN73_PDET_PARDET10GCONTROL_PD_SW_OVERIDE_SHIFT             13

/* AN73_pdet :: parDet10GControl :: pd_sw_busy_an [12:12] */
#define AN73_PDET_PARDET10GCONTROL_PD_SW_BUSY_AN_MASK              0x1000
#define AN73_PDET_PARDET10GCONTROL_PD_SW_BUSY_AN_ALIGN             0
#define AN73_PDET_PARDET10GCONTROL_PD_SW_BUSY_AN_BITS              1
#define AN73_PDET_PARDET10GCONTROL_PD_SW_BUSY_AN_SHIFT             12

/* AN73_pdet :: parDet10GControl :: pd_sw_CX4_en [11:11] */
#define AN73_PDET_PARDET10GCONTROL_PD_SW_CX4_EN_MASK               0x0800
#define AN73_PDET_PARDET10GCONTROL_PD_SW_CX4_EN_ALIGN              0
#define AN73_PDET_PARDET10GCONTROL_PD_SW_CX4_EN_BITS               1
#define AN73_PDET_PARDET10GCONTROL_PD_SW_CX4_EN_SHIFT              11

/* AN73_pdet :: parDet10GControl :: pd_sw_tunePll12g [10:10] */
#define AN73_PDET_PARDET10GCONTROL_PD_SW_TUNEPLL12G_MASK           0x0400
#define AN73_PDET_PARDET10GCONTROL_PD_SW_TUNEPLL12G_ALIGN          0
#define AN73_PDET_PARDET10GCONTROL_PD_SW_TUNEPLL12G_BITS           1
#define AN73_PDET_PARDET10GCONTROL_PD_SW_TUNEPLL12G_SHIFT          10

/* AN73_pdet :: parDet10GControl :: pd_sw_tunePll10g [09:09] */
#define AN73_PDET_PARDET10GCONTROL_PD_SW_TUNEPLL10G_MASK           0x0200
#define AN73_PDET_PARDET10GCONTROL_PD_SW_TUNEPLL10G_ALIGN          0
#define AN73_PDET_PARDET10GCONTROL_PD_SW_TUNEPLL10G_BITS           1
#define AN73_PDET_PARDET10GCONTROL_PD_SW_TUNEPLL10G_SHIFT          9

/* AN73_pdet :: parDet10GControl :: pd_sw_lssFaultCount_en [08:08] */
#define AN73_PDET_PARDET10GCONTROL_PD_SW_LSSFAULTCOUNT_EN_MASK     0x0100
#define AN73_PDET_PARDET10GCONTROL_PD_SW_LSSFAULTCOUNT_EN_ALIGN    0
#define AN73_PDET_PARDET10GCONTROL_PD_SW_LSSFAULTCOUNT_EN_BITS     1
#define AN73_PDET_PARDET10GCONTROL_PD_SW_LSSFAULTCOUNT_EN_SHIFT    8

/* AN73_pdet :: parDet10GControl :: pd_sw_txdOff [07:07] */
#define AN73_PDET_PARDET10GCONTROL_PD_SW_TXDOFF_MASK               0x0080
#define AN73_PDET_PARDET10GCONTROL_PD_SW_TXDOFF_ALIGN              0
#define AN73_PDET_PARDET10GCONTROL_PD_SW_TXDOFF_BITS               1
#define AN73_PDET_PARDET10GCONTROL_PD_SW_TXDOFF_SHIFT              7

/* AN73_pdet :: parDet10GControl :: pd_12g_txdOn_disable [06:06] */
#define AN73_PDET_PARDET10GCONTROL_PD_12G_TXDON_DISABLE_MASK       0x0040
#define AN73_PDET_PARDET10GCONTROL_PD_12G_TXDON_DISABLE_ALIGN      0
#define AN73_PDET_PARDET10GCONTROL_PD_12G_TXDON_DISABLE_BITS       1
#define AN73_PDET_PARDET10GCONTROL_PD_12G_TXDON_DISABLE_SHIFT      6

/* AN73_pdet :: parDet10GControl :: pd_12g_disable [05:05] */
#define AN73_PDET_PARDET10GCONTROL_PD_12G_DISABLE_MASK             0x0020
#define AN73_PDET_PARDET10GCONTROL_PD_12G_DISABLE_ALIGN            0
#define AN73_PDET_PARDET10GCONTROL_PD_12G_DISABLE_BITS             1
#define AN73_PDET_PARDET10GCONTROL_PD_12G_DISABLE_SHIFT            5

/* AN73_pdet :: parDet10GControl :: pd_10g_txdOn_disable [04:04] */
#define AN73_PDET_PARDET10GCONTROL_PD_10G_TXDON_DISABLE_MASK       0x0010
#define AN73_PDET_PARDET10GCONTROL_PD_10G_TXDON_DISABLE_ALIGN      0
#define AN73_PDET_PARDET10GCONTROL_PD_10G_TXDON_DISABLE_BITS       1
#define AN73_PDET_PARDET10GCONTROL_PD_10G_TXDON_DISABLE_SHIFT      4

/* AN73_pdet :: parDet10GControl :: pd_10g_disable [03:03] */
#define AN73_PDET_PARDET10GCONTROL_PD_10G_DISABLE_MASK             0x0008
#define AN73_PDET_PARDET10GCONTROL_PD_10G_DISABLE_ALIGN            0
#define AN73_PDET_PARDET10GCONTROL_PD_10G_DISABLE_BITS             1
#define AN73_PDET_PARDET10GCONTROL_PD_10G_DISABLE_SHIFT            3

/* AN73_pdet :: parDet10GControl :: pd_stat_sel [02:02] */
#define AN73_PDET_PARDET10GCONTROL_PD_STAT_SEL_MASK                0x0004
#define AN73_PDET_PARDET10GCONTROL_PD_STAT_SEL_ALIGN               0
#define AN73_PDET_PARDET10GCONTROL_PD_STAT_SEL_BITS                1
#define AN73_PDET_PARDET10GCONTROL_PD_STAT_SEL_SHIFT               2

/* AN73_pdet :: parDet10GControl :: pd_fast_timer_en [01:01] */
#define AN73_PDET_PARDET10GCONTROL_PD_FAST_TIMER_EN_MASK           0x0002
#define AN73_PDET_PARDET10GCONTROL_PD_FAST_TIMER_EN_ALIGN          0
#define AN73_PDET_PARDET10GCONTROL_PD_FAST_TIMER_EN_BITS           1
#define AN73_PDET_PARDET10GCONTROL_PD_FAST_TIMER_EN_SHIFT          1

/* AN73_pdet :: parDet10GControl :: parDet10g_en [00:00] */
#define AN73_PDET_PARDET10GCONTROL_PARDET10G_EN_MASK               0x0001
#define AN73_PDET_PARDET10GCONTROL_PARDET10G_EN_ALIGN              0
#define AN73_PDET_PARDET10GCONTROL_PARDET10G_EN_BITS               1
#define AN73_PDET_PARDET10GCONTROL_PARDET10G_EN_SHIFT              0


/****************************************************************************
 * AN73_pdet :: parDet10GSigDet
 ***************************************************************************/
/* AN73_pdet :: parDet10GSigDet :: pd_sd_count [15:00] */
#define AN73_PDET_PARDET10GSIGDET_PD_SD_COUNT_MASK                 0xffff
#define AN73_PDET_PARDET10GSIGDET_PD_SD_COUNT_ALIGN                0
#define AN73_PDET_PARDET10GSIGDET_PD_SD_COUNT_BITS                 16
#define AN73_PDET_PARDET10GSIGDET_PD_SD_COUNT_SHIFT                0


/****************************************************************************
 * AN73_pdet :: parDet10GLink
 ***************************************************************************/
/* AN73_pdet :: parDet10GLink :: pd_link_count [15:00] */
#define AN73_PDET_PARDET10GLINK_PD_LINK_COUNT_MASK                 0xffff
#define AN73_PDET_PARDET10GLINK_PD_LINK_COUNT_ALIGN                0
#define AN73_PDET_PARDET10GLINK_PD_LINK_COUNT_BITS                 16
#define AN73_PDET_PARDET10GLINK_PD_LINK_COUNT_SHIFT                0


/****************************************************************************
 * AN73_pdet :: parDet10GLostLink
 ***************************************************************************/
/* AN73_pdet :: parDet10GLostLink :: pd_lostlink_count [15:00] */
#define AN73_PDET_PARDET10GLOSTLINK_PD_LOSTLINK_COUNT_MASK         0xffff
#define AN73_PDET_PARDET10GLOSTLINK_PD_LOSTLINK_COUNT_ALIGN        0
#define AN73_PDET_PARDET10GLOSTLINK_PD_LOSTLINK_COUNT_BITS         16
#define AN73_PDET_PARDET10GLOSTLINK_PD_LOSTLINK_COUNT_SHIFT        0


/****************************************************************************
 * AN73_pdet :: cl73Control1
 ***************************************************************************/
/* AN73_pdet :: cl73Control1 :: reserved0 [15:08] */
#define AN73_PDET_CL73CONTROL1_RESERVED0_MASK                      0xff00
#define AN73_PDET_CL73CONTROL1_RESERVED0_ALIGN                     0
#define AN73_PDET_CL73CONTROL1_RESERVED0_BITS                      8
#define AN73_PDET_CL73CONTROL1_RESERVED0_SHIFT                     8

/* AN73_pdet :: cl73Control1 :: cl73_internal_10us_timer_val [07:00] */
#define AN73_PDET_CL73CONTROL1_CL73_INTERNAL_10US_TIMER_VAL_MASK   0x00ff
#define AN73_PDET_CL73CONTROL1_CL73_INTERNAL_10US_TIMER_VAL_ALIGN  0
#define AN73_PDET_CL73CONTROL1_CL73_INTERNAL_10US_TIMER_VAL_BITS   8
#define AN73_PDET_CL73CONTROL1_CL73_INTERNAL_10US_TIMER_VAL_SHIFT  0


/****************************************************************************
 * AN73_pdet :: cl73Control2
 ***************************************************************************/
/* AN73_pdet :: cl73Control2 :: reserved0 [15:13] */
#define AN73_PDET_CL73CONTROL2_RESERVED0_MASK                      0xe000
#define AN73_PDET_CL73CONTROL2_RESERVED0_ALIGN                     0
#define AN73_PDET_CL73CONTROL2_RESERVED0_BITS                      3
#define AN73_PDET_CL73CONTROL2_RESERVED0_SHIFT                     13

/* AN73_pdet :: cl73Control2 :: cl73_link_fail_inhibit_timer_val [12:00] */
#define AN73_PDET_CL73CONTROL2_CL73_LINK_FAIL_INHIBIT_TIMER_VAL_MASK 0x1fff
#define AN73_PDET_CL73CONTROL2_CL73_LINK_FAIL_INHIBIT_TIMER_VAL_ALIGN 0
#define AN73_PDET_CL73CONTROL2_CL73_LINK_FAIL_INHIBIT_TIMER_VAL_BITS 13
#define AN73_PDET_CL73CONTROL2_CL73_LINK_FAIL_INHIBIT_TIMER_VAL_SHIFT 0


/****************************************************************************
 * AN73_pdet :: cl73Control3
 ***************************************************************************/
/* AN73_pdet :: cl73Control3 :: reserved0 [15:13] */
#define AN73_PDET_CL73CONTROL3_RESERVED0_MASK                      0xe000
#define AN73_PDET_CL73CONTROL3_RESERVED0_ALIGN                     0
#define AN73_PDET_CL73CONTROL3_RESERVED0_BITS                      3
#define AN73_PDET_CL73CONTROL3_RESERVED0_SHIFT                     13

/* AN73_pdet :: cl73Control3 :: cl73_an_wait_timer_val [12:00] */
#define AN73_PDET_CL73CONTROL3_CL73_AN_WAIT_TIMER_VAL_MASK         0x1fff
#define AN73_PDET_CL73CONTROL3_CL73_AN_WAIT_TIMER_VAL_ALIGN        0
#define AN73_PDET_CL73CONTROL3_CL73_AN_WAIT_TIMER_VAL_BITS         13
#define AN73_PDET_CL73CONTROL3_CL73_AN_WAIT_TIMER_VAL_SHIFT        0


/****************************************************************************
 * AN73_pdet :: cl73Control4
 ***************************************************************************/
/* AN73_pdet :: cl73Control4 :: reserved0 [15:13] */
#define AN73_PDET_CL73CONTROL4_RESERVED0_MASK                      0xe000
#define AN73_PDET_CL73CONTROL4_RESERVED0_ALIGN                     0
#define AN73_PDET_CL73CONTROL4_RESERVED0_BITS                      3
#define AN73_PDET_CL73CONTROL4_RESERVED0_SHIFT                     13

/* AN73_pdet :: cl73Control4 :: cl73_break_link_timer_val [12:00] */
#define AN73_PDET_CL73CONTROL4_CL73_BREAK_LINK_TIMER_VAL_MASK      0x1fff
#define AN73_PDET_CL73CONTROL4_CL73_BREAK_LINK_TIMER_VAL_ALIGN     0
#define AN73_PDET_CL73CONTROL4_CL73_BREAK_LINK_TIMER_VAL_BITS      13
#define AN73_PDET_CL73CONTROL4_CL73_BREAK_LINK_TIMER_VAL_SHIFT     0

/****************************************************************************
 * XgxsBlk8 :: txLnSwap1
 ***************************************************************************/
/* XgxsBlk8 :: txLnSwap1 :: reserved_for_eco0 [15:08] */
#define XGXSBLK8_TXLNSWAP1_RESERVED_FOR_ECO0_MASK                  0xff00
#define XGXSBLK8_TXLNSWAP1_RESERVED_FOR_ECO0_ALIGN                 0
#define XGXSBLK8_TXLNSWAP1_RESERVED_FOR_ECO0_BITS                  8
#define XGXSBLK8_TXLNSWAP1_RESERVED_FOR_ECO0_SHIFT                 8

/* XgxsBlk8 :: txLnSwap1 :: tx3_lnswap_sel [07:06] */
#define XGXSBLK8_TXLNSWAP1_TX3_LNSWAP_SEL_MASK                     0x00c0
#define XGXSBLK8_TXLNSWAP1_TX3_LNSWAP_SEL_ALIGN                    0
#define XGXSBLK8_TXLNSWAP1_TX3_LNSWAP_SEL_BITS                     2
#define XGXSBLK8_TXLNSWAP1_TX3_LNSWAP_SEL_SHIFT                    6

/* XgxsBlk8 :: txLnSwap1 :: tx2_lnswap_sel [05:04] */
#define XGXSBLK8_TXLNSWAP1_TX2_LNSWAP_SEL_MASK                     0x0030
#define XGXSBLK8_TXLNSWAP1_TX2_LNSWAP_SEL_ALIGN                    0
#define XGXSBLK8_TXLNSWAP1_TX2_LNSWAP_SEL_BITS                     2
#define XGXSBLK8_TXLNSWAP1_TX2_LNSWAP_SEL_SHIFT                    4

/* XgxsBlk8 :: txLnSwap1 :: tx1_lnswap_sel [03:02] */
#define XGXSBLK8_TXLNSWAP1_TX1_LNSWAP_SEL_MASK                     0x000c
#define XGXSBLK8_TXLNSWAP1_TX1_LNSWAP_SEL_ALIGN                    0
#define XGXSBLK8_TXLNSWAP1_TX1_LNSWAP_SEL_BITS                     2
#define XGXSBLK8_TXLNSWAP1_TX1_LNSWAP_SEL_SHIFT                    2

/* XgxsBlk8 :: txLnSwap1 :: tx0_lnswap_sel [01:00] */
#define XGXSBLK8_TXLNSWAP1_TX0_LNSWAP_SEL_MASK                     0x0003
#define XGXSBLK8_TXLNSWAP1_TX0_LNSWAP_SEL_ALIGN                    0
#define XGXSBLK8_TXLNSWAP1_TX0_LNSWAP_SEL_BITS                     2
#define XGXSBLK8_TXLNSWAP1_TX0_LNSWAP_SEL_SHIFT                    0

/****************************************************************************
 * XgxsBlk8 :: rxLnSwap1
 ***************************************************************************/
/* XgxsBlk8 :: rxLnSwap1 :: reserved_for_eco0 [15:08] */
#define XGXSBLK8_RXLNSWAP1_RESERVED_FOR_ECO0_MASK                  0xff00
#define XGXSBLK8_RXLNSWAP1_RESERVED_FOR_ECO0_ALIGN                 0
#define XGXSBLK8_RXLNSWAP1_RESERVED_FOR_ECO0_BITS                  8
#define XGXSBLK8_RXLNSWAP1_RESERVED_FOR_ECO0_SHIFT                 8

/* XgxsBlk8 :: rxLnSwap1 :: rx3_lnswap_sel [07:06] */
#define XGXSBLK8_RXLNSWAP1_RX3_LNSWAP_SEL_MASK                     0x00c0
#define XGXSBLK8_RXLNSWAP1_RX3_LNSWAP_SEL_ALIGN                    0
#define XGXSBLK8_RXLNSWAP1_RX3_LNSWAP_SEL_BITS                     2
#define XGXSBLK8_RXLNSWAP1_RX3_LNSWAP_SEL_SHIFT                    6

/* XgxsBlk8 :: rxLnSwap1 :: rx2_lnswap_sel [05:04] */
#define XGXSBLK8_RXLNSWAP1_RX2_LNSWAP_SEL_MASK                     0x0030
#define XGXSBLK8_RXLNSWAP1_RX2_LNSWAP_SEL_ALIGN                    0
#define XGXSBLK8_RXLNSWAP1_RX2_LNSWAP_SEL_BITS                     2
#define XGXSBLK8_RXLNSWAP1_RX2_LNSWAP_SEL_SHIFT                    4

/* XgxsBlk8 :: rxLnSwap1 :: rx1_lnswap_sel [03:02] */
#define XGXSBLK8_RXLNSWAP1_RX1_LNSWAP_SEL_MASK                     0x000c
#define XGXSBLK8_RXLNSWAP1_RX1_LNSWAP_SEL_ALIGN                    0
#define XGXSBLK8_RXLNSWAP1_RX1_LNSWAP_SEL_BITS                     2
#define XGXSBLK8_RXLNSWAP1_RX1_LNSWAP_SEL_SHIFT                    2

/* XgxsBlk8 :: rxLnSwap1 :: rx0_lnswap_sel [01:00] */
#define XGXSBLK8_RXLNSWAP1_RX0_LNSWAP_SEL_MASK                     0x0003
#define XGXSBLK8_RXLNSWAP1_RX0_LNSWAP_SEL_ALIGN                    0
#define XGXSBLK8_RXLNSWAP1_RX0_LNSWAP_SEL_BITS                     2
#define XGXSBLK8_RXLNSWAP1_RX0_LNSWAP_SEL_SHIFT                    0


/****************************************************************************
 * XGXS16G_USER_dsc_1_0
 ***************************************************************************/
/****************************************************************************
 * dsc_1_0 :: cdr_ctrl0
 ***************************************************************************/
/* dsc_1_0 :: cdr_ctrl0 :: reserved_for_eco0 [15:09] */
#define DSC_1_0_CDR_CTRL0_RESERVED_FOR_ECO0_MASK                   0xfe00
#define DSC_1_0_CDR_CTRL0_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC_1_0_CDR_CTRL0_RESERVED_FOR_ECO0_BITS                   7
#define DSC_1_0_CDR_CTRL0_RESERVED_FOR_ECO0_SHIFT                  9

/* dsc_1_0 :: cdr_ctrl0 :: cdrbr_bwsel_integ [08:07] */
#define DSC_1_0_CDR_CTRL0_CDRBR_BWSEL_INTEG_MASK                   0x0180
#define DSC_1_0_CDR_CTRL0_CDRBR_BWSEL_INTEG_ALIGN                  0
#define DSC_1_0_CDR_CTRL0_CDRBR_BWSEL_INTEG_BITS                   2
#define DSC_1_0_CDR_CTRL0_CDRBR_BWSEL_INTEG_SHIFT                  7

/* dsc_1_0 :: cdr_ctrl0 :: cdrbr_bwsel_prop [06:04] */
#define DSC_1_0_CDR_CTRL0_CDRBR_BWSEL_PROP_MASK                    0x0070
#define DSC_1_0_CDR_CTRL0_CDRBR_BWSEL_PROP_ALIGN                   0
#define DSC_1_0_CDR_CTRL0_CDRBR_BWSEL_PROP_BITS                    3
#define DSC_1_0_CDR_CTRL0_CDRBR_BWSEL_PROP_SHIFT                   4

/* dsc_1_0 :: cdr_ctrl0 :: cdrbr_polarity [03:03] */
#define DSC_1_0_CDR_CTRL0_CDRBR_POLARITY_MASK                      0x0008
#define DSC_1_0_CDR_CTRL0_CDRBR_POLARITY_ALIGN                     0
#define DSC_1_0_CDR_CTRL0_CDRBR_POLARITY_BITS                      1
#define DSC_1_0_CDR_CTRL0_CDRBR_POLARITY_SHIFT                     3

/* dsc_1_0 :: cdr_ctrl0 :: cdrbr_third_vec_en [02:02] */
#define DSC_1_0_CDR_CTRL0_CDRBR_THIRD_VEC_EN_MASK                  0x0004
#define DSC_1_0_CDR_CTRL0_CDRBR_THIRD_VEC_EN_ALIGN                 0
#define DSC_1_0_CDR_CTRL0_CDRBR_THIRD_VEC_EN_BITS                  1
#define DSC_1_0_CDR_CTRL0_CDRBR_THIRD_VEC_EN_SHIFT                 2

/* dsc_1_0 :: cdr_ctrl0 :: reserved_for_eco1 [01:00] */
#define DSC_1_0_CDR_CTRL0_RESERVED_FOR_ECO1_MASK                   0x0003
#define DSC_1_0_CDR_CTRL0_RESERVED_FOR_ECO1_ALIGN                  0
#define DSC_1_0_CDR_CTRL0_RESERVED_FOR_ECO1_BITS                   2
#define DSC_1_0_CDR_CTRL0_RESERVED_FOR_ECO1_SHIFT                  0


/****************************************************************************
 * dsc_1_0 :: cdr_ctrl1
 ***************************************************************************/
/* dsc_1_0 :: cdr_ctrl1 :: reserved_for_eco0 [15:10] */
#define DSC_1_0_CDR_CTRL1_RESERVED_FOR_ECO0_MASK                   0xfc00
#define DSC_1_0_CDR_CTRL1_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC_1_0_CDR_CTRL1_RESERVED_FOR_ECO0_BITS                   6
#define DSC_1_0_CDR_CTRL1_RESERVED_FOR_ECO0_SHIFT                  10

/* dsc_1_0 :: cdr_ctrl1 :: cdr_phase_err_frz [09:09] */
#define DSC_1_0_CDR_CTRL1_CDR_PHASE_ERR_FRZ_MASK                   0x0200
#define DSC_1_0_CDR_CTRL1_CDR_PHASE_ERR_FRZ_ALIGN                  0
#define DSC_1_0_CDR_CTRL1_CDR_PHASE_ERR_FRZ_BITS                   1
#define DSC_1_0_CDR_CTRL1_CDR_PHASE_ERR_FRZ_SHIFT                  9

/* dsc_1_0 :: cdr_ctrl1 :: cdr_integ_reg_clr [08:08] */
#define DSC_1_0_CDR_CTRL1_CDR_INTEG_REG_CLR_MASK                   0x0100
#define DSC_1_0_CDR_CTRL1_CDR_INTEG_REG_CLR_ALIGN                  0
#define DSC_1_0_CDR_CTRL1_CDR_INTEG_REG_CLR_BITS                   1
#define DSC_1_0_CDR_CTRL1_CDR_INTEG_REG_CLR_SHIFT                  8

/* dsc_1_0 :: cdr_ctrl1 :: cdr_freq_override_val [07:03] */
#define DSC_1_0_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_MASK               0x00f8
#define DSC_1_0_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_ALIGN              0
#define DSC_1_0_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_BITS               5
#define DSC_1_0_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_SHIFT              3

/* dsc_1_0 :: cdr_ctrl1 :: cdr_freq_override_en [02:02] */
#define DSC_1_0_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_MASK                0x0004
#define DSC_1_0_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_ALIGN               0
#define DSC_1_0_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_BITS                1
#define DSC_1_0_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_SHIFT               2

/* dsc_1_0 :: cdr_ctrl1 :: cdr_freq_upd_en [01:01] */
#define DSC_1_0_CDR_CTRL1_CDR_FREQ_UPD_EN_MASK                     0x0002
#define DSC_1_0_CDR_CTRL1_CDR_FREQ_UPD_EN_ALIGN                    0
#define DSC_1_0_CDR_CTRL1_CDR_FREQ_UPD_EN_BITS                     1
#define DSC_1_0_CDR_CTRL1_CDR_FREQ_UPD_EN_SHIFT                    1

/* dsc_1_0 :: cdr_ctrl1 :: cdr_freq_en [00:00] */
#define DSC_1_0_CDR_CTRL1_CDR_FREQ_EN_MASK                         0x0001
#define DSC_1_0_CDR_CTRL1_CDR_FREQ_EN_ALIGN                        0
#define DSC_1_0_CDR_CTRL1_CDR_FREQ_EN_BITS                         1
#define DSC_1_0_CDR_CTRL1_CDR_FREQ_EN_SHIFT                        0


/****************************************************************************
 * dsc_1_0 :: cdr_ctrl2
 ***************************************************************************/
/* dsc_1_0 :: cdr_ctrl2 :: reserved_for_eco0 [15:14] */
#define DSC_1_0_CDR_CTRL2_RESERVED_FOR_ECO0_MASK                   0xc000
#define DSC_1_0_CDR_CTRL2_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC_1_0_CDR_CTRL2_RESERVED_FOR_ECO0_BITS                   2
#define DSC_1_0_CDR_CTRL2_RESERVED_FOR_ECO0_SHIFT                  14

/* dsc_1_0 :: cdr_ctrl2 :: cdros_bwsel_prop [13:10] */
#define DSC_1_0_CDR_CTRL2_CDROS_BWSEL_PROP_MASK                    0x3c00
#define DSC_1_0_CDR_CTRL2_CDROS_BWSEL_PROP_ALIGN                   0
#define DSC_1_0_CDR_CTRL2_CDROS_BWSEL_PROP_BITS                    4
#define DSC_1_0_CDR_CTRL2_CDROS_BWSEL_PROP_SHIFT                   10

/* dsc_1_0 :: cdr_ctrl2 :: cdros_bwsel_integ [09:06] */
#define DSC_1_0_CDR_CTRL2_CDROS_BWSEL_INTEG_MASK                   0x03c0
#define DSC_1_0_CDR_CTRL2_CDROS_BWSEL_INTEG_ALIGN                  0
#define DSC_1_0_CDR_CTRL2_CDROS_BWSEL_INTEG_BITS                   4
#define DSC_1_0_CDR_CTRL2_CDROS_BWSEL_INTEG_SHIFT                  6

/* dsc_1_0 :: cdr_ctrl2 :: cdros_falling_edge [05:05] */
#define DSC_1_0_CDR_CTRL2_CDROS_FALLING_EDGE_MASK                  0x0020
#define DSC_1_0_CDR_CTRL2_CDROS_FALLING_EDGE_ALIGN                 0
#define DSC_1_0_CDR_CTRL2_CDROS_FALLING_EDGE_BITS                  1
#define DSC_1_0_CDR_CTRL2_CDROS_FALLING_EDGE_SHIFT                 5

/* dsc_1_0 :: cdr_ctrl2 :: cdros_rising_edge [04:04] */
#define DSC_1_0_CDR_CTRL2_CDROS_RISING_EDGE_MASK                   0x0010
#define DSC_1_0_CDR_CTRL2_CDROS_RISING_EDGE_ALIGN                  0
#define DSC_1_0_CDR_CTRL2_CDROS_RISING_EDGE_BITS                   1
#define DSC_1_0_CDR_CTRL2_CDROS_RISING_EDGE_SHIFT                  4

/* dsc_1_0 :: cdr_ctrl2 :: cdros_phase_sat_ctrl [03:02] */
#define DSC_1_0_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_MASK                0x000c
#define DSC_1_0_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_ALIGN               0
#define DSC_1_0_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_BITS                2
#define DSC_1_0_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_SHIFT               2

/* dsc_1_0 :: cdr_ctrl2 :: cdros_peak_polarity [01:01] */
#define DSC_1_0_CDR_CTRL2_CDROS_PEAK_POLARITY_MASK                 0x0002
#define DSC_1_0_CDR_CTRL2_CDROS_PEAK_POLARITY_ALIGN                0
#define DSC_1_0_CDR_CTRL2_CDROS_PEAK_POLARITY_BITS                 1
#define DSC_1_0_CDR_CTRL2_CDROS_PEAK_POLARITY_SHIFT                1

/* dsc_1_0 :: cdr_ctrl2 :: cdros_zero_polarity [00:00] */
#define DSC_1_0_CDR_CTRL2_CDROS_ZERO_POLARITY_MASK                 0x0001
#define DSC_1_0_CDR_CTRL2_CDROS_ZERO_POLARITY_ALIGN                0
#define DSC_1_0_CDR_CTRL2_CDROS_ZERO_POLARITY_BITS                 1
#define DSC_1_0_CDR_CTRL2_CDROS_ZERO_POLARITY_SHIFT                0


/****************************************************************************
 * dsc_1_0 :: cdr_status0
 ***************************************************************************/
/* dsc_1_0 :: cdr_status0 :: integ_reg [15:00] */
#define DSC_1_0_CDR_STATUS0_INTEG_REG_MASK                         0xffff
#define DSC_1_0_CDR_STATUS0_INTEG_REG_ALIGN                        0
#define DSC_1_0_CDR_STATUS0_INTEG_REG_BITS                         16
#define DSC_1_0_CDR_STATUS0_INTEG_REG_SHIFT                        0


/****************************************************************************
 * dsc_1_0 :: cdr_status1
 ***************************************************************************/
/* dsc_1_0 :: cdr_status1 :: reserved_for_eco0 [15:06] */
#define DSC_1_0_CDR_STATUS1_RESERVED_FOR_ECO0_MASK                 0xffc0
#define DSC_1_0_CDR_STATUS1_RESERVED_FOR_ECO0_ALIGN                0
#define DSC_1_0_CDR_STATUS1_RESERVED_FOR_ECO0_BITS                 10
#define DSC_1_0_CDR_STATUS1_RESERVED_FOR_ECO0_SHIFT                6

/* dsc_1_0 :: cdr_status1 :: phase_err [05:00] */
#define DSC_1_0_CDR_STATUS1_PHASE_ERR_MASK                         0x003f
#define DSC_1_0_CDR_STATUS1_PHASE_ERR_ALIGN                        0
#define DSC_1_0_CDR_STATUS1_PHASE_ERR_BITS                         6
#define DSC_1_0_CDR_STATUS1_PHASE_ERR_SHIFT                        0


/****************************************************************************
 * dsc_1_0 :: pi_ctrl0
 ***************************************************************************/
/* dsc_1_0 :: pi_ctrl0 :: reserved_for_eco0 [15:11] */
#define DSC_1_0_PI_CTRL0_RESERVED_FOR_ECO0_MASK                    0xf800
#define DSC_1_0_PI_CTRL0_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC_1_0_PI_CTRL0_RESERVED_FOR_ECO0_BITS                    5
#define DSC_1_0_PI_CTRL0_RESERVED_FOR_ECO0_SHIFT                   11

/* dsc_1_0 :: pi_ctrl0 :: pi_phase_invert [10:10] */
#define DSC_1_0_PI_CTRL0_PI_PHASE_INVERT_MASK                      0x0400
#define DSC_1_0_PI_CTRL0_PI_PHASE_INVERT_ALIGN                     0
#define DSC_1_0_PI_CTRL0_PI_PHASE_INVERT_BITS                      1
#define DSC_1_0_PI_CTRL0_PI_PHASE_INVERT_SHIFT                     10

/* dsc_1_0 :: pi_ctrl0 :: pi_dual_phase_override [09:09] */
#define DSC_1_0_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_MASK               0x0200
#define DSC_1_0_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_ALIGN              0
#define DSC_1_0_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_BITS               1
#define DSC_1_0_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_SHIFT              9

/* dsc_1_0 :: pi_ctrl0 :: pi_clk90_offset_override [08:08] */
#define DSC_1_0_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_MASK             0x0100
#define DSC_1_0_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_ALIGN            0
#define DSC_1_0_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_BITS             1
#define DSC_1_0_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_SHIFT            8

/* dsc_1_0 :: pi_ctrl0 :: pi_phase_dec [07:07] */
#define DSC_1_0_PI_CTRL0_PI_PHASE_DEC_MASK                         0x0080
#define DSC_1_0_PI_CTRL0_PI_PHASE_DEC_ALIGN                        0
#define DSC_1_0_PI_CTRL0_PI_PHASE_DEC_BITS                         1
#define DSC_1_0_PI_CTRL0_PI_PHASE_DEC_SHIFT                        7

/* dsc_1_0 :: pi_ctrl0 :: pi_phase_inc [06:06] */
#define DSC_1_0_PI_CTRL0_PI_PHASE_INC_MASK                         0x0040
#define DSC_1_0_PI_CTRL0_PI_PHASE_INC_ALIGN                        0
#define DSC_1_0_PI_CTRL0_PI_PHASE_INC_BITS                         1
#define DSC_1_0_PI_CTRL0_PI_PHASE_INC_SHIFT                        6

/* dsc_1_0 :: pi_ctrl0 :: pi_phase_strobe [05:05] */
#define DSC_1_0_PI_CTRL0_PI_PHASE_STROBE_MASK                      0x0020
#define DSC_1_0_PI_CTRL0_PI_PHASE_STROBE_ALIGN                     0
#define DSC_1_0_PI_CTRL0_PI_PHASE_STROBE_BITS                      1
#define DSC_1_0_PI_CTRL0_PI_PHASE_STROBE_SHIFT                     5

/* dsc_1_0 :: pi_ctrl0 :: pi_phase_delta [04:01] */
#define DSC_1_0_PI_CTRL0_PI_PHASE_DELTA_MASK                       0x001e
#define DSC_1_0_PI_CTRL0_PI_PHASE_DELTA_ALIGN                      0
#define DSC_1_0_PI_CTRL0_PI_PHASE_DELTA_BITS                       4
#define DSC_1_0_PI_CTRL0_PI_PHASE_DELTA_SHIFT                      1

/* dsc_1_0 :: pi_ctrl0 :: pi_phase_step_mult [00:00] */
#define DSC_1_0_PI_CTRL0_PI_PHASE_STEP_MULT_MASK                   0x0001
#define DSC_1_0_PI_CTRL0_PI_PHASE_STEP_MULT_ALIGN                  0
#define DSC_1_0_PI_CTRL0_PI_PHASE_STEP_MULT_BITS                   1
#define DSC_1_0_PI_CTRL0_PI_PHASE_STEP_MULT_SHIFT                  0


/****************************************************************************
 * dsc_1_0 :: pi_status0
 ***************************************************************************/
/* dsc_1_0 :: pi_status0 :: reserved_for_eco0 [15:14] */
#define DSC_1_0_PI_STATUS0_RESERVED_FOR_ECO0_MASK                  0xc000
#define DSC_1_0_PI_STATUS0_RESERVED_FOR_ECO0_ALIGN                 0
#define DSC_1_0_PI_STATUS0_RESERVED_FOR_ECO0_BITS                  2
#define DSC_1_0_PI_STATUS0_RESERVED_FOR_ECO0_SHIFT                 14

/* dsc_1_0 :: pi_status0 :: clk90_phase_offset [13:07] */
#define DSC_1_0_PI_STATUS0_CLK90_PHASE_OFFSET_MASK                 0x3f80
#define DSC_1_0_PI_STATUS0_CLK90_PHASE_OFFSET_ALIGN                0
#define DSC_1_0_PI_STATUS0_CLK90_PHASE_OFFSET_BITS                 7
#define DSC_1_0_PI_STATUS0_CLK90_PHASE_OFFSET_SHIFT                7

/* dsc_1_0 :: pi_status0 :: phase_cntr [06:00] */
#define DSC_1_0_PI_STATUS0_PHASE_CNTR_MASK                         0x007f
#define DSC_1_0_PI_STATUS0_PHASE_CNTR_ALIGN                        0
#define DSC_1_0_PI_STATUS0_PHASE_CNTR_BITS                         7
#define DSC_1_0_PI_STATUS0_PHASE_CNTR_SHIFT                        0


/****************************************************************************
 * dsc_1_0 :: dfe_vga_ctrl0
 ***************************************************************************/
/* dsc_1_0 :: dfe_vga_ctrl0 :: reserved_for_eco0 [15:12] */
#define DSC_1_0_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_MASK               0xf000
#define DSC_1_0_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_ALIGN              0
#define DSC_1_0_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_BITS               4
#define DSC_1_0_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_SHIFT              12

/* dsc_1_0 :: dfe_vga_ctrl0 :: trnsum_tap0_only [11:11] */
#define DSC_1_0_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_MASK                0x0800
#define DSC_1_0_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_ALIGN               0
#define DSC_1_0_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_BITS                1
#define DSC_1_0_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_SHIFT               11

/* dsc_1_0 :: dfe_vga_ctrl0 :: sum_m1err [10:10] */
#define DSC_1_0_DFE_VGA_CTRL0_SUM_M1ERR_MASK                       0x0400
#define DSC_1_0_DFE_VGA_CTRL0_SUM_M1ERR_ALIGN                      0
#define DSC_1_0_DFE_VGA_CTRL0_SUM_M1ERR_BITS                       1
#define DSC_1_0_DFE_VGA_CTRL0_SUM_M1ERR_SHIFT                      10

/* dsc_1_0 :: dfe_vga_ctrl0 :: dfe_vga_clken [09:09] */
#define DSC_1_0_DFE_VGA_CTRL0_DFE_VGA_CLKEN_MASK                   0x0200
#define DSC_1_0_DFE_VGA_CTRL0_DFE_VGA_CLKEN_ALIGN                  0
#define DSC_1_0_DFE_VGA_CTRL0_DFE_VGA_CLKEN_BITS                   1
#define DSC_1_0_DFE_VGA_CTRL0_DFE_VGA_CLKEN_SHIFT                  9

/* dsc_1_0 :: dfe_vga_ctrl0 :: hysteresis_en [08:08] */
#define DSC_1_0_DFE_VGA_CTRL0_HYSTERESIS_EN_MASK                   0x0100
#define DSC_1_0_DFE_VGA_CTRL0_HYSTERESIS_EN_ALIGN                  0
#define DSC_1_0_DFE_VGA_CTRL0_HYSTERESIS_EN_BITS                   1
#define DSC_1_0_DFE_VGA_CTRL0_HYSTERESIS_EN_SHIFT                  8

/* dsc_1_0 :: dfe_vga_ctrl0 :: dfe_vga_write_val [07:02] */
#define DSC_1_0_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_MASK               0x00fc
#define DSC_1_0_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_ALIGN              0
#define DSC_1_0_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_BITS               6
#define DSC_1_0_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_SHIFT              2

/* dsc_1_0 :: dfe_vga_ctrl0 :: vga_write_en [01:01] */
#define DSC_1_0_DFE_VGA_CTRL0_VGA_WRITE_EN_MASK                    0x0002
#define DSC_1_0_DFE_VGA_CTRL0_VGA_WRITE_EN_ALIGN                   0
#define DSC_1_0_DFE_VGA_CTRL0_VGA_WRITE_EN_BITS                    1
#define DSC_1_0_DFE_VGA_CTRL0_VGA_WRITE_EN_SHIFT                   1

/* dsc_1_0 :: dfe_vga_ctrl0 :: dfe_write_en [00:00] */
#define DSC_1_0_DFE_VGA_CTRL0_DFE_WRITE_EN_MASK                    0x0001
#define DSC_1_0_DFE_VGA_CTRL0_DFE_WRITE_EN_ALIGN                   0
#define DSC_1_0_DFE_VGA_CTRL0_DFE_WRITE_EN_BITS                    1
#define DSC_1_0_DFE_VGA_CTRL0_DFE_WRITE_EN_SHIFT                   0


/****************************************************************************
 * dsc_1_0 :: dfe_vga_ctrl1
 ***************************************************************************/
/* dsc_1_0 :: dfe_vga_ctrl1 :: reserved_for_eco0 [15:15] */
#define DSC_1_0_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_MASK               0x8000
#define DSC_1_0_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_ALIGN              0
#define DSC_1_0_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_BITS               1
#define DSC_1_0_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_SHIFT              15

/* dsc_1_0 :: dfe_vga_ctrl1 :: trnsum_otap_en [14:08] */
#define DSC_1_0_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_MASK                  0x7f00
#define DSC_1_0_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_ALIGN                 0
#define DSC_1_0_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_BITS                  7
#define DSC_1_0_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_SHIFT                 8

/* dsc_1_0 :: dfe_vga_ctrl1 :: trnsum_etap_en [07:01] */
#define DSC_1_0_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_MASK                  0x00fe
#define DSC_1_0_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_ALIGN                 0
#define DSC_1_0_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_BITS                  7
#define DSC_1_0_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_SHIFT                 1

/* dsc_1_0 :: dfe_vga_ctrl1 :: trnsum_en [00:00] */
#define DSC_1_0_DFE_VGA_CTRL1_TRNSUM_EN_MASK                       0x0001
#define DSC_1_0_DFE_VGA_CTRL1_TRNSUM_EN_ALIGN                      0
#define DSC_1_0_DFE_VGA_CTRL1_TRNSUM_EN_BITS                       1
#define DSC_1_0_DFE_VGA_CTRL1_TRNSUM_EN_SHIFT                      0


/****************************************************************************
 * dsc_1_0 :: dfe_vga_ctrl2
 ***************************************************************************/
/* dsc_1_0 :: dfe_vga_ctrl2 :: vga_polarity [15:15] */
#define DSC_1_0_DFE_VGA_CTRL2_VGA_POLARITY_MASK                    0x8000
#define DSC_1_0_DFE_VGA_CTRL2_VGA_POLARITY_ALIGN                   0
#define DSC_1_0_DFE_VGA_CTRL2_VGA_POLARITY_BITS                    1
#define DSC_1_0_DFE_VGA_CTRL2_VGA_POLARITY_SHIFT                   15

/* dsc_1_0 :: dfe_vga_ctrl2 :: dfe_polarity [14:14] */
#define DSC_1_0_DFE_VGA_CTRL2_DFE_POLARITY_MASK                    0x4000
#define DSC_1_0_DFE_VGA_CTRL2_DFE_POLARITY_ALIGN                   0
#define DSC_1_0_DFE_VGA_CTRL2_DFE_POLARITY_BITS                    1
#define DSC_1_0_DFE_VGA_CTRL2_DFE_POLARITY_SHIFT                   14

/* dsc_1_0 :: dfe_vga_ctrl2 :: trnsum_otap_sign [13:07] */
#define DSC_1_0_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_MASK                0x3f80
#define DSC_1_0_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_ALIGN               0
#define DSC_1_0_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_BITS                7
#define DSC_1_0_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_SHIFT               7

/* dsc_1_0 :: dfe_vga_ctrl2 :: trnsum_etap_sign [06:00] */
#define DSC_1_0_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_MASK                0x007f
#define DSC_1_0_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_ALIGN               0
#define DSC_1_0_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_BITS                7
#define DSC_1_0_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_SHIFT               0


/****************************************************************************
 * dsc_1_0 :: dfe_vga_ctrl3
 ***************************************************************************/
/* dsc_1_0 :: dfe_vga_ctrl3 :: reserved_for_eco0 [15:10] */
#define DSC_1_0_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_MASK               0xfc00
#define DSC_1_0_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_ALIGN              0
#define DSC_1_0_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_BITS               6
#define DSC_1_0_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_SHIFT              10

/* dsc_1_0 :: dfe_vga_ctrl3 :: vga_cor_sel_e [09:05] */
#define DSC_1_0_DFE_VGA_CTRL3_VGA_COR_SEL_E_MASK                   0x03e0
#define DSC_1_0_DFE_VGA_CTRL3_VGA_COR_SEL_E_ALIGN                  0
#define DSC_1_0_DFE_VGA_CTRL3_VGA_COR_SEL_E_BITS                   5
#define DSC_1_0_DFE_VGA_CTRL3_VGA_COR_SEL_E_SHIFT                  5

/* dsc_1_0 :: dfe_vga_ctrl3 :: vga_cor_sel_o [04:00] */
#define DSC_1_0_DFE_VGA_CTRL3_VGA_COR_SEL_O_MASK                   0x001f
#define DSC_1_0_DFE_VGA_CTRL3_VGA_COR_SEL_O_ALIGN                  0
#define DSC_1_0_DFE_VGA_CTRL3_VGA_COR_SEL_O_BITS                   5
#define DSC_1_0_DFE_VGA_CTRL3_VGA_COR_SEL_O_SHIFT                  0


/****************************************************************************
 * dsc_1_0 :: dfe_vga_ctrl4
 ***************************************************************************/
/* dsc_1_0 :: dfe_vga_ctrl4 :: reserved_for_eco0 [15:10] */
#define DSC_1_0_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_MASK               0xfc00
#define DSC_1_0_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_ALIGN              0
#define DSC_1_0_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_BITS               6
#define DSC_1_0_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_SHIFT              10

/* dsc_1_0 :: dfe_vga_ctrl4 :: dfe_cor_sel_e [09:05] */
#define DSC_1_0_DFE_VGA_CTRL4_DFE_COR_SEL_E_MASK                   0x03e0
#define DSC_1_0_DFE_VGA_CTRL4_DFE_COR_SEL_E_ALIGN                  0
#define DSC_1_0_DFE_VGA_CTRL4_DFE_COR_SEL_E_BITS                   5
#define DSC_1_0_DFE_VGA_CTRL4_DFE_COR_SEL_E_SHIFT                  5

/* dsc_1_0 :: dfe_vga_ctrl4 :: dfe_cor_sel_o [04:00] */
#define DSC_1_0_DFE_VGA_CTRL4_DFE_COR_SEL_O_MASK                   0x001f
#define DSC_1_0_DFE_VGA_CTRL4_DFE_COR_SEL_O_ALIGN                  0
#define DSC_1_0_DFE_VGA_CTRL4_DFE_COR_SEL_O_BITS                   5
#define DSC_1_0_DFE_VGA_CTRL4_DFE_COR_SEL_O_SHIFT                  0


/****************************************************************************
 * dsc_1_0 :: dfe_vga_status0
 ***************************************************************************/
/* dsc_1_0 :: dfe_vga_status0 :: vga_sum [15:11] */
#define DSC_1_0_DFE_VGA_STATUS0_VGA_SUM_MASK                       0xf800
#define DSC_1_0_DFE_VGA_STATUS0_VGA_SUM_ALIGN                      0
#define DSC_1_0_DFE_VGA_STATUS0_VGA_SUM_BITS                       5
#define DSC_1_0_DFE_VGA_STATUS0_VGA_SUM_SHIFT                      11

/* dsc_1_0 :: dfe_vga_status0 :: trnsum [10:00] */
#define DSC_1_0_DFE_VGA_STATUS0_TRNSUM_MASK                        0x07ff
#define DSC_1_0_DFE_VGA_STATUS0_TRNSUM_ALIGN                       0
#define DSC_1_0_DFE_VGA_STATUS0_TRNSUM_BITS                        11
#define DSC_1_0_DFE_VGA_STATUS0_TRNSUM_SHIFT                       0


/****************************************************************************
 * dsc_1_0 :: dfe_vga_status1
 ***************************************************************************/
/* dsc_1_0 :: dfe_vga_status1 :: odd_dfe_acc [15:06] */
#define DSC_1_0_DFE_VGA_STATUS1_ODD_DFE_ACC_MASK                   0xffc0
#define DSC_1_0_DFE_VGA_STATUS1_ODD_DFE_ACC_ALIGN                  0
#define DSC_1_0_DFE_VGA_STATUS1_ODD_DFE_ACC_BITS                   10
#define DSC_1_0_DFE_VGA_STATUS1_ODD_DFE_ACC_SHIFT                  6

/* dsc_1_0 :: dfe_vga_status1 :: dfe_tap_bin [05:00] */
#define DSC_1_0_DFE_VGA_STATUS1_DFE_TAP_BIN_MASK                   0x003f
#define DSC_1_0_DFE_VGA_STATUS1_DFE_TAP_BIN_ALIGN                  0
#define DSC_1_0_DFE_VGA_STATUS1_DFE_TAP_BIN_BITS                   6
#define DSC_1_0_DFE_VGA_STATUS1_DFE_TAP_BIN_SHIFT                  0


/****************************************************************************
 * dsc_1_0 :: dfe_vga_status2
 ***************************************************************************/
/* dsc_1_0 :: dfe_vga_status2 :: reserved_for_eco0 [15:10] */
#define DSC_1_0_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_MASK             0xfc00
#define DSC_1_0_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_ALIGN            0
#define DSC_1_0_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_BITS             6
#define DSC_1_0_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_SHIFT            10

/* dsc_1_0 :: dfe_vga_status2 :: evn_dfe_acc [09:00] */
#define DSC_1_0_DFE_VGA_STATUS2_EVN_DFE_ACC_MASK                   0x03ff
#define DSC_1_0_DFE_VGA_STATUS2_EVN_DFE_ACC_ALIGN                  0
#define DSC_1_0_DFE_VGA_STATUS2_EVN_DFE_ACC_BITS                   10
#define DSC_1_0_DFE_VGA_STATUS2_EVN_DFE_ACC_SHIFT                  0


/****************************************************************************
 * XGXS16G_USER_dsc_1_1
 ***************************************************************************/
/****************************************************************************
 * dsc_1_1 :: cdr_ctrl0
 ***************************************************************************/
/* dsc_1_1 :: cdr_ctrl0 :: reserved_for_eco0 [15:09] */
#define DSC_1_1_CDR_CTRL0_RESERVED_FOR_ECO0_MASK                   0xfe00
#define DSC_1_1_CDR_CTRL0_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC_1_1_CDR_CTRL0_RESERVED_FOR_ECO0_BITS                   7
#define DSC_1_1_CDR_CTRL0_RESERVED_FOR_ECO0_SHIFT                  9

/* dsc_1_1 :: cdr_ctrl0 :: cdrbr_bwsel_integ [08:07] */
#define DSC_1_1_CDR_CTRL0_CDRBR_BWSEL_INTEG_MASK                   0x0180
#define DSC_1_1_CDR_CTRL0_CDRBR_BWSEL_INTEG_ALIGN                  0
#define DSC_1_1_CDR_CTRL0_CDRBR_BWSEL_INTEG_BITS                   2
#define DSC_1_1_CDR_CTRL0_CDRBR_BWSEL_INTEG_SHIFT                  7

/* dsc_1_1 :: cdr_ctrl0 :: cdrbr_bwsel_prop [06:04] */
#define DSC_1_1_CDR_CTRL0_CDRBR_BWSEL_PROP_MASK                    0x0070
#define DSC_1_1_CDR_CTRL0_CDRBR_BWSEL_PROP_ALIGN                   0
#define DSC_1_1_CDR_CTRL0_CDRBR_BWSEL_PROP_BITS                    3
#define DSC_1_1_CDR_CTRL0_CDRBR_BWSEL_PROP_SHIFT                   4

/* dsc_1_1 :: cdr_ctrl0 :: cdrbr_polarity [03:03] */
#define DSC_1_1_CDR_CTRL0_CDRBR_POLARITY_MASK                      0x0008
#define DSC_1_1_CDR_CTRL0_CDRBR_POLARITY_ALIGN                     0
#define DSC_1_1_CDR_CTRL0_CDRBR_POLARITY_BITS                      1
#define DSC_1_1_CDR_CTRL0_CDRBR_POLARITY_SHIFT                     3

/* dsc_1_1 :: cdr_ctrl0 :: cdrbr_third_vec_en [02:02] */
#define DSC_1_1_CDR_CTRL0_CDRBR_THIRD_VEC_EN_MASK                  0x0004
#define DSC_1_1_CDR_CTRL0_CDRBR_THIRD_VEC_EN_ALIGN                 0
#define DSC_1_1_CDR_CTRL0_CDRBR_THIRD_VEC_EN_BITS                  1
#define DSC_1_1_CDR_CTRL0_CDRBR_THIRD_VEC_EN_SHIFT                 2

/* dsc_1_1 :: cdr_ctrl0 :: reserved_for_eco1 [01:00] */
#define DSC_1_1_CDR_CTRL0_RESERVED_FOR_ECO1_MASK                   0x0003
#define DSC_1_1_CDR_CTRL0_RESERVED_FOR_ECO1_ALIGN                  0
#define DSC_1_1_CDR_CTRL0_RESERVED_FOR_ECO1_BITS                   2
#define DSC_1_1_CDR_CTRL0_RESERVED_FOR_ECO1_SHIFT                  0


/****************************************************************************
 * dsc_1_1 :: cdr_ctrl1
 ***************************************************************************/
/* dsc_1_1 :: cdr_ctrl1 :: reserved_for_eco0 [15:10] */
#define DSC_1_1_CDR_CTRL1_RESERVED_FOR_ECO0_MASK                   0xfc00
#define DSC_1_1_CDR_CTRL1_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC_1_1_CDR_CTRL1_RESERVED_FOR_ECO0_BITS                   6
#define DSC_1_1_CDR_CTRL1_RESERVED_FOR_ECO0_SHIFT                  10

/* dsc_1_1 :: cdr_ctrl1 :: cdr_phase_err_frz [09:09] */
#define DSC_1_1_CDR_CTRL1_CDR_PHASE_ERR_FRZ_MASK                   0x0200
#define DSC_1_1_CDR_CTRL1_CDR_PHASE_ERR_FRZ_ALIGN                  0
#define DSC_1_1_CDR_CTRL1_CDR_PHASE_ERR_FRZ_BITS                   1
#define DSC_1_1_CDR_CTRL1_CDR_PHASE_ERR_FRZ_SHIFT                  9

/* dsc_1_1 :: cdr_ctrl1 :: cdr_integ_reg_clr [08:08] */
#define DSC_1_1_CDR_CTRL1_CDR_INTEG_REG_CLR_MASK                   0x0100
#define DSC_1_1_CDR_CTRL1_CDR_INTEG_REG_CLR_ALIGN                  0
#define DSC_1_1_CDR_CTRL1_CDR_INTEG_REG_CLR_BITS                   1
#define DSC_1_1_CDR_CTRL1_CDR_INTEG_REG_CLR_SHIFT                  8

/* dsc_1_1 :: cdr_ctrl1 :: cdr_freq_override_val [07:03] */
#define DSC_1_1_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_MASK               0x00f8
#define DSC_1_1_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_ALIGN              0
#define DSC_1_1_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_BITS               5
#define DSC_1_1_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_SHIFT              3

/* dsc_1_1 :: cdr_ctrl1 :: cdr_freq_override_en [02:02] */
#define DSC_1_1_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_MASK                0x0004
#define DSC_1_1_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_ALIGN               0
#define DSC_1_1_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_BITS                1
#define DSC_1_1_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_SHIFT               2

/* dsc_1_1 :: cdr_ctrl1 :: cdr_freq_upd_en [01:01] */
#define DSC_1_1_CDR_CTRL1_CDR_FREQ_UPD_EN_MASK                     0x0002
#define DSC_1_1_CDR_CTRL1_CDR_FREQ_UPD_EN_ALIGN                    0
#define DSC_1_1_CDR_CTRL1_CDR_FREQ_UPD_EN_BITS                     1
#define DSC_1_1_CDR_CTRL1_CDR_FREQ_UPD_EN_SHIFT                    1

/* dsc_1_1 :: cdr_ctrl1 :: cdr_freq_en [00:00] */
#define DSC_1_1_CDR_CTRL1_CDR_FREQ_EN_MASK                         0x0001
#define DSC_1_1_CDR_CTRL1_CDR_FREQ_EN_ALIGN                        0
#define DSC_1_1_CDR_CTRL1_CDR_FREQ_EN_BITS                         1
#define DSC_1_1_CDR_CTRL1_CDR_FREQ_EN_SHIFT                        0


/****************************************************************************
 * dsc_1_1 :: cdr_ctrl2
 ***************************************************************************/
/* dsc_1_1 :: cdr_ctrl2 :: reserved_for_eco0 [15:14] */
#define DSC_1_1_CDR_CTRL2_RESERVED_FOR_ECO0_MASK                   0xc000
#define DSC_1_1_CDR_CTRL2_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC_1_1_CDR_CTRL2_RESERVED_FOR_ECO0_BITS                   2
#define DSC_1_1_CDR_CTRL2_RESERVED_FOR_ECO0_SHIFT                  14

/* dsc_1_1 :: cdr_ctrl2 :: cdros_bwsel_prop [13:10] */
#define DSC_1_1_CDR_CTRL2_CDROS_BWSEL_PROP_MASK                    0x3c00
#define DSC_1_1_CDR_CTRL2_CDROS_BWSEL_PROP_ALIGN                   0
#define DSC_1_1_CDR_CTRL2_CDROS_BWSEL_PROP_BITS                    4
#define DSC_1_1_CDR_CTRL2_CDROS_BWSEL_PROP_SHIFT                   10

/* dsc_1_1 :: cdr_ctrl2 :: cdros_bwsel_integ [09:06] */
#define DSC_1_1_CDR_CTRL2_CDROS_BWSEL_INTEG_MASK                   0x03c0
#define DSC_1_1_CDR_CTRL2_CDROS_BWSEL_INTEG_ALIGN                  0
#define DSC_1_1_CDR_CTRL2_CDROS_BWSEL_INTEG_BITS                   4
#define DSC_1_1_CDR_CTRL2_CDROS_BWSEL_INTEG_SHIFT                  6

/* dsc_1_1 :: cdr_ctrl2 :: cdros_falling_edge [05:05] */
#define DSC_1_1_CDR_CTRL2_CDROS_FALLING_EDGE_MASK                  0x0020
#define DSC_1_1_CDR_CTRL2_CDROS_FALLING_EDGE_ALIGN                 0
#define DSC_1_1_CDR_CTRL2_CDROS_FALLING_EDGE_BITS                  1
#define DSC_1_1_CDR_CTRL2_CDROS_FALLING_EDGE_SHIFT                 5

/* dsc_1_1 :: cdr_ctrl2 :: cdros_rising_edge [04:04] */
#define DSC_1_1_CDR_CTRL2_CDROS_RISING_EDGE_MASK                   0x0010
#define DSC_1_1_CDR_CTRL2_CDROS_RISING_EDGE_ALIGN                  0
#define DSC_1_1_CDR_CTRL2_CDROS_RISING_EDGE_BITS                   1
#define DSC_1_1_CDR_CTRL2_CDROS_RISING_EDGE_SHIFT                  4

/* dsc_1_1 :: cdr_ctrl2 :: cdros_phase_sat_ctrl [03:02] */
#define DSC_1_1_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_MASK                0x000c
#define DSC_1_1_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_ALIGN               0
#define DSC_1_1_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_BITS                2
#define DSC_1_1_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_SHIFT               2

/* dsc_1_1 :: cdr_ctrl2 :: cdros_peak_polarity [01:01] */
#define DSC_1_1_CDR_CTRL2_CDROS_PEAK_POLARITY_MASK                 0x0002
#define DSC_1_1_CDR_CTRL2_CDROS_PEAK_POLARITY_ALIGN                0
#define DSC_1_1_CDR_CTRL2_CDROS_PEAK_POLARITY_BITS                 1
#define DSC_1_1_CDR_CTRL2_CDROS_PEAK_POLARITY_SHIFT                1

/* dsc_1_1 :: cdr_ctrl2 :: cdros_zero_polarity [00:00] */
#define DSC_1_1_CDR_CTRL2_CDROS_ZERO_POLARITY_MASK                 0x0001
#define DSC_1_1_CDR_CTRL2_CDROS_ZERO_POLARITY_ALIGN                0
#define DSC_1_1_CDR_CTRL2_CDROS_ZERO_POLARITY_BITS                 1
#define DSC_1_1_CDR_CTRL2_CDROS_ZERO_POLARITY_SHIFT                0


/****************************************************************************
 * dsc_1_1 :: cdr_status0
 ***************************************************************************/
/* dsc_1_1 :: cdr_status0 :: integ_reg [15:00] */
#define DSC_1_1_CDR_STATUS0_INTEG_REG_MASK                         0xffff
#define DSC_1_1_CDR_STATUS0_INTEG_REG_ALIGN                        0
#define DSC_1_1_CDR_STATUS0_INTEG_REG_BITS                         16
#define DSC_1_1_CDR_STATUS0_INTEG_REG_SHIFT                        0


/****************************************************************************
 * dsc_1_1 :: cdr_status1
 ***************************************************************************/
/* dsc_1_1 :: cdr_status1 :: reserved_for_eco0 [15:06] */
#define DSC_1_1_CDR_STATUS1_RESERVED_FOR_ECO0_MASK                 0xffc0
#define DSC_1_1_CDR_STATUS1_RESERVED_FOR_ECO0_ALIGN                0
#define DSC_1_1_CDR_STATUS1_RESERVED_FOR_ECO0_BITS                 10
#define DSC_1_1_CDR_STATUS1_RESERVED_FOR_ECO0_SHIFT                6

/* dsc_1_1 :: cdr_status1 :: phase_err [05:00] */
#define DSC_1_1_CDR_STATUS1_PHASE_ERR_MASK                         0x003f
#define DSC_1_1_CDR_STATUS1_PHASE_ERR_ALIGN                        0
#define DSC_1_1_CDR_STATUS1_PHASE_ERR_BITS                         6
#define DSC_1_1_CDR_STATUS1_PHASE_ERR_SHIFT                        0


/****************************************************************************
 * dsc_1_1 :: pi_ctrl0
 ***************************************************************************/
/* dsc_1_1 :: pi_ctrl0 :: reserved_for_eco0 [15:11] */
#define DSC_1_1_PI_CTRL0_RESERVED_FOR_ECO0_MASK                    0xf800
#define DSC_1_1_PI_CTRL0_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC_1_1_PI_CTRL0_RESERVED_FOR_ECO0_BITS                    5
#define DSC_1_1_PI_CTRL0_RESERVED_FOR_ECO0_SHIFT                   11

/* dsc_1_1 :: pi_ctrl0 :: pi_phase_invert [10:10] */
#define DSC_1_1_PI_CTRL0_PI_PHASE_INVERT_MASK                      0x0400
#define DSC_1_1_PI_CTRL0_PI_PHASE_INVERT_ALIGN                     0
#define DSC_1_1_PI_CTRL0_PI_PHASE_INVERT_BITS                      1
#define DSC_1_1_PI_CTRL0_PI_PHASE_INVERT_SHIFT                     10

/* dsc_1_1 :: pi_ctrl0 :: pi_dual_phase_override [09:09] */
#define DSC_1_1_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_MASK               0x0200
#define DSC_1_1_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_ALIGN              0
#define DSC_1_1_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_BITS               1
#define DSC_1_1_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_SHIFT              9

/* dsc_1_1 :: pi_ctrl0 :: pi_clk90_offset_override [08:08] */
#define DSC_1_1_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_MASK             0x0100
#define DSC_1_1_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_ALIGN            0
#define DSC_1_1_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_BITS             1
#define DSC_1_1_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_SHIFT            8

/* dsc_1_1 :: pi_ctrl0 :: pi_phase_dec [07:07] */
#define DSC_1_1_PI_CTRL0_PI_PHASE_DEC_MASK                         0x0080
#define DSC_1_1_PI_CTRL0_PI_PHASE_DEC_ALIGN                        0
#define DSC_1_1_PI_CTRL0_PI_PHASE_DEC_BITS                         1
#define DSC_1_1_PI_CTRL0_PI_PHASE_DEC_SHIFT                        7

/* dsc_1_1 :: pi_ctrl0 :: pi_phase_inc [06:06] */
#define DSC_1_1_PI_CTRL0_PI_PHASE_INC_MASK                         0x0040
#define DSC_1_1_PI_CTRL0_PI_PHASE_INC_ALIGN                        0
#define DSC_1_1_PI_CTRL0_PI_PHASE_INC_BITS                         1
#define DSC_1_1_PI_CTRL0_PI_PHASE_INC_SHIFT                        6

/* dsc_1_1 :: pi_ctrl0 :: pi_phase_strobe [05:05] */
#define DSC_1_1_PI_CTRL0_PI_PHASE_STROBE_MASK                      0x0020
#define DSC_1_1_PI_CTRL0_PI_PHASE_STROBE_ALIGN                     0
#define DSC_1_1_PI_CTRL0_PI_PHASE_STROBE_BITS                      1
#define DSC_1_1_PI_CTRL0_PI_PHASE_STROBE_SHIFT                     5

/* dsc_1_1 :: pi_ctrl0 :: pi_phase_delta [04:01] */
#define DSC_1_1_PI_CTRL0_PI_PHASE_DELTA_MASK                       0x001e
#define DSC_1_1_PI_CTRL0_PI_PHASE_DELTA_ALIGN                      0
#define DSC_1_1_PI_CTRL0_PI_PHASE_DELTA_BITS                       4
#define DSC_1_1_PI_CTRL0_PI_PHASE_DELTA_SHIFT                      1

/* dsc_1_1 :: pi_ctrl0 :: pi_phase_step_mult [00:00] */
#define DSC_1_1_PI_CTRL0_PI_PHASE_STEP_MULT_MASK                   0x0001
#define DSC_1_1_PI_CTRL0_PI_PHASE_STEP_MULT_ALIGN                  0
#define DSC_1_1_PI_CTRL0_PI_PHASE_STEP_MULT_BITS                   1
#define DSC_1_1_PI_CTRL0_PI_PHASE_STEP_MULT_SHIFT                  0


/****************************************************************************
 * dsc_1_1 :: pi_status0
 ***************************************************************************/
/* dsc_1_1 :: pi_status0 :: reserved_for_eco0 [15:14] */
#define DSC_1_1_PI_STATUS0_RESERVED_FOR_ECO0_MASK                  0xc000
#define DSC_1_1_PI_STATUS0_RESERVED_FOR_ECO0_ALIGN                 0
#define DSC_1_1_PI_STATUS0_RESERVED_FOR_ECO0_BITS                  2
#define DSC_1_1_PI_STATUS0_RESERVED_FOR_ECO0_SHIFT                 14

/* dsc_1_1 :: pi_status0 :: clk90_phase_offset [13:07] */
#define DSC_1_1_PI_STATUS0_CLK90_PHASE_OFFSET_MASK                 0x3f80
#define DSC_1_1_PI_STATUS0_CLK90_PHASE_OFFSET_ALIGN                0
#define DSC_1_1_PI_STATUS0_CLK90_PHASE_OFFSET_BITS                 7
#define DSC_1_1_PI_STATUS0_CLK90_PHASE_OFFSET_SHIFT                7

/* dsc_1_1 :: pi_status0 :: phase_cntr [06:00] */
#define DSC_1_1_PI_STATUS0_PHASE_CNTR_MASK                         0x007f
#define DSC_1_1_PI_STATUS0_PHASE_CNTR_ALIGN                        0
#define DSC_1_1_PI_STATUS0_PHASE_CNTR_BITS                         7
#define DSC_1_1_PI_STATUS0_PHASE_CNTR_SHIFT                        0


/****************************************************************************
 * dsc_1_1 :: dfe_vga_ctrl0
 ***************************************************************************/
/* dsc_1_1 :: dfe_vga_ctrl0 :: reserved_for_eco0 [15:12] */
#define DSC_1_1_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_MASK               0xf000
#define DSC_1_1_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_ALIGN              0
#define DSC_1_1_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_BITS               4
#define DSC_1_1_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_SHIFT              12

/* dsc_1_1 :: dfe_vga_ctrl0 :: trnsum_tap0_only [11:11] */
#define DSC_1_1_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_MASK                0x0800
#define DSC_1_1_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_ALIGN               0
#define DSC_1_1_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_BITS                1
#define DSC_1_1_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_SHIFT               11

/* dsc_1_1 :: dfe_vga_ctrl0 :: sum_m1err [10:10] */
#define DSC_1_1_DFE_VGA_CTRL0_SUM_M1ERR_MASK                       0x0400
#define DSC_1_1_DFE_VGA_CTRL0_SUM_M1ERR_ALIGN                      0
#define DSC_1_1_DFE_VGA_CTRL0_SUM_M1ERR_BITS                       1
#define DSC_1_1_DFE_VGA_CTRL0_SUM_M1ERR_SHIFT                      10

/* dsc_1_1 :: dfe_vga_ctrl0 :: dfe_vga_clken [09:09] */
#define DSC_1_1_DFE_VGA_CTRL0_DFE_VGA_CLKEN_MASK                   0x0200
#define DSC_1_1_DFE_VGA_CTRL0_DFE_VGA_CLKEN_ALIGN                  0
#define DSC_1_1_DFE_VGA_CTRL0_DFE_VGA_CLKEN_BITS                   1
#define DSC_1_1_DFE_VGA_CTRL0_DFE_VGA_CLKEN_SHIFT                  9

/* dsc_1_1 :: dfe_vga_ctrl0 :: hysteresis_en [08:08] */
#define DSC_1_1_DFE_VGA_CTRL0_HYSTERESIS_EN_MASK                   0x0100
#define DSC_1_1_DFE_VGA_CTRL0_HYSTERESIS_EN_ALIGN                  0
#define DSC_1_1_DFE_VGA_CTRL0_HYSTERESIS_EN_BITS                   1
#define DSC_1_1_DFE_VGA_CTRL0_HYSTERESIS_EN_SHIFT                  8

/* dsc_1_1 :: dfe_vga_ctrl0 :: dfe_vga_write_val [07:02] */
#define DSC_1_1_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_MASK               0x00fc
#define DSC_1_1_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_ALIGN              0
#define DSC_1_1_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_BITS               6
#define DSC_1_1_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_SHIFT              2

/* dsc_1_1 :: dfe_vga_ctrl0 :: vga_write_en [01:01] */
#define DSC_1_1_DFE_VGA_CTRL0_VGA_WRITE_EN_MASK                    0x0002
#define DSC_1_1_DFE_VGA_CTRL0_VGA_WRITE_EN_ALIGN                   0
#define DSC_1_1_DFE_VGA_CTRL0_VGA_WRITE_EN_BITS                    1
#define DSC_1_1_DFE_VGA_CTRL0_VGA_WRITE_EN_SHIFT                   1

/* dsc_1_1 :: dfe_vga_ctrl0 :: dfe_write_en [00:00] */
#define DSC_1_1_DFE_VGA_CTRL0_DFE_WRITE_EN_MASK                    0x0001
#define DSC_1_1_DFE_VGA_CTRL0_DFE_WRITE_EN_ALIGN                   0
#define DSC_1_1_DFE_VGA_CTRL0_DFE_WRITE_EN_BITS                    1
#define DSC_1_1_DFE_VGA_CTRL0_DFE_WRITE_EN_SHIFT                   0


/****************************************************************************
 * dsc_1_1 :: dfe_vga_ctrl1
 ***************************************************************************/
/* dsc_1_1 :: dfe_vga_ctrl1 :: reserved_for_eco0 [15:15] */
#define DSC_1_1_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_MASK               0x8000
#define DSC_1_1_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_ALIGN              0
#define DSC_1_1_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_BITS               1
#define DSC_1_1_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_SHIFT              15

/* dsc_1_1 :: dfe_vga_ctrl1 :: trnsum_otap_en [14:08] */
#define DSC_1_1_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_MASK                  0x7f00
#define DSC_1_1_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_ALIGN                 0
#define DSC_1_1_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_BITS                  7
#define DSC_1_1_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_SHIFT                 8

/* dsc_1_1 :: dfe_vga_ctrl1 :: trnsum_etap_en [07:01] */
#define DSC_1_1_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_MASK                  0x00fe
#define DSC_1_1_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_ALIGN                 0
#define DSC_1_1_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_BITS                  7
#define DSC_1_1_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_SHIFT                 1

/* dsc_1_1 :: dfe_vga_ctrl1 :: trnsum_en [00:00] */
#define DSC_1_1_DFE_VGA_CTRL1_TRNSUM_EN_MASK                       0x0001
#define DSC_1_1_DFE_VGA_CTRL1_TRNSUM_EN_ALIGN                      0
#define DSC_1_1_DFE_VGA_CTRL1_TRNSUM_EN_BITS                       1
#define DSC_1_1_DFE_VGA_CTRL1_TRNSUM_EN_SHIFT                      0


/****************************************************************************
 * dsc_1_1 :: dfe_vga_ctrl2
 ***************************************************************************/
/* dsc_1_1 :: dfe_vga_ctrl2 :: vga_polarity [15:15] */
#define DSC_1_1_DFE_VGA_CTRL2_VGA_POLARITY_MASK                    0x8000
#define DSC_1_1_DFE_VGA_CTRL2_VGA_POLARITY_ALIGN                   0
#define DSC_1_1_DFE_VGA_CTRL2_VGA_POLARITY_BITS                    1
#define DSC_1_1_DFE_VGA_CTRL2_VGA_POLARITY_SHIFT                   15

/* dsc_1_1 :: dfe_vga_ctrl2 :: dfe_polarity [14:14] */
#define DSC_1_1_DFE_VGA_CTRL2_DFE_POLARITY_MASK                    0x4000
#define DSC_1_1_DFE_VGA_CTRL2_DFE_POLARITY_ALIGN                   0
#define DSC_1_1_DFE_VGA_CTRL2_DFE_POLARITY_BITS                    1
#define DSC_1_1_DFE_VGA_CTRL2_DFE_POLARITY_SHIFT                   14

/* dsc_1_1 :: dfe_vga_ctrl2 :: trnsum_otap_sign [13:07] */
#define DSC_1_1_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_MASK                0x3f80
#define DSC_1_1_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_ALIGN               0
#define DSC_1_1_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_BITS                7
#define DSC_1_1_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_SHIFT               7

/* dsc_1_1 :: dfe_vga_ctrl2 :: trnsum_etap_sign [06:00] */
#define DSC_1_1_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_MASK                0x007f
#define DSC_1_1_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_ALIGN               0
#define DSC_1_1_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_BITS                7
#define DSC_1_1_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_SHIFT               0


/****************************************************************************
 * dsc_1_1 :: dfe_vga_ctrl3
 ***************************************************************************/
/* dsc_1_1 :: dfe_vga_ctrl3 :: reserved_for_eco0 [15:10] */
#define DSC_1_1_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_MASK               0xfc00
#define DSC_1_1_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_ALIGN              0
#define DSC_1_1_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_BITS               6
#define DSC_1_1_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_SHIFT              10

/* dsc_1_1 :: dfe_vga_ctrl3 :: vga_cor_sel_e [09:05] */
#define DSC_1_1_DFE_VGA_CTRL3_VGA_COR_SEL_E_MASK                   0x03e0
#define DSC_1_1_DFE_VGA_CTRL3_VGA_COR_SEL_E_ALIGN                  0
#define DSC_1_1_DFE_VGA_CTRL3_VGA_COR_SEL_E_BITS                   5
#define DSC_1_1_DFE_VGA_CTRL3_VGA_COR_SEL_E_SHIFT                  5

/* dsc_1_1 :: dfe_vga_ctrl3 :: vga_cor_sel_o [04:00] */
#define DSC_1_1_DFE_VGA_CTRL3_VGA_COR_SEL_O_MASK                   0x001f
#define DSC_1_1_DFE_VGA_CTRL3_VGA_COR_SEL_O_ALIGN                  0
#define DSC_1_1_DFE_VGA_CTRL3_VGA_COR_SEL_O_BITS                   5
#define DSC_1_1_DFE_VGA_CTRL3_VGA_COR_SEL_O_SHIFT                  0


/****************************************************************************
 * dsc_1_1 :: dfe_vga_ctrl4
 ***************************************************************************/
/* dsc_1_1 :: dfe_vga_ctrl4 :: reserved_for_eco0 [15:10] */
#define DSC_1_1_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_MASK               0xfc00
#define DSC_1_1_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_ALIGN              0
#define DSC_1_1_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_BITS               6
#define DSC_1_1_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_SHIFT              10

/* dsc_1_1 :: dfe_vga_ctrl4 :: dfe_cor_sel_e [09:05] */
#define DSC_1_1_DFE_VGA_CTRL4_DFE_COR_SEL_E_MASK                   0x03e0
#define DSC_1_1_DFE_VGA_CTRL4_DFE_COR_SEL_E_ALIGN                  0
#define DSC_1_1_DFE_VGA_CTRL4_DFE_COR_SEL_E_BITS                   5
#define DSC_1_1_DFE_VGA_CTRL4_DFE_COR_SEL_E_SHIFT                  5

/* dsc_1_1 :: dfe_vga_ctrl4 :: dfe_cor_sel_o [04:00] */
#define DSC_1_1_DFE_VGA_CTRL4_DFE_COR_SEL_O_MASK                   0x001f
#define DSC_1_1_DFE_VGA_CTRL4_DFE_COR_SEL_O_ALIGN                  0
#define DSC_1_1_DFE_VGA_CTRL4_DFE_COR_SEL_O_BITS                   5
#define DSC_1_1_DFE_VGA_CTRL4_DFE_COR_SEL_O_SHIFT                  0


/****************************************************************************
 * dsc_1_1 :: dfe_vga_status0
 ***************************************************************************/
/* dsc_1_1 :: dfe_vga_status0 :: vga_sum [15:11] */
#define DSC_1_1_DFE_VGA_STATUS0_VGA_SUM_MASK                       0xf800
#define DSC_1_1_DFE_VGA_STATUS0_VGA_SUM_ALIGN                      0
#define DSC_1_1_DFE_VGA_STATUS0_VGA_SUM_BITS                       5
#define DSC_1_1_DFE_VGA_STATUS0_VGA_SUM_SHIFT                      11

/* dsc_1_1 :: dfe_vga_status0 :: trnsum [10:00] */
#define DSC_1_1_DFE_VGA_STATUS0_TRNSUM_MASK                        0x07ff
#define DSC_1_1_DFE_VGA_STATUS0_TRNSUM_ALIGN                       0
#define DSC_1_1_DFE_VGA_STATUS0_TRNSUM_BITS                        11
#define DSC_1_1_DFE_VGA_STATUS0_TRNSUM_SHIFT                       0


/****************************************************************************
 * dsc_1_1 :: dfe_vga_status1
 ***************************************************************************/
/* dsc_1_1 :: dfe_vga_status1 :: odd_dfe_acc [15:06] */
#define DSC_1_1_DFE_VGA_STATUS1_ODD_DFE_ACC_MASK                   0xffc0
#define DSC_1_1_DFE_VGA_STATUS1_ODD_DFE_ACC_ALIGN                  0
#define DSC_1_1_DFE_VGA_STATUS1_ODD_DFE_ACC_BITS                   10
#define DSC_1_1_DFE_VGA_STATUS1_ODD_DFE_ACC_SHIFT                  6

/* dsc_1_1 :: dfe_vga_status1 :: dfe_tap_bin [05:00] */
#define DSC_1_1_DFE_VGA_STATUS1_DFE_TAP_BIN_MASK                   0x003f
#define DSC_1_1_DFE_VGA_STATUS1_DFE_TAP_BIN_ALIGN                  0
#define DSC_1_1_DFE_VGA_STATUS1_DFE_TAP_BIN_BITS                   6
#define DSC_1_1_DFE_VGA_STATUS1_DFE_TAP_BIN_SHIFT                  0


/****************************************************************************
 * dsc_1_1 :: dfe_vga_status2
 ***************************************************************************/
/* dsc_1_1 :: dfe_vga_status2 :: reserved_for_eco0 [15:10] */
#define DSC_1_1_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_MASK             0xfc00
#define DSC_1_1_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_ALIGN            0
#define DSC_1_1_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_BITS             6
#define DSC_1_1_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_SHIFT            10

/* dsc_1_1 :: dfe_vga_status2 :: evn_dfe_acc [09:00] */
#define DSC_1_1_DFE_VGA_STATUS2_EVN_DFE_ACC_MASK                   0x03ff
#define DSC_1_1_DFE_VGA_STATUS2_EVN_DFE_ACC_ALIGN                  0
#define DSC_1_1_DFE_VGA_STATUS2_EVN_DFE_ACC_BITS                   10
#define DSC_1_1_DFE_VGA_STATUS2_EVN_DFE_ACC_SHIFT                  0


/****************************************************************************
 * XGXS16G_USER_dsc_1_2
 ***************************************************************************/
/****************************************************************************
 * dsc_1_2 :: cdr_ctrl0
 ***************************************************************************/
/* dsc_1_2 :: cdr_ctrl0 :: reserved_for_eco0 [15:09] */
#define DSC_1_2_CDR_CTRL0_RESERVED_FOR_ECO0_MASK                   0xfe00
#define DSC_1_2_CDR_CTRL0_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC_1_2_CDR_CTRL0_RESERVED_FOR_ECO0_BITS                   7
#define DSC_1_2_CDR_CTRL0_RESERVED_FOR_ECO0_SHIFT                  9

/* dsc_1_2 :: cdr_ctrl0 :: cdrbr_bwsel_integ [08:07] */
#define DSC_1_2_CDR_CTRL0_CDRBR_BWSEL_INTEG_MASK                   0x0180
#define DSC_1_2_CDR_CTRL0_CDRBR_BWSEL_INTEG_ALIGN                  0
#define DSC_1_2_CDR_CTRL0_CDRBR_BWSEL_INTEG_BITS                   2
#define DSC_1_2_CDR_CTRL0_CDRBR_BWSEL_INTEG_SHIFT                  7

/* dsc_1_2 :: cdr_ctrl0 :: cdrbr_bwsel_prop [06:04] */
#define DSC_1_2_CDR_CTRL0_CDRBR_BWSEL_PROP_MASK                    0x0070
#define DSC_1_2_CDR_CTRL0_CDRBR_BWSEL_PROP_ALIGN                   0
#define DSC_1_2_CDR_CTRL0_CDRBR_BWSEL_PROP_BITS                    3
#define DSC_1_2_CDR_CTRL0_CDRBR_BWSEL_PROP_SHIFT                   4

/* dsc_1_2 :: cdr_ctrl0 :: cdrbr_polarity [03:03] */
#define DSC_1_2_CDR_CTRL0_CDRBR_POLARITY_MASK                      0x0008
#define DSC_1_2_CDR_CTRL0_CDRBR_POLARITY_ALIGN                     0
#define DSC_1_2_CDR_CTRL0_CDRBR_POLARITY_BITS                      1
#define DSC_1_2_CDR_CTRL0_CDRBR_POLARITY_SHIFT                     3

/* dsc_1_2 :: cdr_ctrl0 :: cdrbr_third_vec_en [02:02] */
#define DSC_1_2_CDR_CTRL0_CDRBR_THIRD_VEC_EN_MASK                  0x0004
#define DSC_1_2_CDR_CTRL0_CDRBR_THIRD_VEC_EN_ALIGN                 0
#define DSC_1_2_CDR_CTRL0_CDRBR_THIRD_VEC_EN_BITS                  1
#define DSC_1_2_CDR_CTRL0_CDRBR_THIRD_VEC_EN_SHIFT                 2

/* dsc_1_2 :: cdr_ctrl0 :: reserved_for_eco1 [01:00] */
#define DSC_1_2_CDR_CTRL0_RESERVED_FOR_ECO1_MASK                   0x0003
#define DSC_1_2_CDR_CTRL0_RESERVED_FOR_ECO1_ALIGN                  0
#define DSC_1_2_CDR_CTRL0_RESERVED_FOR_ECO1_BITS                   2
#define DSC_1_2_CDR_CTRL0_RESERVED_FOR_ECO1_SHIFT                  0


/****************************************************************************
 * dsc_1_2 :: cdr_ctrl1
 ***************************************************************************/
/* dsc_1_2 :: cdr_ctrl1 :: reserved_for_eco0 [15:10] */
#define DSC_1_2_CDR_CTRL1_RESERVED_FOR_ECO0_MASK                   0xfc00
#define DSC_1_2_CDR_CTRL1_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC_1_2_CDR_CTRL1_RESERVED_FOR_ECO0_BITS                   6
#define DSC_1_2_CDR_CTRL1_RESERVED_FOR_ECO0_SHIFT                  10

/* dsc_1_2 :: cdr_ctrl1 :: cdr_phase_err_frz [09:09] */
#define DSC_1_2_CDR_CTRL1_CDR_PHASE_ERR_FRZ_MASK                   0x0200
#define DSC_1_2_CDR_CTRL1_CDR_PHASE_ERR_FRZ_ALIGN                  0
#define DSC_1_2_CDR_CTRL1_CDR_PHASE_ERR_FRZ_BITS                   1
#define DSC_1_2_CDR_CTRL1_CDR_PHASE_ERR_FRZ_SHIFT                  9

/* dsc_1_2 :: cdr_ctrl1 :: cdr_integ_reg_clr [08:08] */
#define DSC_1_2_CDR_CTRL1_CDR_INTEG_REG_CLR_MASK                   0x0100
#define DSC_1_2_CDR_CTRL1_CDR_INTEG_REG_CLR_ALIGN                  0
#define DSC_1_2_CDR_CTRL1_CDR_INTEG_REG_CLR_BITS                   1
#define DSC_1_2_CDR_CTRL1_CDR_INTEG_REG_CLR_SHIFT                  8

/* dsc_1_2 :: cdr_ctrl1 :: cdr_freq_override_val [07:03] */
#define DSC_1_2_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_MASK               0x00f8
#define DSC_1_2_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_ALIGN              0
#define DSC_1_2_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_BITS               5
#define DSC_1_2_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_SHIFT              3

/* dsc_1_2 :: cdr_ctrl1 :: cdr_freq_override_en [02:02] */
#define DSC_1_2_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_MASK                0x0004
#define DSC_1_2_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_ALIGN               0
#define DSC_1_2_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_BITS                1
#define DSC_1_2_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_SHIFT               2

/* dsc_1_2 :: cdr_ctrl1 :: cdr_freq_upd_en [01:01] */
#define DSC_1_2_CDR_CTRL1_CDR_FREQ_UPD_EN_MASK                     0x0002
#define DSC_1_2_CDR_CTRL1_CDR_FREQ_UPD_EN_ALIGN                    0
#define DSC_1_2_CDR_CTRL1_CDR_FREQ_UPD_EN_BITS                     1
#define DSC_1_2_CDR_CTRL1_CDR_FREQ_UPD_EN_SHIFT                    1

/* dsc_1_2 :: cdr_ctrl1 :: cdr_freq_en [00:00] */
#define DSC_1_2_CDR_CTRL1_CDR_FREQ_EN_MASK                         0x0001
#define DSC_1_2_CDR_CTRL1_CDR_FREQ_EN_ALIGN                        0
#define DSC_1_2_CDR_CTRL1_CDR_FREQ_EN_BITS                         1
#define DSC_1_2_CDR_CTRL1_CDR_FREQ_EN_SHIFT                        0


/****************************************************************************
 * dsc_1_2 :: cdr_ctrl2
 ***************************************************************************/
/* dsc_1_2 :: cdr_ctrl2 :: reserved_for_eco0 [15:14] */
#define DSC_1_2_CDR_CTRL2_RESERVED_FOR_ECO0_MASK                   0xc000
#define DSC_1_2_CDR_CTRL2_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC_1_2_CDR_CTRL2_RESERVED_FOR_ECO0_BITS                   2
#define DSC_1_2_CDR_CTRL2_RESERVED_FOR_ECO0_SHIFT                  14

/* dsc_1_2 :: cdr_ctrl2 :: cdros_bwsel_prop [13:10] */
#define DSC_1_2_CDR_CTRL2_CDROS_BWSEL_PROP_MASK                    0x3c00
#define DSC_1_2_CDR_CTRL2_CDROS_BWSEL_PROP_ALIGN                   0
#define DSC_1_2_CDR_CTRL2_CDROS_BWSEL_PROP_BITS                    4
#define DSC_1_2_CDR_CTRL2_CDROS_BWSEL_PROP_SHIFT                   10

/* dsc_1_2 :: cdr_ctrl2 :: cdros_bwsel_integ [09:06] */
#define DSC_1_2_CDR_CTRL2_CDROS_BWSEL_INTEG_MASK                   0x03c0
#define DSC_1_2_CDR_CTRL2_CDROS_BWSEL_INTEG_ALIGN                  0
#define DSC_1_2_CDR_CTRL2_CDROS_BWSEL_INTEG_BITS                   4
#define DSC_1_2_CDR_CTRL2_CDROS_BWSEL_INTEG_SHIFT                  6

/* dsc_1_2 :: cdr_ctrl2 :: cdros_falling_edge [05:05] */
#define DSC_1_2_CDR_CTRL2_CDROS_FALLING_EDGE_MASK                  0x0020
#define DSC_1_2_CDR_CTRL2_CDROS_FALLING_EDGE_ALIGN                 0
#define DSC_1_2_CDR_CTRL2_CDROS_FALLING_EDGE_BITS                  1
#define DSC_1_2_CDR_CTRL2_CDROS_FALLING_EDGE_SHIFT                 5

/* dsc_1_2 :: cdr_ctrl2 :: cdros_rising_edge [04:04] */
#define DSC_1_2_CDR_CTRL2_CDROS_RISING_EDGE_MASK                   0x0010
#define DSC_1_2_CDR_CTRL2_CDROS_RISING_EDGE_ALIGN                  0
#define DSC_1_2_CDR_CTRL2_CDROS_RISING_EDGE_BITS                   1
#define DSC_1_2_CDR_CTRL2_CDROS_RISING_EDGE_SHIFT                  4

/* dsc_1_2 :: cdr_ctrl2 :: cdros_phase_sat_ctrl [03:02] */
#define DSC_1_2_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_MASK                0x000c
#define DSC_1_2_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_ALIGN               0
#define DSC_1_2_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_BITS                2
#define DSC_1_2_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_SHIFT               2

/* dsc_1_2 :: cdr_ctrl2 :: cdros_peak_polarity [01:01] */
#define DSC_1_2_CDR_CTRL2_CDROS_PEAK_POLARITY_MASK                 0x0002
#define DSC_1_2_CDR_CTRL2_CDROS_PEAK_POLARITY_ALIGN                0
#define DSC_1_2_CDR_CTRL2_CDROS_PEAK_POLARITY_BITS                 1
#define DSC_1_2_CDR_CTRL2_CDROS_PEAK_POLARITY_SHIFT                1

/* dsc_1_2 :: cdr_ctrl2 :: cdros_zero_polarity [00:00] */
#define DSC_1_2_CDR_CTRL2_CDROS_ZERO_POLARITY_MASK                 0x0001
#define DSC_1_2_CDR_CTRL2_CDROS_ZERO_POLARITY_ALIGN                0
#define DSC_1_2_CDR_CTRL2_CDROS_ZERO_POLARITY_BITS                 1
#define DSC_1_2_CDR_CTRL2_CDROS_ZERO_POLARITY_SHIFT                0


/****************************************************************************
 * dsc_1_2 :: cdr_status0
 ***************************************************************************/
/* dsc_1_2 :: cdr_status0 :: integ_reg [15:00] */
#define DSC_1_2_CDR_STATUS0_INTEG_REG_MASK                         0xffff
#define DSC_1_2_CDR_STATUS0_INTEG_REG_ALIGN                        0
#define DSC_1_2_CDR_STATUS0_INTEG_REG_BITS                         16
#define DSC_1_2_CDR_STATUS0_INTEG_REG_SHIFT                        0


/****************************************************************************
 * dsc_1_2 :: cdr_status1
 ***************************************************************************/
/* dsc_1_2 :: cdr_status1 :: reserved_for_eco0 [15:06] */
#define DSC_1_2_CDR_STATUS1_RESERVED_FOR_ECO0_MASK                 0xffc0
#define DSC_1_2_CDR_STATUS1_RESERVED_FOR_ECO0_ALIGN                0
#define DSC_1_2_CDR_STATUS1_RESERVED_FOR_ECO0_BITS                 10
#define DSC_1_2_CDR_STATUS1_RESERVED_FOR_ECO0_SHIFT                6

/* dsc_1_2 :: cdr_status1 :: phase_err [05:00] */
#define DSC_1_2_CDR_STATUS1_PHASE_ERR_MASK                         0x003f
#define DSC_1_2_CDR_STATUS1_PHASE_ERR_ALIGN                        0
#define DSC_1_2_CDR_STATUS1_PHASE_ERR_BITS                         6
#define DSC_1_2_CDR_STATUS1_PHASE_ERR_SHIFT                        0


/****************************************************************************
 * dsc_1_2 :: pi_ctrl0
 ***************************************************************************/
/* dsc_1_2 :: pi_ctrl0 :: reserved_for_eco0 [15:11] */
#define DSC_1_2_PI_CTRL0_RESERVED_FOR_ECO0_MASK                    0xf800
#define DSC_1_2_PI_CTRL0_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC_1_2_PI_CTRL0_RESERVED_FOR_ECO0_BITS                    5
#define DSC_1_2_PI_CTRL0_RESERVED_FOR_ECO0_SHIFT                   11

/* dsc_1_2 :: pi_ctrl0 :: pi_phase_invert [10:10] */
#define DSC_1_2_PI_CTRL0_PI_PHASE_INVERT_MASK                      0x0400
#define DSC_1_2_PI_CTRL0_PI_PHASE_INVERT_ALIGN                     0
#define DSC_1_2_PI_CTRL0_PI_PHASE_INVERT_BITS                      1
#define DSC_1_2_PI_CTRL0_PI_PHASE_INVERT_SHIFT                     10

/* dsc_1_2 :: pi_ctrl0 :: pi_dual_phase_override [09:09] */
#define DSC_1_2_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_MASK               0x0200
#define DSC_1_2_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_ALIGN              0
#define DSC_1_2_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_BITS               1
#define DSC_1_2_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_SHIFT              9

/* dsc_1_2 :: pi_ctrl0 :: pi_clk90_offset_override [08:08] */
#define DSC_1_2_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_MASK             0x0100
#define DSC_1_2_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_ALIGN            0
#define DSC_1_2_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_BITS             1
#define DSC_1_2_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_SHIFT            8

/* dsc_1_2 :: pi_ctrl0 :: pi_phase_dec [07:07] */
#define DSC_1_2_PI_CTRL0_PI_PHASE_DEC_MASK                         0x0080
#define DSC_1_2_PI_CTRL0_PI_PHASE_DEC_ALIGN                        0
#define DSC_1_2_PI_CTRL0_PI_PHASE_DEC_BITS                         1
#define DSC_1_2_PI_CTRL0_PI_PHASE_DEC_SHIFT                        7

/* dsc_1_2 :: pi_ctrl0 :: pi_phase_inc [06:06] */
#define DSC_1_2_PI_CTRL0_PI_PHASE_INC_MASK                         0x0040
#define DSC_1_2_PI_CTRL0_PI_PHASE_INC_ALIGN                        0
#define DSC_1_2_PI_CTRL0_PI_PHASE_INC_BITS                         1
#define DSC_1_2_PI_CTRL0_PI_PHASE_INC_SHIFT                        6

/* dsc_1_2 :: pi_ctrl0 :: pi_phase_strobe [05:05] */
#define DSC_1_2_PI_CTRL0_PI_PHASE_STROBE_MASK                      0x0020
#define DSC_1_2_PI_CTRL0_PI_PHASE_STROBE_ALIGN                     0
#define DSC_1_2_PI_CTRL0_PI_PHASE_STROBE_BITS                      1
#define DSC_1_2_PI_CTRL0_PI_PHASE_STROBE_SHIFT                     5

/* dsc_1_2 :: pi_ctrl0 :: pi_phase_delta [04:01] */
#define DSC_1_2_PI_CTRL0_PI_PHASE_DELTA_MASK                       0x001e
#define DSC_1_2_PI_CTRL0_PI_PHASE_DELTA_ALIGN                      0
#define DSC_1_2_PI_CTRL0_PI_PHASE_DELTA_BITS                       4
#define DSC_1_2_PI_CTRL0_PI_PHASE_DELTA_SHIFT                      1

/* dsc_1_2 :: pi_ctrl0 :: pi_phase_step_mult [00:00] */
#define DSC_1_2_PI_CTRL0_PI_PHASE_STEP_MULT_MASK                   0x0001
#define DSC_1_2_PI_CTRL0_PI_PHASE_STEP_MULT_ALIGN                  0
#define DSC_1_2_PI_CTRL0_PI_PHASE_STEP_MULT_BITS                   1
#define DSC_1_2_PI_CTRL0_PI_PHASE_STEP_MULT_SHIFT                  0


/****************************************************************************
 * dsc_1_2 :: pi_status0
 ***************************************************************************/
/* dsc_1_2 :: pi_status0 :: reserved_for_eco0 [15:14] */
#define DSC_1_2_PI_STATUS0_RESERVED_FOR_ECO0_MASK                  0xc000
#define DSC_1_2_PI_STATUS0_RESERVED_FOR_ECO0_ALIGN                 0
#define DSC_1_2_PI_STATUS0_RESERVED_FOR_ECO0_BITS                  2
#define DSC_1_2_PI_STATUS0_RESERVED_FOR_ECO0_SHIFT                 14

/* dsc_1_2 :: pi_status0 :: clk90_phase_offset [13:07] */
#define DSC_1_2_PI_STATUS0_CLK90_PHASE_OFFSET_MASK                 0x3f80
#define DSC_1_2_PI_STATUS0_CLK90_PHASE_OFFSET_ALIGN                0
#define DSC_1_2_PI_STATUS0_CLK90_PHASE_OFFSET_BITS                 7
#define DSC_1_2_PI_STATUS0_CLK90_PHASE_OFFSET_SHIFT                7

/* dsc_1_2 :: pi_status0 :: phase_cntr [06:00] */
#define DSC_1_2_PI_STATUS0_PHASE_CNTR_MASK                         0x007f
#define DSC_1_2_PI_STATUS0_PHASE_CNTR_ALIGN                        0
#define DSC_1_2_PI_STATUS0_PHASE_CNTR_BITS                         7
#define DSC_1_2_PI_STATUS0_PHASE_CNTR_SHIFT                        0


/****************************************************************************
 * dsc_1_2 :: dfe_vga_ctrl0
 ***************************************************************************/
/* dsc_1_2 :: dfe_vga_ctrl0 :: reserved_for_eco0 [15:12] */
#define DSC_1_2_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_MASK               0xf000
#define DSC_1_2_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_ALIGN              0
#define DSC_1_2_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_BITS               4
#define DSC_1_2_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_SHIFT              12

/* dsc_1_2 :: dfe_vga_ctrl0 :: trnsum_tap0_only [11:11] */
#define DSC_1_2_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_MASK                0x0800
#define DSC_1_2_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_ALIGN               0
#define DSC_1_2_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_BITS                1
#define DSC_1_2_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_SHIFT               11

/* dsc_1_2 :: dfe_vga_ctrl0 :: sum_m1err [10:10] */
#define DSC_1_2_DFE_VGA_CTRL0_SUM_M1ERR_MASK                       0x0400
#define DSC_1_2_DFE_VGA_CTRL0_SUM_M1ERR_ALIGN                      0
#define DSC_1_2_DFE_VGA_CTRL0_SUM_M1ERR_BITS                       1
#define DSC_1_2_DFE_VGA_CTRL0_SUM_M1ERR_SHIFT                      10

/* dsc_1_2 :: dfe_vga_ctrl0 :: dfe_vga_clken [09:09] */
#define DSC_1_2_DFE_VGA_CTRL0_DFE_VGA_CLKEN_MASK                   0x0200
#define DSC_1_2_DFE_VGA_CTRL0_DFE_VGA_CLKEN_ALIGN                  0
#define DSC_1_2_DFE_VGA_CTRL0_DFE_VGA_CLKEN_BITS                   1
#define DSC_1_2_DFE_VGA_CTRL0_DFE_VGA_CLKEN_SHIFT                  9

/* dsc_1_2 :: dfe_vga_ctrl0 :: hysteresis_en [08:08] */
#define DSC_1_2_DFE_VGA_CTRL0_HYSTERESIS_EN_MASK                   0x0100
#define DSC_1_2_DFE_VGA_CTRL0_HYSTERESIS_EN_ALIGN                  0
#define DSC_1_2_DFE_VGA_CTRL0_HYSTERESIS_EN_BITS                   1
#define DSC_1_2_DFE_VGA_CTRL0_HYSTERESIS_EN_SHIFT                  8

/* dsc_1_2 :: dfe_vga_ctrl0 :: dfe_vga_write_val [07:02] */
#define DSC_1_2_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_MASK               0x00fc
#define DSC_1_2_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_ALIGN              0
#define DSC_1_2_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_BITS               6
#define DSC_1_2_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_SHIFT              2

/* dsc_1_2 :: dfe_vga_ctrl0 :: vga_write_en [01:01] */
#define DSC_1_2_DFE_VGA_CTRL0_VGA_WRITE_EN_MASK                    0x0002
#define DSC_1_2_DFE_VGA_CTRL0_VGA_WRITE_EN_ALIGN                   0
#define DSC_1_2_DFE_VGA_CTRL0_VGA_WRITE_EN_BITS                    1
#define DSC_1_2_DFE_VGA_CTRL0_VGA_WRITE_EN_SHIFT                   1

/* dsc_1_2 :: dfe_vga_ctrl0 :: dfe_write_en [00:00] */
#define DSC_1_2_DFE_VGA_CTRL0_DFE_WRITE_EN_MASK                    0x0001
#define DSC_1_2_DFE_VGA_CTRL0_DFE_WRITE_EN_ALIGN                   0
#define DSC_1_2_DFE_VGA_CTRL0_DFE_WRITE_EN_BITS                    1
#define DSC_1_2_DFE_VGA_CTRL0_DFE_WRITE_EN_SHIFT                   0


/****************************************************************************
 * dsc_1_2 :: dfe_vga_ctrl1
 ***************************************************************************/
/* dsc_1_2 :: dfe_vga_ctrl1 :: reserved_for_eco0 [15:15] */
#define DSC_1_2_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_MASK               0x8000
#define DSC_1_2_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_ALIGN              0
#define DSC_1_2_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_BITS               1
#define DSC_1_2_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_SHIFT              15

/* dsc_1_2 :: dfe_vga_ctrl1 :: trnsum_otap_en [14:08] */
#define DSC_1_2_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_MASK                  0x7f00
#define DSC_1_2_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_ALIGN                 0
#define DSC_1_2_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_BITS                  7
#define DSC_1_2_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_SHIFT                 8

/* dsc_1_2 :: dfe_vga_ctrl1 :: trnsum_etap_en [07:01] */
#define DSC_1_2_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_MASK                  0x00fe
#define DSC_1_2_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_ALIGN                 0
#define DSC_1_2_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_BITS                  7
#define DSC_1_2_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_SHIFT                 1

/* dsc_1_2 :: dfe_vga_ctrl1 :: trnsum_en [00:00] */
#define DSC_1_2_DFE_VGA_CTRL1_TRNSUM_EN_MASK                       0x0001
#define DSC_1_2_DFE_VGA_CTRL1_TRNSUM_EN_ALIGN                      0
#define DSC_1_2_DFE_VGA_CTRL1_TRNSUM_EN_BITS                       1
#define DSC_1_2_DFE_VGA_CTRL1_TRNSUM_EN_SHIFT                      0


/****************************************************************************
 * dsc_1_2 :: dfe_vga_ctrl2
 ***************************************************************************/
/* dsc_1_2 :: dfe_vga_ctrl2 :: vga_polarity [15:15] */
#define DSC_1_2_DFE_VGA_CTRL2_VGA_POLARITY_MASK                    0x8000
#define DSC_1_2_DFE_VGA_CTRL2_VGA_POLARITY_ALIGN                   0
#define DSC_1_2_DFE_VGA_CTRL2_VGA_POLARITY_BITS                    1
#define DSC_1_2_DFE_VGA_CTRL2_VGA_POLARITY_SHIFT                   15

/* dsc_1_2 :: dfe_vga_ctrl2 :: dfe_polarity [14:14] */
#define DSC_1_2_DFE_VGA_CTRL2_DFE_POLARITY_MASK                    0x4000
#define DSC_1_2_DFE_VGA_CTRL2_DFE_POLARITY_ALIGN                   0
#define DSC_1_2_DFE_VGA_CTRL2_DFE_POLARITY_BITS                    1
#define DSC_1_2_DFE_VGA_CTRL2_DFE_POLARITY_SHIFT                   14

/* dsc_1_2 :: dfe_vga_ctrl2 :: trnsum_otap_sign [13:07] */
#define DSC_1_2_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_MASK                0x3f80
#define DSC_1_2_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_ALIGN               0
#define DSC_1_2_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_BITS                7
#define DSC_1_2_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_SHIFT               7

/* dsc_1_2 :: dfe_vga_ctrl2 :: trnsum_etap_sign [06:00] */
#define DSC_1_2_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_MASK                0x007f
#define DSC_1_2_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_ALIGN               0
#define DSC_1_2_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_BITS                7
#define DSC_1_2_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_SHIFT               0


/****************************************************************************
 * dsc_1_2 :: dfe_vga_ctrl3
 ***************************************************************************/
/* dsc_1_2 :: dfe_vga_ctrl3 :: reserved_for_eco0 [15:10] */
#define DSC_1_2_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_MASK               0xfc00
#define DSC_1_2_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_ALIGN              0
#define DSC_1_2_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_BITS               6
#define DSC_1_2_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_SHIFT              10

/* dsc_1_2 :: dfe_vga_ctrl3 :: vga_cor_sel_e [09:05] */
#define DSC_1_2_DFE_VGA_CTRL3_VGA_COR_SEL_E_MASK                   0x03e0
#define DSC_1_2_DFE_VGA_CTRL3_VGA_COR_SEL_E_ALIGN                  0
#define DSC_1_2_DFE_VGA_CTRL3_VGA_COR_SEL_E_BITS                   5
#define DSC_1_2_DFE_VGA_CTRL3_VGA_COR_SEL_E_SHIFT                  5

/* dsc_1_2 :: dfe_vga_ctrl3 :: vga_cor_sel_o [04:00] */
#define DSC_1_2_DFE_VGA_CTRL3_VGA_COR_SEL_O_MASK                   0x001f
#define DSC_1_2_DFE_VGA_CTRL3_VGA_COR_SEL_O_ALIGN                  0
#define DSC_1_2_DFE_VGA_CTRL3_VGA_COR_SEL_O_BITS                   5
#define DSC_1_2_DFE_VGA_CTRL3_VGA_COR_SEL_O_SHIFT                  0


/****************************************************************************
 * dsc_1_2 :: dfe_vga_ctrl4
 ***************************************************************************/
/* dsc_1_2 :: dfe_vga_ctrl4 :: reserved_for_eco0 [15:10] */
#define DSC_1_2_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_MASK               0xfc00
#define DSC_1_2_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_ALIGN              0
#define DSC_1_2_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_BITS               6
#define DSC_1_2_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_SHIFT              10

/* dsc_1_2 :: dfe_vga_ctrl4 :: dfe_cor_sel_e [09:05] */
#define DSC_1_2_DFE_VGA_CTRL4_DFE_COR_SEL_E_MASK                   0x03e0
#define DSC_1_2_DFE_VGA_CTRL4_DFE_COR_SEL_E_ALIGN                  0
#define DSC_1_2_DFE_VGA_CTRL4_DFE_COR_SEL_E_BITS                   5
#define DSC_1_2_DFE_VGA_CTRL4_DFE_COR_SEL_E_SHIFT                  5

/* dsc_1_2 :: dfe_vga_ctrl4 :: dfe_cor_sel_o [04:00] */
#define DSC_1_2_DFE_VGA_CTRL4_DFE_COR_SEL_O_MASK                   0x001f
#define DSC_1_2_DFE_VGA_CTRL4_DFE_COR_SEL_O_ALIGN                  0
#define DSC_1_2_DFE_VGA_CTRL4_DFE_COR_SEL_O_BITS                   5
#define DSC_1_2_DFE_VGA_CTRL4_DFE_COR_SEL_O_SHIFT                  0


/****************************************************************************
 * dsc_1_2 :: dfe_vga_status0
 ***************************************************************************/
/* dsc_1_2 :: dfe_vga_status0 :: vga_sum [15:11] */
#define DSC_1_2_DFE_VGA_STATUS0_VGA_SUM_MASK                       0xf800
#define DSC_1_2_DFE_VGA_STATUS0_VGA_SUM_ALIGN                      0
#define DSC_1_2_DFE_VGA_STATUS0_VGA_SUM_BITS                       5
#define DSC_1_2_DFE_VGA_STATUS0_VGA_SUM_SHIFT                      11

/* dsc_1_2 :: dfe_vga_status0 :: trnsum [10:00] */
#define DSC_1_2_DFE_VGA_STATUS0_TRNSUM_MASK                        0x07ff
#define DSC_1_2_DFE_VGA_STATUS0_TRNSUM_ALIGN                       0
#define DSC_1_2_DFE_VGA_STATUS0_TRNSUM_BITS                        11
#define DSC_1_2_DFE_VGA_STATUS0_TRNSUM_SHIFT                       0


/****************************************************************************
 * dsc_1_2 :: dfe_vga_status1
 ***************************************************************************/
/* dsc_1_2 :: dfe_vga_status1 :: odd_dfe_acc [15:06] */
#define DSC_1_2_DFE_VGA_STATUS1_ODD_DFE_ACC_MASK                   0xffc0
#define DSC_1_2_DFE_VGA_STATUS1_ODD_DFE_ACC_ALIGN                  0
#define DSC_1_2_DFE_VGA_STATUS1_ODD_DFE_ACC_BITS                   10
#define DSC_1_2_DFE_VGA_STATUS1_ODD_DFE_ACC_SHIFT                  6

/* dsc_1_2 :: dfe_vga_status1 :: dfe_tap_bin [05:00] */
#define DSC_1_2_DFE_VGA_STATUS1_DFE_TAP_BIN_MASK                   0x003f
#define DSC_1_2_DFE_VGA_STATUS1_DFE_TAP_BIN_ALIGN                  0
#define DSC_1_2_DFE_VGA_STATUS1_DFE_TAP_BIN_BITS                   6
#define DSC_1_2_DFE_VGA_STATUS1_DFE_TAP_BIN_SHIFT                  0


/****************************************************************************
 * dsc_1_2 :: dfe_vga_status2
 ***************************************************************************/
/* dsc_1_2 :: dfe_vga_status2 :: reserved_for_eco0 [15:10] */
#define DSC_1_2_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_MASK             0xfc00
#define DSC_1_2_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_ALIGN            0
#define DSC_1_2_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_BITS             6
#define DSC_1_2_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_SHIFT            10

/* dsc_1_2 :: dfe_vga_status2 :: evn_dfe_acc [09:00] */
#define DSC_1_2_DFE_VGA_STATUS2_EVN_DFE_ACC_MASK                   0x03ff
#define DSC_1_2_DFE_VGA_STATUS2_EVN_DFE_ACC_ALIGN                  0
#define DSC_1_2_DFE_VGA_STATUS2_EVN_DFE_ACC_BITS                   10
#define DSC_1_2_DFE_VGA_STATUS2_EVN_DFE_ACC_SHIFT                  0


/****************************************************************************
 * XGXS16G_USER_dsc_1_3
 ***************************************************************************/
/****************************************************************************
 * dsc_1_3 :: cdr_ctrl0
 ***************************************************************************/
/* dsc_1_3 :: cdr_ctrl0 :: reserved_for_eco0 [15:09] */
#define DSC_1_3_CDR_CTRL0_RESERVED_FOR_ECO0_MASK                   0xfe00
#define DSC_1_3_CDR_CTRL0_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC_1_3_CDR_CTRL0_RESERVED_FOR_ECO0_BITS                   7
#define DSC_1_3_CDR_CTRL0_RESERVED_FOR_ECO0_SHIFT                  9

/* dsc_1_3 :: cdr_ctrl0 :: cdrbr_bwsel_integ [08:07] */
#define DSC_1_3_CDR_CTRL0_CDRBR_BWSEL_INTEG_MASK                   0x0180
#define DSC_1_3_CDR_CTRL0_CDRBR_BWSEL_INTEG_ALIGN                  0
#define DSC_1_3_CDR_CTRL0_CDRBR_BWSEL_INTEG_BITS                   2
#define DSC_1_3_CDR_CTRL0_CDRBR_BWSEL_INTEG_SHIFT                  7

/* dsc_1_3 :: cdr_ctrl0 :: cdrbr_bwsel_prop [06:04] */
#define DSC_1_3_CDR_CTRL0_CDRBR_BWSEL_PROP_MASK                    0x0070
#define DSC_1_3_CDR_CTRL0_CDRBR_BWSEL_PROP_ALIGN                   0
#define DSC_1_3_CDR_CTRL0_CDRBR_BWSEL_PROP_BITS                    3
#define DSC_1_3_CDR_CTRL0_CDRBR_BWSEL_PROP_SHIFT                   4

/* dsc_1_3 :: cdr_ctrl0 :: cdrbr_polarity [03:03] */
#define DSC_1_3_CDR_CTRL0_CDRBR_POLARITY_MASK                      0x0008
#define DSC_1_3_CDR_CTRL0_CDRBR_POLARITY_ALIGN                     0
#define DSC_1_3_CDR_CTRL0_CDRBR_POLARITY_BITS                      1
#define DSC_1_3_CDR_CTRL0_CDRBR_POLARITY_SHIFT                     3

/* dsc_1_3 :: cdr_ctrl0 :: cdrbr_third_vec_en [02:02] */
#define DSC_1_3_CDR_CTRL0_CDRBR_THIRD_VEC_EN_MASK                  0x0004
#define DSC_1_3_CDR_CTRL0_CDRBR_THIRD_VEC_EN_ALIGN                 0
#define DSC_1_3_CDR_CTRL0_CDRBR_THIRD_VEC_EN_BITS                  1
#define DSC_1_3_CDR_CTRL0_CDRBR_THIRD_VEC_EN_SHIFT                 2

/* dsc_1_3 :: cdr_ctrl0 :: reserved_for_eco1 [01:00] */
#define DSC_1_3_CDR_CTRL0_RESERVED_FOR_ECO1_MASK                   0x0003
#define DSC_1_3_CDR_CTRL0_RESERVED_FOR_ECO1_ALIGN                  0
#define DSC_1_3_CDR_CTRL0_RESERVED_FOR_ECO1_BITS                   2
#define DSC_1_3_CDR_CTRL0_RESERVED_FOR_ECO1_SHIFT                  0


/****************************************************************************
 * dsc_1_3 :: cdr_ctrl1
 ***************************************************************************/
/* dsc_1_3 :: cdr_ctrl1 :: reserved_for_eco0 [15:10] */
#define DSC_1_3_CDR_CTRL1_RESERVED_FOR_ECO0_MASK                   0xfc00
#define DSC_1_3_CDR_CTRL1_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC_1_3_CDR_CTRL1_RESERVED_FOR_ECO0_BITS                   6
#define DSC_1_3_CDR_CTRL1_RESERVED_FOR_ECO0_SHIFT                  10

/* dsc_1_3 :: cdr_ctrl1 :: cdr_phase_err_frz [09:09] */
#define DSC_1_3_CDR_CTRL1_CDR_PHASE_ERR_FRZ_MASK                   0x0200
#define DSC_1_3_CDR_CTRL1_CDR_PHASE_ERR_FRZ_ALIGN                  0
#define DSC_1_3_CDR_CTRL1_CDR_PHASE_ERR_FRZ_BITS                   1
#define DSC_1_3_CDR_CTRL1_CDR_PHASE_ERR_FRZ_SHIFT                  9

/* dsc_1_3 :: cdr_ctrl1 :: cdr_integ_reg_clr [08:08] */
#define DSC_1_3_CDR_CTRL1_CDR_INTEG_REG_CLR_MASK                   0x0100
#define DSC_1_3_CDR_CTRL1_CDR_INTEG_REG_CLR_ALIGN                  0
#define DSC_1_3_CDR_CTRL1_CDR_INTEG_REG_CLR_BITS                   1
#define DSC_1_3_CDR_CTRL1_CDR_INTEG_REG_CLR_SHIFT                  8

/* dsc_1_3 :: cdr_ctrl1 :: cdr_freq_override_val [07:03] */
#define DSC_1_3_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_MASK               0x00f8
#define DSC_1_3_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_ALIGN              0
#define DSC_1_3_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_BITS               5
#define DSC_1_3_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_SHIFT              3

/* dsc_1_3 :: cdr_ctrl1 :: cdr_freq_override_en [02:02] */
#define DSC_1_3_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_MASK                0x0004
#define DSC_1_3_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_ALIGN               0
#define DSC_1_3_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_BITS                1
#define DSC_1_3_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_SHIFT               2

/* dsc_1_3 :: cdr_ctrl1 :: cdr_freq_upd_en [01:01] */
#define DSC_1_3_CDR_CTRL1_CDR_FREQ_UPD_EN_MASK                     0x0002
#define DSC_1_3_CDR_CTRL1_CDR_FREQ_UPD_EN_ALIGN                    0
#define DSC_1_3_CDR_CTRL1_CDR_FREQ_UPD_EN_BITS                     1
#define DSC_1_3_CDR_CTRL1_CDR_FREQ_UPD_EN_SHIFT                    1

/* dsc_1_3 :: cdr_ctrl1 :: cdr_freq_en [00:00] */
#define DSC_1_3_CDR_CTRL1_CDR_FREQ_EN_MASK                         0x0001
#define DSC_1_3_CDR_CTRL1_CDR_FREQ_EN_ALIGN                        0
#define DSC_1_3_CDR_CTRL1_CDR_FREQ_EN_BITS                         1
#define DSC_1_3_CDR_CTRL1_CDR_FREQ_EN_SHIFT                        0


/****************************************************************************
 * dsc_1_3 :: cdr_ctrl2
 ***************************************************************************/
/* dsc_1_3 :: cdr_ctrl2 :: reserved_for_eco0 [15:14] */
#define DSC_1_3_CDR_CTRL2_RESERVED_FOR_ECO0_MASK                   0xc000
#define DSC_1_3_CDR_CTRL2_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC_1_3_CDR_CTRL2_RESERVED_FOR_ECO0_BITS                   2
#define DSC_1_3_CDR_CTRL2_RESERVED_FOR_ECO0_SHIFT                  14

/* dsc_1_3 :: cdr_ctrl2 :: cdros_bwsel_prop [13:10] */
#define DSC_1_3_CDR_CTRL2_CDROS_BWSEL_PROP_MASK                    0x3c00
#define DSC_1_3_CDR_CTRL2_CDROS_BWSEL_PROP_ALIGN                   0
#define DSC_1_3_CDR_CTRL2_CDROS_BWSEL_PROP_BITS                    4
#define DSC_1_3_CDR_CTRL2_CDROS_BWSEL_PROP_SHIFT                   10

/* dsc_1_3 :: cdr_ctrl2 :: cdros_bwsel_integ [09:06] */
#define DSC_1_3_CDR_CTRL2_CDROS_BWSEL_INTEG_MASK                   0x03c0
#define DSC_1_3_CDR_CTRL2_CDROS_BWSEL_INTEG_ALIGN                  0
#define DSC_1_3_CDR_CTRL2_CDROS_BWSEL_INTEG_BITS                   4
#define DSC_1_3_CDR_CTRL2_CDROS_BWSEL_INTEG_SHIFT                  6

/* dsc_1_3 :: cdr_ctrl2 :: cdros_falling_edge [05:05] */
#define DSC_1_3_CDR_CTRL2_CDROS_FALLING_EDGE_MASK                  0x0020
#define DSC_1_3_CDR_CTRL2_CDROS_FALLING_EDGE_ALIGN                 0
#define DSC_1_3_CDR_CTRL2_CDROS_FALLING_EDGE_BITS                  1
#define DSC_1_3_CDR_CTRL2_CDROS_FALLING_EDGE_SHIFT                 5

/* dsc_1_3 :: cdr_ctrl2 :: cdros_rising_edge [04:04] */
#define DSC_1_3_CDR_CTRL2_CDROS_RISING_EDGE_MASK                   0x0010
#define DSC_1_3_CDR_CTRL2_CDROS_RISING_EDGE_ALIGN                  0
#define DSC_1_3_CDR_CTRL2_CDROS_RISING_EDGE_BITS                   1
#define DSC_1_3_CDR_CTRL2_CDROS_RISING_EDGE_SHIFT                  4

/* dsc_1_3 :: cdr_ctrl2 :: cdros_phase_sat_ctrl [03:02] */
#define DSC_1_3_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_MASK                0x000c
#define DSC_1_3_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_ALIGN               0
#define DSC_1_3_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_BITS                2
#define DSC_1_3_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_SHIFT               2

/* dsc_1_3 :: cdr_ctrl2 :: cdros_peak_polarity [01:01] */
#define DSC_1_3_CDR_CTRL2_CDROS_PEAK_POLARITY_MASK                 0x0002
#define DSC_1_3_CDR_CTRL2_CDROS_PEAK_POLARITY_ALIGN                0
#define DSC_1_3_CDR_CTRL2_CDROS_PEAK_POLARITY_BITS                 1
#define DSC_1_3_CDR_CTRL2_CDROS_PEAK_POLARITY_SHIFT                1

/* dsc_1_3 :: cdr_ctrl2 :: cdros_zero_polarity [00:00] */
#define DSC_1_3_CDR_CTRL2_CDROS_ZERO_POLARITY_MASK                 0x0001
#define DSC_1_3_CDR_CTRL2_CDROS_ZERO_POLARITY_ALIGN                0
#define DSC_1_3_CDR_CTRL2_CDROS_ZERO_POLARITY_BITS                 1
#define DSC_1_3_CDR_CTRL2_CDROS_ZERO_POLARITY_SHIFT                0


/****************************************************************************
 * dsc_1_3 :: cdr_status0
 ***************************************************************************/
/* dsc_1_3 :: cdr_status0 :: integ_reg [15:00] */
#define DSC_1_3_CDR_STATUS0_INTEG_REG_MASK                         0xffff
#define DSC_1_3_CDR_STATUS0_INTEG_REG_ALIGN                        0
#define DSC_1_3_CDR_STATUS0_INTEG_REG_BITS                         16
#define DSC_1_3_CDR_STATUS0_INTEG_REG_SHIFT                        0


/****************************************************************************
 * dsc_1_3 :: cdr_status1
 ***************************************************************************/
/* dsc_1_3 :: cdr_status1 :: reserved_for_eco0 [15:06] */
#define DSC_1_3_CDR_STATUS1_RESERVED_FOR_ECO0_MASK                 0xffc0
#define DSC_1_3_CDR_STATUS1_RESERVED_FOR_ECO0_ALIGN                0
#define DSC_1_3_CDR_STATUS1_RESERVED_FOR_ECO0_BITS                 10
#define DSC_1_3_CDR_STATUS1_RESERVED_FOR_ECO0_SHIFT                6

/* dsc_1_3 :: cdr_status1 :: phase_err [05:00] */
#define DSC_1_3_CDR_STATUS1_PHASE_ERR_MASK                         0x003f
#define DSC_1_3_CDR_STATUS1_PHASE_ERR_ALIGN                        0
#define DSC_1_3_CDR_STATUS1_PHASE_ERR_BITS                         6
#define DSC_1_3_CDR_STATUS1_PHASE_ERR_SHIFT                        0


/****************************************************************************
 * dsc_1_3 :: pi_ctrl0
 ***************************************************************************/
/* dsc_1_3 :: pi_ctrl0 :: reserved_for_eco0 [15:11] */
#define DSC_1_3_PI_CTRL0_RESERVED_FOR_ECO0_MASK                    0xf800
#define DSC_1_3_PI_CTRL0_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC_1_3_PI_CTRL0_RESERVED_FOR_ECO0_BITS                    5
#define DSC_1_3_PI_CTRL0_RESERVED_FOR_ECO0_SHIFT                   11

/* dsc_1_3 :: pi_ctrl0 :: pi_phase_invert [10:10] */
#define DSC_1_3_PI_CTRL0_PI_PHASE_INVERT_MASK                      0x0400
#define DSC_1_3_PI_CTRL0_PI_PHASE_INVERT_ALIGN                     0
#define DSC_1_3_PI_CTRL0_PI_PHASE_INVERT_BITS                      1
#define DSC_1_3_PI_CTRL0_PI_PHASE_INVERT_SHIFT                     10

/* dsc_1_3 :: pi_ctrl0 :: pi_dual_phase_override [09:09] */
#define DSC_1_3_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_MASK               0x0200
#define DSC_1_3_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_ALIGN              0
#define DSC_1_3_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_BITS               1
#define DSC_1_3_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_SHIFT              9

/* dsc_1_3 :: pi_ctrl0 :: pi_clk90_offset_override [08:08] */
#define DSC_1_3_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_MASK             0x0100
#define DSC_1_3_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_ALIGN            0
#define DSC_1_3_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_BITS             1
#define DSC_1_3_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_SHIFT            8

/* dsc_1_3 :: pi_ctrl0 :: pi_phase_dec [07:07] */
#define DSC_1_3_PI_CTRL0_PI_PHASE_DEC_MASK                         0x0080
#define DSC_1_3_PI_CTRL0_PI_PHASE_DEC_ALIGN                        0
#define DSC_1_3_PI_CTRL0_PI_PHASE_DEC_BITS                         1
#define DSC_1_3_PI_CTRL0_PI_PHASE_DEC_SHIFT                        7

/* dsc_1_3 :: pi_ctrl0 :: pi_phase_inc [06:06] */
#define DSC_1_3_PI_CTRL0_PI_PHASE_INC_MASK                         0x0040
#define DSC_1_3_PI_CTRL0_PI_PHASE_INC_ALIGN                        0
#define DSC_1_3_PI_CTRL0_PI_PHASE_INC_BITS                         1
#define DSC_1_3_PI_CTRL0_PI_PHASE_INC_SHIFT                        6

/* dsc_1_3 :: pi_ctrl0 :: pi_phase_strobe [05:05] */
#define DSC_1_3_PI_CTRL0_PI_PHASE_STROBE_MASK                      0x0020
#define DSC_1_3_PI_CTRL0_PI_PHASE_STROBE_ALIGN                     0
#define DSC_1_3_PI_CTRL0_PI_PHASE_STROBE_BITS                      1
#define DSC_1_3_PI_CTRL0_PI_PHASE_STROBE_SHIFT                     5

/* dsc_1_3 :: pi_ctrl0 :: pi_phase_delta [04:01] */
#define DSC_1_3_PI_CTRL0_PI_PHASE_DELTA_MASK                       0x001e
#define DSC_1_3_PI_CTRL0_PI_PHASE_DELTA_ALIGN                      0
#define DSC_1_3_PI_CTRL0_PI_PHASE_DELTA_BITS                       4
#define DSC_1_3_PI_CTRL0_PI_PHASE_DELTA_SHIFT                      1

/* dsc_1_3 :: pi_ctrl0 :: pi_phase_step_mult [00:00] */
#define DSC_1_3_PI_CTRL0_PI_PHASE_STEP_MULT_MASK                   0x0001
#define DSC_1_3_PI_CTRL0_PI_PHASE_STEP_MULT_ALIGN                  0
#define DSC_1_3_PI_CTRL0_PI_PHASE_STEP_MULT_BITS                   1
#define DSC_1_3_PI_CTRL0_PI_PHASE_STEP_MULT_SHIFT                  0


/****************************************************************************
 * dsc_1_3 :: pi_status0
 ***************************************************************************/
/* dsc_1_3 :: pi_status0 :: reserved_for_eco0 [15:14] */
#define DSC_1_3_PI_STATUS0_RESERVED_FOR_ECO0_MASK                  0xc000
#define DSC_1_3_PI_STATUS0_RESERVED_FOR_ECO0_ALIGN                 0
#define DSC_1_3_PI_STATUS0_RESERVED_FOR_ECO0_BITS                  2
#define DSC_1_3_PI_STATUS0_RESERVED_FOR_ECO0_SHIFT                 14

/* dsc_1_3 :: pi_status0 :: clk90_phase_offset [13:07] */
#define DSC_1_3_PI_STATUS0_CLK90_PHASE_OFFSET_MASK                 0x3f80
#define DSC_1_3_PI_STATUS0_CLK90_PHASE_OFFSET_ALIGN                0
#define DSC_1_3_PI_STATUS0_CLK90_PHASE_OFFSET_BITS                 7
#define DSC_1_3_PI_STATUS0_CLK90_PHASE_OFFSET_SHIFT                7

/* dsc_1_3 :: pi_status0 :: phase_cntr [06:00] */
#define DSC_1_3_PI_STATUS0_PHASE_CNTR_MASK                         0x007f
#define DSC_1_3_PI_STATUS0_PHASE_CNTR_ALIGN                        0
#define DSC_1_3_PI_STATUS0_PHASE_CNTR_BITS                         7
#define DSC_1_3_PI_STATUS0_PHASE_CNTR_SHIFT                        0


/****************************************************************************
 * dsc_1_3 :: dfe_vga_ctrl0
 ***************************************************************************/
/* dsc_1_3 :: dfe_vga_ctrl0 :: reserved_for_eco0 [15:12] */
#define DSC_1_3_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_MASK               0xf000
#define DSC_1_3_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_ALIGN              0
#define DSC_1_3_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_BITS               4
#define DSC_1_3_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_SHIFT              12

/* dsc_1_3 :: dfe_vga_ctrl0 :: trnsum_tap0_only [11:11] */
#define DSC_1_3_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_MASK                0x0800
#define DSC_1_3_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_ALIGN               0
#define DSC_1_3_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_BITS                1
#define DSC_1_3_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_SHIFT               11

/* dsc_1_3 :: dfe_vga_ctrl0 :: sum_m1err [10:10] */
#define DSC_1_3_DFE_VGA_CTRL0_SUM_M1ERR_MASK                       0x0400
#define DSC_1_3_DFE_VGA_CTRL0_SUM_M1ERR_ALIGN                      0
#define DSC_1_3_DFE_VGA_CTRL0_SUM_M1ERR_BITS                       1
#define DSC_1_3_DFE_VGA_CTRL0_SUM_M1ERR_SHIFT                      10

/* dsc_1_3 :: dfe_vga_ctrl0 :: dfe_vga_clken [09:09] */
#define DSC_1_3_DFE_VGA_CTRL0_DFE_VGA_CLKEN_MASK                   0x0200
#define DSC_1_3_DFE_VGA_CTRL0_DFE_VGA_CLKEN_ALIGN                  0
#define DSC_1_3_DFE_VGA_CTRL0_DFE_VGA_CLKEN_BITS                   1
#define DSC_1_3_DFE_VGA_CTRL0_DFE_VGA_CLKEN_SHIFT                  9

/* dsc_1_3 :: dfe_vga_ctrl0 :: hysteresis_en [08:08] */
#define DSC_1_3_DFE_VGA_CTRL0_HYSTERESIS_EN_MASK                   0x0100
#define DSC_1_3_DFE_VGA_CTRL0_HYSTERESIS_EN_ALIGN                  0
#define DSC_1_3_DFE_VGA_CTRL0_HYSTERESIS_EN_BITS                   1
#define DSC_1_3_DFE_VGA_CTRL0_HYSTERESIS_EN_SHIFT                  8

/* dsc_1_3 :: dfe_vga_ctrl0 :: dfe_vga_write_val [07:02] */
#define DSC_1_3_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_MASK               0x00fc
#define DSC_1_3_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_ALIGN              0
#define DSC_1_3_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_BITS               6
#define DSC_1_3_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_SHIFT              2

/* dsc_1_3 :: dfe_vga_ctrl0 :: vga_write_en [01:01] */
#define DSC_1_3_DFE_VGA_CTRL0_VGA_WRITE_EN_MASK                    0x0002
#define DSC_1_3_DFE_VGA_CTRL0_VGA_WRITE_EN_ALIGN                   0
#define DSC_1_3_DFE_VGA_CTRL0_VGA_WRITE_EN_BITS                    1
#define DSC_1_3_DFE_VGA_CTRL0_VGA_WRITE_EN_SHIFT                   1

/* dsc_1_3 :: dfe_vga_ctrl0 :: dfe_write_en [00:00] */
#define DSC_1_3_DFE_VGA_CTRL0_DFE_WRITE_EN_MASK                    0x0001
#define DSC_1_3_DFE_VGA_CTRL0_DFE_WRITE_EN_ALIGN                   0
#define DSC_1_3_DFE_VGA_CTRL0_DFE_WRITE_EN_BITS                    1
#define DSC_1_3_DFE_VGA_CTRL0_DFE_WRITE_EN_SHIFT                   0


/****************************************************************************
 * dsc_1_3 :: dfe_vga_ctrl1
 ***************************************************************************/
/* dsc_1_3 :: dfe_vga_ctrl1 :: reserved_for_eco0 [15:15] */
#define DSC_1_3_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_MASK               0x8000
#define DSC_1_3_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_ALIGN              0
#define DSC_1_3_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_BITS               1
#define DSC_1_3_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_SHIFT              15

/* dsc_1_3 :: dfe_vga_ctrl1 :: trnsum_otap_en [14:08] */
#define DSC_1_3_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_MASK                  0x7f00
#define DSC_1_3_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_ALIGN                 0
#define DSC_1_3_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_BITS                  7
#define DSC_1_3_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_SHIFT                 8

/* dsc_1_3 :: dfe_vga_ctrl1 :: trnsum_etap_en [07:01] */
#define DSC_1_3_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_MASK                  0x00fe
#define DSC_1_3_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_ALIGN                 0
#define DSC_1_3_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_BITS                  7
#define DSC_1_3_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_SHIFT                 1

/* dsc_1_3 :: dfe_vga_ctrl1 :: trnsum_en [00:00] */
#define DSC_1_3_DFE_VGA_CTRL1_TRNSUM_EN_MASK                       0x0001
#define DSC_1_3_DFE_VGA_CTRL1_TRNSUM_EN_ALIGN                      0
#define DSC_1_3_DFE_VGA_CTRL1_TRNSUM_EN_BITS                       1
#define DSC_1_3_DFE_VGA_CTRL1_TRNSUM_EN_SHIFT                      0


/****************************************************************************
 * dsc_1_3 :: dfe_vga_ctrl2
 ***************************************************************************/
/* dsc_1_3 :: dfe_vga_ctrl2 :: vga_polarity [15:15] */
#define DSC_1_3_DFE_VGA_CTRL2_VGA_POLARITY_MASK                    0x8000
#define DSC_1_3_DFE_VGA_CTRL2_VGA_POLARITY_ALIGN                   0
#define DSC_1_3_DFE_VGA_CTRL2_VGA_POLARITY_BITS                    1
#define DSC_1_3_DFE_VGA_CTRL2_VGA_POLARITY_SHIFT                   15

/* dsc_1_3 :: dfe_vga_ctrl2 :: dfe_polarity [14:14] */
#define DSC_1_3_DFE_VGA_CTRL2_DFE_POLARITY_MASK                    0x4000
#define DSC_1_3_DFE_VGA_CTRL2_DFE_POLARITY_ALIGN                   0
#define DSC_1_3_DFE_VGA_CTRL2_DFE_POLARITY_BITS                    1
#define DSC_1_3_DFE_VGA_CTRL2_DFE_POLARITY_SHIFT                   14

/* dsc_1_3 :: dfe_vga_ctrl2 :: trnsum_otap_sign [13:07] */
#define DSC_1_3_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_MASK                0x3f80
#define DSC_1_3_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_ALIGN               0
#define DSC_1_3_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_BITS                7
#define DSC_1_3_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_SHIFT               7

/* dsc_1_3 :: dfe_vga_ctrl2 :: trnsum_etap_sign [06:00] */
#define DSC_1_3_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_MASK                0x007f
#define DSC_1_3_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_ALIGN               0
#define DSC_1_3_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_BITS                7
#define DSC_1_3_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_SHIFT               0


/****************************************************************************
 * dsc_1_3 :: dfe_vga_ctrl3
 ***************************************************************************/
/* dsc_1_3 :: dfe_vga_ctrl3 :: reserved_for_eco0 [15:10] */
#define DSC_1_3_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_MASK               0xfc00
#define DSC_1_3_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_ALIGN              0
#define DSC_1_3_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_BITS               6
#define DSC_1_3_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_SHIFT              10

/* dsc_1_3 :: dfe_vga_ctrl3 :: vga_cor_sel_e [09:05] */
#define DSC_1_3_DFE_VGA_CTRL3_VGA_COR_SEL_E_MASK                   0x03e0
#define DSC_1_3_DFE_VGA_CTRL3_VGA_COR_SEL_E_ALIGN                  0
#define DSC_1_3_DFE_VGA_CTRL3_VGA_COR_SEL_E_BITS                   5
#define DSC_1_3_DFE_VGA_CTRL3_VGA_COR_SEL_E_SHIFT                  5

/* dsc_1_3 :: dfe_vga_ctrl3 :: vga_cor_sel_o [04:00] */
#define DSC_1_3_DFE_VGA_CTRL3_VGA_COR_SEL_O_MASK                   0x001f
#define DSC_1_3_DFE_VGA_CTRL3_VGA_COR_SEL_O_ALIGN                  0
#define DSC_1_3_DFE_VGA_CTRL3_VGA_COR_SEL_O_BITS                   5
#define DSC_1_3_DFE_VGA_CTRL3_VGA_COR_SEL_O_SHIFT                  0


/****************************************************************************
 * dsc_1_3 :: dfe_vga_ctrl4
 ***************************************************************************/
/* dsc_1_3 :: dfe_vga_ctrl4 :: reserved_for_eco0 [15:10] */
#define DSC_1_3_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_MASK               0xfc00
#define DSC_1_3_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_ALIGN              0
#define DSC_1_3_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_BITS               6
#define DSC_1_3_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_SHIFT              10

/* dsc_1_3 :: dfe_vga_ctrl4 :: dfe_cor_sel_e [09:05] */
#define DSC_1_3_DFE_VGA_CTRL4_DFE_COR_SEL_E_MASK                   0x03e0
#define DSC_1_3_DFE_VGA_CTRL4_DFE_COR_SEL_E_ALIGN                  0
#define DSC_1_3_DFE_VGA_CTRL4_DFE_COR_SEL_E_BITS                   5
#define DSC_1_3_DFE_VGA_CTRL4_DFE_COR_SEL_E_SHIFT                  5

/* dsc_1_3 :: dfe_vga_ctrl4 :: dfe_cor_sel_o [04:00] */
#define DSC_1_3_DFE_VGA_CTRL4_DFE_COR_SEL_O_MASK                   0x001f
#define DSC_1_3_DFE_VGA_CTRL4_DFE_COR_SEL_O_ALIGN                  0
#define DSC_1_3_DFE_VGA_CTRL4_DFE_COR_SEL_O_BITS                   5
#define DSC_1_3_DFE_VGA_CTRL4_DFE_COR_SEL_O_SHIFT                  0


/****************************************************************************
 * dsc_1_3 :: dfe_vga_status0
 ***************************************************************************/
/* dsc_1_3 :: dfe_vga_status0 :: vga_sum [15:11] */
#define DSC_1_3_DFE_VGA_STATUS0_VGA_SUM_MASK                       0xf800
#define DSC_1_3_DFE_VGA_STATUS0_VGA_SUM_ALIGN                      0
#define DSC_1_3_DFE_VGA_STATUS0_VGA_SUM_BITS                       5
#define DSC_1_3_DFE_VGA_STATUS0_VGA_SUM_SHIFT                      11

/* dsc_1_3 :: dfe_vga_status0 :: trnsum [10:00] */
#define DSC_1_3_DFE_VGA_STATUS0_TRNSUM_MASK                        0x07ff
#define DSC_1_3_DFE_VGA_STATUS0_TRNSUM_ALIGN                       0
#define DSC_1_3_DFE_VGA_STATUS0_TRNSUM_BITS                        11
#define DSC_1_3_DFE_VGA_STATUS0_TRNSUM_SHIFT                       0


/****************************************************************************
 * dsc_1_3 :: dfe_vga_status1
 ***************************************************************************/
/* dsc_1_3 :: dfe_vga_status1 :: odd_dfe_acc [15:06] */
#define DSC_1_3_DFE_VGA_STATUS1_ODD_DFE_ACC_MASK                   0xffc0
#define DSC_1_3_DFE_VGA_STATUS1_ODD_DFE_ACC_ALIGN                  0
#define DSC_1_3_DFE_VGA_STATUS1_ODD_DFE_ACC_BITS                   10
#define DSC_1_3_DFE_VGA_STATUS1_ODD_DFE_ACC_SHIFT                  6

/* dsc_1_3 :: dfe_vga_status1 :: dfe_tap_bin [05:00] */
#define DSC_1_3_DFE_VGA_STATUS1_DFE_TAP_BIN_MASK                   0x003f
#define DSC_1_3_DFE_VGA_STATUS1_DFE_TAP_BIN_ALIGN                  0
#define DSC_1_3_DFE_VGA_STATUS1_DFE_TAP_BIN_BITS                   6
#define DSC_1_3_DFE_VGA_STATUS1_DFE_TAP_BIN_SHIFT                  0


/****************************************************************************
 * dsc_1_3 :: dfe_vga_status2
 ***************************************************************************/
/* dsc_1_3 :: dfe_vga_status2 :: reserved_for_eco0 [15:10] */
#define DSC_1_3_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_MASK             0xfc00
#define DSC_1_3_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_ALIGN            0
#define DSC_1_3_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_BITS             6
#define DSC_1_3_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_SHIFT            10

/* dsc_1_3 :: dfe_vga_status2 :: evn_dfe_acc [09:00] */
#define DSC_1_3_DFE_VGA_STATUS2_EVN_DFE_ACC_MASK                   0x03ff
#define DSC_1_3_DFE_VGA_STATUS2_EVN_DFE_ACC_ALIGN                  0
#define DSC_1_3_DFE_VGA_STATUS2_EVN_DFE_ACC_BITS                   10
#define DSC_1_3_DFE_VGA_STATUS2_EVN_DFE_ACC_SHIFT                  0


/****************************************************************************
 * XGXS16G_USER_dsc_1_A
 ***************************************************************************/
/****************************************************************************
 * dsc_1_A :: cdr_ctrl0
 ***************************************************************************/
/* dsc_1_A :: cdr_ctrl0 :: reserved_for_eco0 [15:09] */
#define DSC_1_A_CDR_CTRL0_RESERVED_FOR_ECO0_MASK                   0xfe00
#define DSC_1_A_CDR_CTRL0_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC_1_A_CDR_CTRL0_RESERVED_FOR_ECO0_BITS                   7
#define DSC_1_A_CDR_CTRL0_RESERVED_FOR_ECO0_SHIFT                  9

/* dsc_1_A :: cdr_ctrl0 :: cdrbr_bwsel_integ [08:07] */
#define DSC_1_A_CDR_CTRL0_CDRBR_BWSEL_INTEG_MASK                   0x0180
#define DSC_1_A_CDR_CTRL0_CDRBR_BWSEL_INTEG_ALIGN                  0
#define DSC_1_A_CDR_CTRL0_CDRBR_BWSEL_INTEG_BITS                   2
#define DSC_1_A_CDR_CTRL0_CDRBR_BWSEL_INTEG_SHIFT                  7

/* dsc_1_A :: cdr_ctrl0 :: cdrbr_bwsel_prop [06:04] */
#define DSC_1_A_CDR_CTRL0_CDRBR_BWSEL_PROP_MASK                    0x0070
#define DSC_1_A_CDR_CTRL0_CDRBR_BWSEL_PROP_ALIGN                   0
#define DSC_1_A_CDR_CTRL0_CDRBR_BWSEL_PROP_BITS                    3
#define DSC_1_A_CDR_CTRL0_CDRBR_BWSEL_PROP_SHIFT                   4

/* dsc_1_A :: cdr_ctrl0 :: cdrbr_polarity [03:03] */
#define DSC_1_A_CDR_CTRL0_CDRBR_POLARITY_MASK                      0x0008
#define DSC_1_A_CDR_CTRL0_CDRBR_POLARITY_ALIGN                     0
#define DSC_1_A_CDR_CTRL0_CDRBR_POLARITY_BITS                      1
#define DSC_1_A_CDR_CTRL0_CDRBR_POLARITY_SHIFT                     3

/* dsc_1_A :: cdr_ctrl0 :: cdrbr_third_vec_en [02:02] */
#define DSC_1_A_CDR_CTRL0_CDRBR_THIRD_VEC_EN_MASK                  0x0004
#define DSC_1_A_CDR_CTRL0_CDRBR_THIRD_VEC_EN_ALIGN                 0
#define DSC_1_A_CDR_CTRL0_CDRBR_THIRD_VEC_EN_BITS                  1
#define DSC_1_A_CDR_CTRL0_CDRBR_THIRD_VEC_EN_SHIFT                 2

/* dsc_1_A :: cdr_ctrl0 :: reserved_for_eco1 [01:00] */
#define DSC_1_A_CDR_CTRL0_RESERVED_FOR_ECO1_MASK                   0x0003
#define DSC_1_A_CDR_CTRL0_RESERVED_FOR_ECO1_ALIGN                  0
#define DSC_1_A_CDR_CTRL0_RESERVED_FOR_ECO1_BITS                   2
#define DSC_1_A_CDR_CTRL0_RESERVED_FOR_ECO1_SHIFT                  0


/****************************************************************************
 * dsc_1_A :: cdr_ctrl1
 ***************************************************************************/
/* dsc_1_A :: cdr_ctrl1 :: reserved_for_eco0 [15:10] */
#define DSC_1_A_CDR_CTRL1_RESERVED_FOR_ECO0_MASK                   0xfc00
#define DSC_1_A_CDR_CTRL1_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC_1_A_CDR_CTRL1_RESERVED_FOR_ECO0_BITS                   6
#define DSC_1_A_CDR_CTRL1_RESERVED_FOR_ECO0_SHIFT                  10

/* dsc_1_A :: cdr_ctrl1 :: cdr_phase_err_frz [09:09] */
#define DSC_1_A_CDR_CTRL1_CDR_PHASE_ERR_FRZ_MASK                   0x0200
#define DSC_1_A_CDR_CTRL1_CDR_PHASE_ERR_FRZ_ALIGN                  0
#define DSC_1_A_CDR_CTRL1_CDR_PHASE_ERR_FRZ_BITS                   1
#define DSC_1_A_CDR_CTRL1_CDR_PHASE_ERR_FRZ_SHIFT                  9

/* dsc_1_A :: cdr_ctrl1 :: cdr_integ_reg_clr [08:08] */
#define DSC_1_A_CDR_CTRL1_CDR_INTEG_REG_CLR_MASK                   0x0100
#define DSC_1_A_CDR_CTRL1_CDR_INTEG_REG_CLR_ALIGN                  0
#define DSC_1_A_CDR_CTRL1_CDR_INTEG_REG_CLR_BITS                   1
#define DSC_1_A_CDR_CTRL1_CDR_INTEG_REG_CLR_SHIFT                  8

/* dsc_1_A :: cdr_ctrl1 :: cdr_freq_override_val [07:03] */
#define DSC_1_A_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_MASK               0x00f8
#define DSC_1_A_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_ALIGN              0
#define DSC_1_A_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_BITS               5
#define DSC_1_A_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_SHIFT              3

/* dsc_1_A :: cdr_ctrl1 :: cdr_freq_override_en [02:02] */
#define DSC_1_A_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_MASK                0x0004
#define DSC_1_A_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_ALIGN               0
#define DSC_1_A_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_BITS                1
#define DSC_1_A_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_SHIFT               2

/* dsc_1_A :: cdr_ctrl1 :: cdr_freq_upd_en [01:01] */
#define DSC_1_A_CDR_CTRL1_CDR_FREQ_UPD_EN_MASK                     0x0002
#define DSC_1_A_CDR_CTRL1_CDR_FREQ_UPD_EN_ALIGN                    0
#define DSC_1_A_CDR_CTRL1_CDR_FREQ_UPD_EN_BITS                     1
#define DSC_1_A_CDR_CTRL1_CDR_FREQ_UPD_EN_SHIFT                    1

/* dsc_1_A :: cdr_ctrl1 :: cdr_freq_en [00:00] */
#define DSC_1_A_CDR_CTRL1_CDR_FREQ_EN_MASK                         0x0001
#define DSC_1_A_CDR_CTRL1_CDR_FREQ_EN_ALIGN                        0
#define DSC_1_A_CDR_CTRL1_CDR_FREQ_EN_BITS                         1
#define DSC_1_A_CDR_CTRL1_CDR_FREQ_EN_SHIFT                        0


/****************************************************************************
 * dsc_1_A :: cdr_ctrl2
 ***************************************************************************/
/* dsc_1_A :: cdr_ctrl2 :: reserved_for_eco0 [15:14] */
#define DSC_1_A_CDR_CTRL2_RESERVED_FOR_ECO0_MASK                   0xc000
#define DSC_1_A_CDR_CTRL2_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC_1_A_CDR_CTRL2_RESERVED_FOR_ECO0_BITS                   2
#define DSC_1_A_CDR_CTRL2_RESERVED_FOR_ECO0_SHIFT                  14

/* dsc_1_A :: cdr_ctrl2 :: cdros_bwsel_prop [13:10] */
#define DSC_1_A_CDR_CTRL2_CDROS_BWSEL_PROP_MASK                    0x3c00
#define DSC_1_A_CDR_CTRL2_CDROS_BWSEL_PROP_ALIGN                   0
#define DSC_1_A_CDR_CTRL2_CDROS_BWSEL_PROP_BITS                    4
#define DSC_1_A_CDR_CTRL2_CDROS_BWSEL_PROP_SHIFT                   10

/* dsc_1_A :: cdr_ctrl2 :: cdros_bwsel_integ [09:06] */
#define DSC_1_A_CDR_CTRL2_CDROS_BWSEL_INTEG_MASK                   0x03c0
#define DSC_1_A_CDR_CTRL2_CDROS_BWSEL_INTEG_ALIGN                  0
#define DSC_1_A_CDR_CTRL2_CDROS_BWSEL_INTEG_BITS                   4
#define DSC_1_A_CDR_CTRL2_CDROS_BWSEL_INTEG_SHIFT                  6

/* dsc_1_A :: cdr_ctrl2 :: cdros_falling_edge [05:05] */
#define DSC_1_A_CDR_CTRL2_CDROS_FALLING_EDGE_MASK                  0x0020
#define DSC_1_A_CDR_CTRL2_CDROS_FALLING_EDGE_ALIGN                 0
#define DSC_1_A_CDR_CTRL2_CDROS_FALLING_EDGE_BITS                  1
#define DSC_1_A_CDR_CTRL2_CDROS_FALLING_EDGE_SHIFT                 5

/* dsc_1_A :: cdr_ctrl2 :: cdros_rising_edge [04:04] */
#define DSC_1_A_CDR_CTRL2_CDROS_RISING_EDGE_MASK                   0x0010
#define DSC_1_A_CDR_CTRL2_CDROS_RISING_EDGE_ALIGN                  0
#define DSC_1_A_CDR_CTRL2_CDROS_RISING_EDGE_BITS                   1
#define DSC_1_A_CDR_CTRL2_CDROS_RISING_EDGE_SHIFT                  4

/* dsc_1_A :: cdr_ctrl2 :: cdros_phase_sat_ctrl [03:02] */
#define DSC_1_A_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_MASK                0x000c
#define DSC_1_A_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_ALIGN               0
#define DSC_1_A_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_BITS                2
#define DSC_1_A_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_SHIFT               2

/* dsc_1_A :: cdr_ctrl2 :: cdros_peak_polarity [01:01] */
#define DSC_1_A_CDR_CTRL2_CDROS_PEAK_POLARITY_MASK                 0x0002
#define DSC_1_A_CDR_CTRL2_CDROS_PEAK_POLARITY_ALIGN                0
#define DSC_1_A_CDR_CTRL2_CDROS_PEAK_POLARITY_BITS                 1
#define DSC_1_A_CDR_CTRL2_CDROS_PEAK_POLARITY_SHIFT                1

/* dsc_1_A :: cdr_ctrl2 :: cdros_zero_polarity [00:00] */
#define DSC_1_A_CDR_CTRL2_CDROS_ZERO_POLARITY_MASK                 0x0001
#define DSC_1_A_CDR_CTRL2_CDROS_ZERO_POLARITY_ALIGN                0
#define DSC_1_A_CDR_CTRL2_CDROS_ZERO_POLARITY_BITS                 1
#define DSC_1_A_CDR_CTRL2_CDROS_ZERO_POLARITY_SHIFT                0


/****************************************************************************
 * dsc_1_A :: cdr_status0
 ***************************************************************************/
/* dsc_1_A :: cdr_status0 :: integ_reg [15:00] */
#define DSC_1_A_CDR_STATUS0_INTEG_REG_MASK                         0xffff
#define DSC_1_A_CDR_STATUS0_INTEG_REG_ALIGN                        0
#define DSC_1_A_CDR_STATUS0_INTEG_REG_BITS                         16
#define DSC_1_A_CDR_STATUS0_INTEG_REG_SHIFT                        0


/****************************************************************************
 * dsc_1_A :: cdr_status1
 ***************************************************************************/
/* dsc_1_A :: cdr_status1 :: reserved_for_eco0 [15:06] */
#define DSC_1_A_CDR_STATUS1_RESERVED_FOR_ECO0_MASK                 0xffc0
#define DSC_1_A_CDR_STATUS1_RESERVED_FOR_ECO0_ALIGN                0
#define DSC_1_A_CDR_STATUS1_RESERVED_FOR_ECO0_BITS                 10
#define DSC_1_A_CDR_STATUS1_RESERVED_FOR_ECO0_SHIFT                6

/* dsc_1_A :: cdr_status1 :: phase_err [05:00] */
#define DSC_1_A_CDR_STATUS1_PHASE_ERR_MASK                         0x003f
#define DSC_1_A_CDR_STATUS1_PHASE_ERR_ALIGN                        0
#define DSC_1_A_CDR_STATUS1_PHASE_ERR_BITS                         6
#define DSC_1_A_CDR_STATUS1_PHASE_ERR_SHIFT                        0


/****************************************************************************
 * dsc_1_A :: pi_ctrl0
 ***************************************************************************/
/* dsc_1_A :: pi_ctrl0 :: reserved_for_eco0 [15:11] */
#define DSC_1_A_PI_CTRL0_RESERVED_FOR_ECO0_MASK                    0xf800
#define DSC_1_A_PI_CTRL0_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC_1_A_PI_CTRL0_RESERVED_FOR_ECO0_BITS                    5
#define DSC_1_A_PI_CTRL0_RESERVED_FOR_ECO0_SHIFT                   11

/* dsc_1_A :: pi_ctrl0 :: pi_phase_invert [10:10] */
#define DSC_1_A_PI_CTRL0_PI_PHASE_INVERT_MASK                      0x0400
#define DSC_1_A_PI_CTRL0_PI_PHASE_INVERT_ALIGN                     0
#define DSC_1_A_PI_CTRL0_PI_PHASE_INVERT_BITS                      1
#define DSC_1_A_PI_CTRL0_PI_PHASE_INVERT_SHIFT                     10

/* dsc_1_A :: pi_ctrl0 :: pi_dual_phase_override [09:09] */
#define DSC_1_A_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_MASK               0x0200
#define DSC_1_A_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_ALIGN              0
#define DSC_1_A_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_BITS               1
#define DSC_1_A_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_SHIFT              9

/* dsc_1_A :: pi_ctrl0 :: pi_clk90_offset_override [08:08] */
#define DSC_1_A_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_MASK             0x0100
#define DSC_1_A_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_ALIGN            0
#define DSC_1_A_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_BITS             1
#define DSC_1_A_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_SHIFT            8

/* dsc_1_A :: pi_ctrl0 :: pi_phase_dec [07:07] */
#define DSC_1_A_PI_CTRL0_PI_PHASE_DEC_MASK                         0x0080
#define DSC_1_A_PI_CTRL0_PI_PHASE_DEC_ALIGN                        0
#define DSC_1_A_PI_CTRL0_PI_PHASE_DEC_BITS                         1
#define DSC_1_A_PI_CTRL0_PI_PHASE_DEC_SHIFT                        7

/* dsc_1_A :: pi_ctrl0 :: pi_phase_inc [06:06] */
#define DSC_1_A_PI_CTRL0_PI_PHASE_INC_MASK                         0x0040
#define DSC_1_A_PI_CTRL0_PI_PHASE_INC_ALIGN                        0
#define DSC_1_A_PI_CTRL0_PI_PHASE_INC_BITS                         1
#define DSC_1_A_PI_CTRL0_PI_PHASE_INC_SHIFT                        6

/* dsc_1_A :: pi_ctrl0 :: pi_phase_strobe [05:05] */
#define DSC_1_A_PI_CTRL0_PI_PHASE_STROBE_MASK                      0x0020
#define DSC_1_A_PI_CTRL0_PI_PHASE_STROBE_ALIGN                     0
#define DSC_1_A_PI_CTRL0_PI_PHASE_STROBE_BITS                      1
#define DSC_1_A_PI_CTRL0_PI_PHASE_STROBE_SHIFT                     5

/* dsc_1_A :: pi_ctrl0 :: pi_phase_delta [04:01] */
#define DSC_1_A_PI_CTRL0_PI_PHASE_DELTA_MASK                       0x001e
#define DSC_1_A_PI_CTRL0_PI_PHASE_DELTA_ALIGN                      0
#define DSC_1_A_PI_CTRL0_PI_PHASE_DELTA_BITS                       4
#define DSC_1_A_PI_CTRL0_PI_PHASE_DELTA_SHIFT                      1

/* dsc_1_A :: pi_ctrl0 :: pi_phase_step_mult [00:00] */
#define DSC_1_A_PI_CTRL0_PI_PHASE_STEP_MULT_MASK                   0x0001
#define DSC_1_A_PI_CTRL0_PI_PHASE_STEP_MULT_ALIGN                  0
#define DSC_1_A_PI_CTRL0_PI_PHASE_STEP_MULT_BITS                   1
#define DSC_1_A_PI_CTRL0_PI_PHASE_STEP_MULT_SHIFT                  0


/****************************************************************************
 * dsc_1_A :: pi_status0
 ***************************************************************************/
/* dsc_1_A :: pi_status0 :: reserved_for_eco0 [15:14] */
#define DSC_1_A_PI_STATUS0_RESERVED_FOR_ECO0_MASK                  0xc000
#define DSC_1_A_PI_STATUS0_RESERVED_FOR_ECO0_ALIGN                 0
#define DSC_1_A_PI_STATUS0_RESERVED_FOR_ECO0_BITS                  2
#define DSC_1_A_PI_STATUS0_RESERVED_FOR_ECO0_SHIFT                 14

/* dsc_1_A :: pi_status0 :: clk90_phase_offset [13:07] */
#define DSC_1_A_PI_STATUS0_CLK90_PHASE_OFFSET_MASK                 0x3f80
#define DSC_1_A_PI_STATUS0_CLK90_PHASE_OFFSET_ALIGN                0
#define DSC_1_A_PI_STATUS0_CLK90_PHASE_OFFSET_BITS                 7
#define DSC_1_A_PI_STATUS0_CLK90_PHASE_OFFSET_SHIFT                7

/* dsc_1_A :: pi_status0 :: phase_cntr [06:00] */
#define DSC_1_A_PI_STATUS0_PHASE_CNTR_MASK                         0x007f
#define DSC_1_A_PI_STATUS0_PHASE_CNTR_ALIGN                        0
#define DSC_1_A_PI_STATUS0_PHASE_CNTR_BITS                         7
#define DSC_1_A_PI_STATUS0_PHASE_CNTR_SHIFT                        0


/****************************************************************************
 * dsc_1_A :: dfe_vga_ctrl0
 ***************************************************************************/
/* dsc_1_A :: dfe_vga_ctrl0 :: reserved_for_eco0 [15:12] */
#define DSC_1_A_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_MASK               0xf000
#define DSC_1_A_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_ALIGN              0
#define DSC_1_A_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_BITS               4
#define DSC_1_A_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_SHIFT              12

/* dsc_1_A :: dfe_vga_ctrl0 :: trnsum_tap0_only [11:11] */
#define DSC_1_A_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_MASK                0x0800
#define DSC_1_A_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_ALIGN               0
#define DSC_1_A_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_BITS                1
#define DSC_1_A_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_SHIFT               11

/* dsc_1_A :: dfe_vga_ctrl0 :: sum_m1err [10:10] */
#define DSC_1_A_DFE_VGA_CTRL0_SUM_M1ERR_MASK                       0x0400
#define DSC_1_A_DFE_VGA_CTRL0_SUM_M1ERR_ALIGN                      0
#define DSC_1_A_DFE_VGA_CTRL0_SUM_M1ERR_BITS                       1
#define DSC_1_A_DFE_VGA_CTRL0_SUM_M1ERR_SHIFT                      10

/* dsc_1_A :: dfe_vga_ctrl0 :: dfe_vga_clken [09:09] */
#define DSC_1_A_DFE_VGA_CTRL0_DFE_VGA_CLKEN_MASK                   0x0200
#define DSC_1_A_DFE_VGA_CTRL0_DFE_VGA_CLKEN_ALIGN                  0
#define DSC_1_A_DFE_VGA_CTRL0_DFE_VGA_CLKEN_BITS                   1
#define DSC_1_A_DFE_VGA_CTRL0_DFE_VGA_CLKEN_SHIFT                  9

/* dsc_1_A :: dfe_vga_ctrl0 :: hysteresis_en [08:08] */
#define DSC_1_A_DFE_VGA_CTRL0_HYSTERESIS_EN_MASK                   0x0100
#define DSC_1_A_DFE_VGA_CTRL0_HYSTERESIS_EN_ALIGN                  0
#define DSC_1_A_DFE_VGA_CTRL0_HYSTERESIS_EN_BITS                   1
#define DSC_1_A_DFE_VGA_CTRL0_HYSTERESIS_EN_SHIFT                  8

/* dsc_1_A :: dfe_vga_ctrl0 :: dfe_vga_write_val [07:02] */
#define DSC_1_A_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_MASK               0x00fc
#define DSC_1_A_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_ALIGN              0
#define DSC_1_A_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_BITS               6
#define DSC_1_A_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_SHIFT              2

/* dsc_1_A :: dfe_vga_ctrl0 :: vga_write_en [01:01] */
#define DSC_1_A_DFE_VGA_CTRL0_VGA_WRITE_EN_MASK                    0x0002
#define DSC_1_A_DFE_VGA_CTRL0_VGA_WRITE_EN_ALIGN                   0
#define DSC_1_A_DFE_VGA_CTRL0_VGA_WRITE_EN_BITS                    1
#define DSC_1_A_DFE_VGA_CTRL0_VGA_WRITE_EN_SHIFT                   1

/* dsc_1_A :: dfe_vga_ctrl0 :: dfe_write_en [00:00] */
#define DSC_1_A_DFE_VGA_CTRL0_DFE_WRITE_EN_MASK                    0x0001
#define DSC_1_A_DFE_VGA_CTRL0_DFE_WRITE_EN_ALIGN                   0
#define DSC_1_A_DFE_VGA_CTRL0_DFE_WRITE_EN_BITS                    1
#define DSC_1_A_DFE_VGA_CTRL0_DFE_WRITE_EN_SHIFT                   0


/****************************************************************************
 * dsc_1_A :: dfe_vga_ctrl1
 ***************************************************************************/
/* dsc_1_A :: dfe_vga_ctrl1 :: reserved_for_eco0 [15:15] */
#define DSC_1_A_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_MASK               0x8000
#define DSC_1_A_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_ALIGN              0
#define DSC_1_A_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_BITS               1
#define DSC_1_A_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_SHIFT              15

/* dsc_1_A :: dfe_vga_ctrl1 :: trnsum_otap_en [14:08] */
#define DSC_1_A_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_MASK                  0x7f00
#define DSC_1_A_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_ALIGN                 0
#define DSC_1_A_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_BITS                  7
#define DSC_1_A_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_SHIFT                 8

/* dsc_1_A :: dfe_vga_ctrl1 :: trnsum_etap_en [07:01] */
#define DSC_1_A_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_MASK                  0x00fe
#define DSC_1_A_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_ALIGN                 0
#define DSC_1_A_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_BITS                  7
#define DSC_1_A_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_SHIFT                 1

/* dsc_1_A :: dfe_vga_ctrl1 :: trnsum_en [00:00] */
#define DSC_1_A_DFE_VGA_CTRL1_TRNSUM_EN_MASK                       0x0001
#define DSC_1_A_DFE_VGA_CTRL1_TRNSUM_EN_ALIGN                      0
#define DSC_1_A_DFE_VGA_CTRL1_TRNSUM_EN_BITS                       1
#define DSC_1_A_DFE_VGA_CTRL1_TRNSUM_EN_SHIFT                      0


/****************************************************************************
 * dsc_1_A :: dfe_vga_ctrl2
 ***************************************************************************/
/* dsc_1_A :: dfe_vga_ctrl2 :: vga_polarity [15:15] */
#define DSC_1_A_DFE_VGA_CTRL2_VGA_POLARITY_MASK                    0x8000
#define DSC_1_A_DFE_VGA_CTRL2_VGA_POLARITY_ALIGN                   0
#define DSC_1_A_DFE_VGA_CTRL2_VGA_POLARITY_BITS                    1
#define DSC_1_A_DFE_VGA_CTRL2_VGA_POLARITY_SHIFT                   15

/* dsc_1_A :: dfe_vga_ctrl2 :: dfe_polarity [14:14] */
#define DSC_1_A_DFE_VGA_CTRL2_DFE_POLARITY_MASK                    0x4000
#define DSC_1_A_DFE_VGA_CTRL2_DFE_POLARITY_ALIGN                   0
#define DSC_1_A_DFE_VGA_CTRL2_DFE_POLARITY_BITS                    1
#define DSC_1_A_DFE_VGA_CTRL2_DFE_POLARITY_SHIFT                   14

/* dsc_1_A :: dfe_vga_ctrl2 :: trnsum_otap_sign [13:07] */
#define DSC_1_A_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_MASK                0x3f80
#define DSC_1_A_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_ALIGN               0
#define DSC_1_A_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_BITS                7
#define DSC_1_A_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_SHIFT               7

/* dsc_1_A :: dfe_vga_ctrl2 :: trnsum_etap_sign [06:00] */
#define DSC_1_A_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_MASK                0x007f
#define DSC_1_A_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_ALIGN               0
#define DSC_1_A_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_BITS                7
#define DSC_1_A_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_SHIFT               0


/****************************************************************************
 * dsc_1_A :: dfe_vga_ctrl3
 ***************************************************************************/
/* dsc_1_A :: dfe_vga_ctrl3 :: reserved_for_eco0 [15:10] */
#define DSC_1_A_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_MASK               0xfc00
#define DSC_1_A_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_ALIGN              0
#define DSC_1_A_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_BITS               6
#define DSC_1_A_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_SHIFT              10

/* dsc_1_A :: dfe_vga_ctrl3 :: vga_cor_sel_e [09:05] */
#define DSC_1_A_DFE_VGA_CTRL3_VGA_COR_SEL_E_MASK                   0x03e0
#define DSC_1_A_DFE_VGA_CTRL3_VGA_COR_SEL_E_ALIGN                  0
#define DSC_1_A_DFE_VGA_CTRL3_VGA_COR_SEL_E_BITS                   5
#define DSC_1_A_DFE_VGA_CTRL3_VGA_COR_SEL_E_SHIFT                  5

/* dsc_1_A :: dfe_vga_ctrl3 :: vga_cor_sel_o [04:00] */
#define DSC_1_A_DFE_VGA_CTRL3_VGA_COR_SEL_O_MASK                   0x001f
#define DSC_1_A_DFE_VGA_CTRL3_VGA_COR_SEL_O_ALIGN                  0
#define DSC_1_A_DFE_VGA_CTRL3_VGA_COR_SEL_O_BITS                   5
#define DSC_1_A_DFE_VGA_CTRL3_VGA_COR_SEL_O_SHIFT                  0


/****************************************************************************
 * dsc_1_A :: dfe_vga_ctrl4
 ***************************************************************************/
/* dsc_1_A :: dfe_vga_ctrl4 :: reserved_for_eco0 [15:10] */
#define DSC_1_A_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_MASK               0xfc00
#define DSC_1_A_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_ALIGN              0
#define DSC_1_A_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_BITS               6
#define DSC_1_A_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_SHIFT              10

/* dsc_1_A :: dfe_vga_ctrl4 :: dfe_cor_sel_e [09:05] */
#define DSC_1_A_DFE_VGA_CTRL4_DFE_COR_SEL_E_MASK                   0x03e0
#define DSC_1_A_DFE_VGA_CTRL4_DFE_COR_SEL_E_ALIGN                  0
#define DSC_1_A_DFE_VGA_CTRL4_DFE_COR_SEL_E_BITS                   5
#define DSC_1_A_DFE_VGA_CTRL4_DFE_COR_SEL_E_SHIFT                  5

/* dsc_1_A :: dfe_vga_ctrl4 :: dfe_cor_sel_o [04:00] */
#define DSC_1_A_DFE_VGA_CTRL4_DFE_COR_SEL_O_MASK                   0x001f
#define DSC_1_A_DFE_VGA_CTRL4_DFE_COR_SEL_O_ALIGN                  0
#define DSC_1_A_DFE_VGA_CTRL4_DFE_COR_SEL_O_BITS                   5
#define DSC_1_A_DFE_VGA_CTRL4_DFE_COR_SEL_O_SHIFT                  0


/****************************************************************************
 * dsc_1_A :: dfe_vga_status0
 ***************************************************************************/
/* dsc_1_A :: dfe_vga_status0 :: vga_sum [15:11] */
#define DSC_1_A_DFE_VGA_STATUS0_VGA_SUM_MASK                       0xf800
#define DSC_1_A_DFE_VGA_STATUS0_VGA_SUM_ALIGN                      0
#define DSC_1_A_DFE_VGA_STATUS0_VGA_SUM_BITS                       5
#define DSC_1_A_DFE_VGA_STATUS0_VGA_SUM_SHIFT                      11

/* dsc_1_A :: dfe_vga_status0 :: trnsum [10:00] */
#define DSC_1_A_DFE_VGA_STATUS0_TRNSUM_MASK                        0x07ff
#define DSC_1_A_DFE_VGA_STATUS0_TRNSUM_ALIGN                       0
#define DSC_1_A_DFE_VGA_STATUS0_TRNSUM_BITS                        11
#define DSC_1_A_DFE_VGA_STATUS0_TRNSUM_SHIFT                       0


/****************************************************************************
 * dsc_1_A :: dfe_vga_status1
 ***************************************************************************/
/* dsc_1_A :: dfe_vga_status1 :: odd_dfe_acc [15:06] */
#define DSC_1_A_DFE_VGA_STATUS1_ODD_DFE_ACC_MASK                   0xffc0
#define DSC_1_A_DFE_VGA_STATUS1_ODD_DFE_ACC_ALIGN                  0
#define DSC_1_A_DFE_VGA_STATUS1_ODD_DFE_ACC_BITS                   10
#define DSC_1_A_DFE_VGA_STATUS1_ODD_DFE_ACC_SHIFT                  6

/* dsc_1_A :: dfe_vga_status1 :: dfe_tap_bin [05:00] */
#define DSC_1_A_DFE_VGA_STATUS1_DFE_TAP_BIN_MASK                   0x003f
#define DSC_1_A_DFE_VGA_STATUS1_DFE_TAP_BIN_ALIGN                  0
#define DSC_1_A_DFE_VGA_STATUS1_DFE_TAP_BIN_BITS                   6
#define DSC_1_A_DFE_VGA_STATUS1_DFE_TAP_BIN_SHIFT                  0


/****************************************************************************
 * dsc_1_A :: dfe_vga_status2
 ***************************************************************************/
/* dsc_1_A :: dfe_vga_status2 :: reserved_for_eco0 [15:10] */
#define DSC_1_A_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_MASK             0xfc00
#define DSC_1_A_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_ALIGN            0
#define DSC_1_A_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_BITS             6
#define DSC_1_A_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_SHIFT            10

/* dsc_1_A :: dfe_vga_status2 :: evn_dfe_acc [09:00] */
#define DSC_1_A_DFE_VGA_STATUS2_EVN_DFE_ACC_MASK                   0x03ff
#define DSC_1_A_DFE_VGA_STATUS2_EVN_DFE_ACC_ALIGN                  0
#define DSC_1_A_DFE_VGA_STATUS2_EVN_DFE_ACC_BITS                   10
#define DSC_1_A_DFE_VGA_STATUS2_EVN_DFE_ACC_SHIFT                  0


/****************************************************************************
 * XGXS16G_USER_dsc_2_0
 ***************************************************************************/
/****************************************************************************
 * dsc_2_0 :: sm_status0
 ***************************************************************************/
/* dsc_2_0 :: sm_status0 :: reserved_for_eco0 [15:04] */
#define DSC_2_0_SM_STATUS0_RESERVED_FOR_ECO0_MASK                  0xfff0
#define DSC_2_0_SM_STATUS0_RESERVED_FOR_ECO0_ALIGN                 0
#define DSC_2_0_SM_STATUS0_RESERVED_FOR_ECO0_BITS                  12
#define DSC_2_0_SM_STATUS0_RESERVED_FOR_ECO0_SHIFT                 4

/* dsc_2_0 :: sm_status0 :: dsc_state [03:00] */
#define DSC_2_0_SM_STATUS0_DSC_STATE_MASK                          0x000f
#define DSC_2_0_SM_STATUS0_DSC_STATE_ALIGN                         0
#define DSC_2_0_SM_STATUS0_DSC_STATE_BITS                          4
#define DSC_2_0_SM_STATUS0_DSC_STATE_SHIFT                         0


/****************************************************************************
 * dsc_2_0 :: sm_ctrl0
 ***************************************************************************/
/* dsc_2_0 :: sm_ctrl0 :: acqvga_timeout [15:11] */
#define DSC_2_0_SM_CTRL0_ACQVGA_TIMEOUT_MASK                       0xf800
#define DSC_2_0_SM_CTRL0_ACQVGA_TIMEOUT_ALIGN                      0
#define DSC_2_0_SM_CTRL0_ACQVGA_TIMEOUT_BITS                       5
#define DSC_2_0_SM_CTRL0_ACQVGA_TIMEOUT_SHIFT                      11

/* dsc_2_0 :: sm_ctrl0 :: tuning_sm_en [10:10] */
#define DSC_2_0_SM_CTRL0_TUNING_SM_EN_MASK                         0x0400
#define DSC_2_0_SM_CTRL0_TUNING_SM_EN_ALIGN                        0
#define DSC_2_0_SM_CTRL0_TUNING_SM_EN_BITS                         1
#define DSC_2_0_SM_CTRL0_TUNING_SM_EN_SHIFT                        10

/* dsc_2_0 :: sm_ctrl0 :: train2_req [09:09] */
#define DSC_2_0_SM_CTRL0_TRAIN2_REQ_MASK                           0x0200
#define DSC_2_0_SM_CTRL0_TRAIN2_REQ_ALIGN                          0
#define DSC_2_0_SM_CTRL0_TRAIN2_REQ_BITS                           1
#define DSC_2_0_SM_CTRL0_TRAIN2_REQ_SHIFT                          9

/* dsc_2_0 :: sm_ctrl0 :: train1_req [08:08] */
#define DSC_2_0_SM_CTRL0_TRAIN1_REQ_MASK                           0x0100
#define DSC_2_0_SM_CTRL0_TRAIN1_REQ_ALIGN                          0
#define DSC_2_0_SM_CTRL0_TRAIN1_REQ_BITS                           1
#define DSC_2_0_SM_CTRL0_TRAIN1_REQ_SHIFT                          8

/* dsc_2_0 :: sm_ctrl0 :: soft_ack [07:07] */
#define DSC_2_0_SM_CTRL0_SOFT_ACK_MASK                             0x0080
#define DSC_2_0_SM_CTRL0_SOFT_ACK_ALIGN                            0
#define DSC_2_0_SM_CTRL0_SOFT_ACK_BITS                             1
#define DSC_2_0_SM_CTRL0_SOFT_ACK_SHIFT                            7

/* dsc_2_0 :: sm_ctrl0 :: train_mode_en [06:06] */
#define DSC_2_0_SM_CTRL0_TRAIN_MODE_EN_MASK                        0x0040
#define DSC_2_0_SM_CTRL0_TRAIN_MODE_EN_ALIGN                       0
#define DSC_2_0_SM_CTRL0_TRAIN_MODE_EN_BITS                        1
#define DSC_2_0_SM_CTRL0_TRAIN_MODE_EN_SHIFT                       6

/* dsc_2_0 :: sm_ctrl0 :: vga_frzval [05:05] */
#define DSC_2_0_SM_CTRL0_VGA_FRZVAL_MASK                           0x0020
#define DSC_2_0_SM_CTRL0_VGA_FRZVAL_ALIGN                          0
#define DSC_2_0_SM_CTRL0_VGA_FRZVAL_BITS                           1
#define DSC_2_0_SM_CTRL0_VGA_FRZVAL_SHIFT                          5

/* dsc_2_0 :: sm_ctrl0 :: vga_frcfrz [04:04] */
#define DSC_2_0_SM_CTRL0_VGA_FRCFRZ_MASK                           0x0010
#define DSC_2_0_SM_CTRL0_VGA_FRCFRZ_ALIGN                          0
#define DSC_2_0_SM_CTRL0_VGA_FRCFRZ_BITS                           1
#define DSC_2_0_SM_CTRL0_VGA_FRCFRZ_SHIFT                          4

/* dsc_2_0 :: sm_ctrl0 :: dfe_frzval [03:03] */
#define DSC_2_0_SM_CTRL0_DFE_FRZVAL_MASK                           0x0008
#define DSC_2_0_SM_CTRL0_DFE_FRZVAL_ALIGN                          0
#define DSC_2_0_SM_CTRL0_DFE_FRZVAL_BITS                           1
#define DSC_2_0_SM_CTRL0_DFE_FRZVAL_SHIFT                          3

/* dsc_2_0 :: sm_ctrl0 :: dfe_frcfrz [02:02] */
#define DSC_2_0_SM_CTRL0_DFE_FRCFRZ_MASK                           0x0004
#define DSC_2_0_SM_CTRL0_DFE_FRCFRZ_ALIGN                          0
#define DSC_2_0_SM_CTRL0_DFE_FRCFRZ_BITS                           1
#define DSC_2_0_SM_CTRL0_DFE_FRCFRZ_SHIFT                          2

/* dsc_2_0 :: sm_ctrl0 :: dsc_clr_val [01:01] */
#define DSC_2_0_SM_CTRL0_DSC_CLR_VAL_MASK                          0x0002
#define DSC_2_0_SM_CTRL0_DSC_CLR_VAL_ALIGN                         0
#define DSC_2_0_SM_CTRL0_DSC_CLR_VAL_BITS                          1
#define DSC_2_0_SM_CTRL0_DSC_CLR_VAL_SHIFT                         1

/* dsc_2_0 :: sm_ctrl0 :: dsc_clr_frc [00:00] */
#define DSC_2_0_SM_CTRL0_DSC_CLR_FRC_MASK                          0x0001
#define DSC_2_0_SM_CTRL0_DSC_CLR_FRC_ALIGN                         0
#define DSC_2_0_SM_CTRL0_DSC_CLR_FRC_BITS                          1
#define DSC_2_0_SM_CTRL0_DSC_CLR_FRC_SHIFT                         0


/****************************************************************************
 * dsc_2_0 :: sm_ctrl1
 ***************************************************************************/
/* dsc_2_0 :: sm_ctrl1 :: fast_timer [15:15] */
#define DSC_2_0_SM_CTRL1_FAST_TIMER_MASK                           0x8000
#define DSC_2_0_SM_CTRL1_FAST_TIMER_ALIGN                          0
#define DSC_2_0_SM_CTRL1_FAST_TIMER_BITS                           1
#define DSC_2_0_SM_CTRL1_FAST_TIMER_SHIFT                          15

/* dsc_2_0 :: sm_ctrl1 :: acq2_timeout [14:10] */
#define DSC_2_0_SM_CTRL1_ACQ2_TIMEOUT_MASK                         0x7c00
#define DSC_2_0_SM_CTRL1_ACQ2_TIMEOUT_ALIGN                        0
#define DSC_2_0_SM_CTRL1_ACQ2_TIMEOUT_BITS                         5
#define DSC_2_0_SM_CTRL1_ACQ2_TIMEOUT_SHIFT                        10

/* dsc_2_0 :: sm_ctrl1 :: acq1_timeout [09:05] */
#define DSC_2_0_SM_CTRL1_ACQ1_TIMEOUT_MASK                         0x03e0
#define DSC_2_0_SM_CTRL1_ACQ1_TIMEOUT_ALIGN                        0
#define DSC_2_0_SM_CTRL1_ACQ1_TIMEOUT_BITS                         5
#define DSC_2_0_SM_CTRL1_ACQ1_TIMEOUT_SHIFT                        5

/* dsc_2_0 :: sm_ctrl1 :: acqcdr_timeout [04:00] */
#define DSC_2_0_SM_CTRL1_ACQCDR_TIMEOUT_MASK                       0x001f
#define DSC_2_0_SM_CTRL1_ACQCDR_TIMEOUT_ALIGN                      0
#define DSC_2_0_SM_CTRL1_ACQCDR_TIMEOUT_BITS                       5
#define DSC_2_0_SM_CTRL1_ACQCDR_TIMEOUT_SHIFT                      0


/****************************************************************************
 * dsc_2_0 :: sm_ctrl2
 ***************************************************************************/
/* dsc_2_0 :: sm_ctrl2 :: reserved_for_eco0 [15:15] */
#define DSC_2_0_SM_CTRL2_RESERVED_FOR_ECO0_MASK                    0x8000
#define DSC_2_0_SM_CTRL2_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC_2_0_SM_CTRL2_RESERVED_FOR_ECO0_BITS                    1
#define DSC_2_0_SM_CTRL2_RESERVED_FOR_ECO0_SHIFT                   15

/* dsc_2_0 :: sm_ctrl2 :: cdrbr_bwsel_prop_acqcdr [14:12] */
#define DSC_2_0_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_MASK              0x7000
#define DSC_2_0_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_ALIGN             0
#define DSC_2_0_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_BITS              3
#define DSC_2_0_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_SHIFT             12

/* dsc_2_0 :: sm_ctrl2 :: dfe_gain_acq2 [11:10] */
#define DSC_2_0_SM_CTRL2_DFE_GAIN_ACQ2_MASK                        0x0c00
#define DSC_2_0_SM_CTRL2_DFE_GAIN_ACQ2_ALIGN                       0
#define DSC_2_0_SM_CTRL2_DFE_GAIN_ACQ2_BITS                        2
#define DSC_2_0_SM_CTRL2_DFE_GAIN_ACQ2_SHIFT                       10

/* dsc_2_0 :: sm_ctrl2 :: dfe_gain_acq1 [09:08] */
#define DSC_2_0_SM_CTRL2_DFE_GAIN_ACQ1_MASK                        0x0300
#define DSC_2_0_SM_CTRL2_DFE_GAIN_ACQ1_ALIGN                       0
#define DSC_2_0_SM_CTRL2_DFE_GAIN_ACQ1_BITS                        2
#define DSC_2_0_SM_CTRL2_DFE_GAIN_ACQ1_SHIFT                       8

/* dsc_2_0 :: sm_ctrl2 :: vga_gain_acq2 [07:06] */
#define DSC_2_0_SM_CTRL2_VGA_GAIN_ACQ2_MASK                        0x00c0
#define DSC_2_0_SM_CTRL2_VGA_GAIN_ACQ2_ALIGN                       0
#define DSC_2_0_SM_CTRL2_VGA_GAIN_ACQ2_BITS                        2
#define DSC_2_0_SM_CTRL2_VGA_GAIN_ACQ2_SHIFT                       6

/* dsc_2_0 :: sm_ctrl2 :: vga_gain_acq1 [05:04] */
#define DSC_2_0_SM_CTRL2_VGA_GAIN_ACQ1_MASK                        0x0030
#define DSC_2_0_SM_CTRL2_VGA_GAIN_ACQ1_ALIGN                       0
#define DSC_2_0_SM_CTRL2_VGA_GAIN_ACQ1_BITS                        2
#define DSC_2_0_SM_CTRL2_VGA_GAIN_ACQ1_SHIFT                       4

/* dsc_2_0 :: sm_ctrl2 :: vga_gain_acqcdr [03:02] */
#define DSC_2_0_SM_CTRL2_VGA_GAIN_ACQCDR_MASK                      0x000c
#define DSC_2_0_SM_CTRL2_VGA_GAIN_ACQCDR_ALIGN                     0
#define DSC_2_0_SM_CTRL2_VGA_GAIN_ACQCDR_BITS                      2
#define DSC_2_0_SM_CTRL2_VGA_GAIN_ACQCDR_SHIFT                     2

/* dsc_2_0 :: sm_ctrl2 :: vga_gain_acqvga [01:00] */
#define DSC_2_0_SM_CTRL2_VGA_GAIN_ACQVGA_MASK                      0x0003
#define DSC_2_0_SM_CTRL2_VGA_GAIN_ACQVGA_ALIGN                     0
#define DSC_2_0_SM_CTRL2_VGA_GAIN_ACQVGA_BITS                      2
#define DSC_2_0_SM_CTRL2_VGA_GAIN_ACQVGA_SHIFT                     0


/****************************************************************************
 * dsc_2_0 :: sm_ctrl3
 ***************************************************************************/
/* dsc_2_0 :: sm_ctrl3 :: reserved_for_eco0 [15:12] */
#define DSC_2_0_SM_CTRL3_RESERVED_FOR_ECO0_MASK                    0xf000
#define DSC_2_0_SM_CTRL3_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC_2_0_SM_CTRL3_RESERVED_FOR_ECO0_BITS                    4
#define DSC_2_0_SM_CTRL3_RESERVED_FOR_ECO0_SHIFT                   12

/* dsc_2_0 :: sm_ctrl3 :: cdrbr_bwsel_integ_acq2 [11:10] */
#define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_MASK               0x0c00
#define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_ALIGN              0
#define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_BITS               2
#define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_SHIFT              10

/* dsc_2_0 :: sm_ctrl3 :: cdrbr_bwsel_integ_acq1 [09:08] */
#define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_MASK               0x0300
#define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_ALIGN              0
#define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_BITS               2
#define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_SHIFT              8

/* dsc_2_0 :: sm_ctrl3 :: cdrbr_bwsel_integ_acqcdr [07:06] */
#define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_MASK             0x00c0
#define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_ALIGN            0
#define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_BITS             2
#define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_SHIFT            6

/* dsc_2_0 :: sm_ctrl3 :: cdrbr_bwsel_prop_acq2 [05:03] */
#define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_MASK                0x0038
#define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_ALIGN               0
#define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_BITS                3
#define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_SHIFT               3

/* dsc_2_0 :: sm_ctrl3 :: cdrbr_bwsel_prop_acq1 [02:00] */
#define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_MASK                0x0007
#define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_ALIGN               0
#define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_BITS                3
#define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_SHIFT               0


/****************************************************************************
 * dsc_2_0 :: sm_ctrl4
 ***************************************************************************/
/* dsc_2_0 :: sm_ctrl4 :: cdros_bwsel_integ_acq1_2 [15:12] */
#define DSC_2_0_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_MASK             0xf000
#define DSC_2_0_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_ALIGN            0
#define DSC_2_0_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_BITS             4
#define DSC_2_0_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_SHIFT            12

/* dsc_2_0 :: sm_ctrl4 :: cdros_bwsel_integ_acqcdr [11:08] */
#define DSC_2_0_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_MASK             0x0f00
#define DSC_2_0_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_ALIGN            0
#define DSC_2_0_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_BITS             4
#define DSC_2_0_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_SHIFT            8

/* dsc_2_0 :: sm_ctrl4 :: cdros_bwsel_prop_acq1_2 [07:04] */
#define DSC_2_0_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_MASK              0x00f0
#define DSC_2_0_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_ALIGN             0
#define DSC_2_0_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_BITS              4
#define DSC_2_0_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_SHIFT             4

/* dsc_2_0 :: sm_ctrl4 :: cdros_bwsel_prop_acqcdr [03:00] */
#define DSC_2_0_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_MASK              0x000f
#define DSC_2_0_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_ALIGN             0
#define DSC_2_0_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_BITS              4
#define DSC_2_0_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_SHIFT             0


/****************************************************************************
 * dsc_2_0 :: dsc_status0
 ***************************************************************************/
/* dsc_2_0 :: dsc_status0 :: data_15_to_0 [15:00] */
#define DSC_2_0_DSC_STATUS0_DATA_15_TO_0_MASK                      0xffff
#define DSC_2_0_DSC_STATUS0_DATA_15_TO_0_ALIGN                     0
#define DSC_2_0_DSC_STATUS0_DATA_15_TO_0_BITS                      16
#define DSC_2_0_DSC_STATUS0_DATA_15_TO_0_SHIFT                     0


/****************************************************************************
 * dsc_2_0 :: dsc_status1
 ***************************************************************************/
/* dsc_2_0 :: dsc_status1 :: p1err_11_to_0 [15:04] */
#define DSC_2_0_DSC_STATUS1_P1ERR_11_TO_0_MASK                     0xfff0
#define DSC_2_0_DSC_STATUS1_P1ERR_11_TO_0_ALIGN                    0
#define DSC_2_0_DSC_STATUS1_P1ERR_11_TO_0_BITS                     12
#define DSC_2_0_DSC_STATUS1_P1ERR_11_TO_0_SHIFT                    4

/* dsc_2_0 :: dsc_status1 :: data_19_to_16 [03:00] */
#define DSC_2_0_DSC_STATUS1_DATA_19_TO_16_MASK                     0x000f
#define DSC_2_0_DSC_STATUS1_DATA_19_TO_16_ALIGN                    0
#define DSC_2_0_DSC_STATUS1_DATA_19_TO_16_BITS                     4
#define DSC_2_0_DSC_STATUS1_DATA_19_TO_16_SHIFT                    0


/****************************************************************************
 * dsc_2_0 :: dsc_status2
 ***************************************************************************/
/* dsc_2_0 :: dsc_status2 :: m1err_7_to_0 [15:08] */
#define DSC_2_0_DSC_STATUS2_M1ERR_7_TO_0_MASK                      0xff00
#define DSC_2_0_DSC_STATUS2_M1ERR_7_TO_0_ALIGN                     0
#define DSC_2_0_DSC_STATUS2_M1ERR_7_TO_0_BITS                      8
#define DSC_2_0_DSC_STATUS2_M1ERR_7_TO_0_SHIFT                     8

/* dsc_2_0 :: dsc_status2 :: p1err_19_to_12 [07:00] */
#define DSC_2_0_DSC_STATUS2_P1ERR_19_TO_12_MASK                    0x00ff
#define DSC_2_0_DSC_STATUS2_P1ERR_19_TO_12_ALIGN                   0
#define DSC_2_0_DSC_STATUS2_P1ERR_19_TO_12_BITS                    8
#define DSC_2_0_DSC_STATUS2_P1ERR_19_TO_12_SHIFT                   0


/****************************************************************************
 * dsc_2_0 :: dsc_status3
 ***************************************************************************/
/* dsc_2_0 :: dsc_status3 :: reserved_for_eco0 [15:12] */
#define DSC_2_0_DSC_STATUS3_RESERVED_FOR_ECO0_MASK                 0xf000
#define DSC_2_0_DSC_STATUS3_RESERVED_FOR_ECO0_ALIGN                0
#define DSC_2_0_DSC_STATUS3_RESERVED_FOR_ECO0_BITS                 4
#define DSC_2_0_DSC_STATUS3_RESERVED_FOR_ECO0_SHIFT                12

/* dsc_2_0 :: dsc_status3 :: m1err_19_to_8 [11:00] */
#define DSC_2_0_DSC_STATUS3_M1ERR_19_TO_8_MASK                     0x0fff
#define DSC_2_0_DSC_STATUS3_M1ERR_19_TO_8_ALIGN                    0
#define DSC_2_0_DSC_STATUS3_M1ERR_19_TO_8_BITS                     12
#define DSC_2_0_DSC_STATUS3_M1ERR_19_TO_8_SHIFT                    0


/****************************************************************************
 * dsc_2_0 :: dsc_ctrl0
 ***************************************************************************/
/* dsc_2_0 :: dsc_ctrl0 :: rxSeqStart [15:15] */
#define DSC_2_0_DSC_CTRL0_RXSEQSTART_MASK                          0x8000
#define DSC_2_0_DSC_CTRL0_RXSEQSTART_ALIGN                         0
#define DSC_2_0_DSC_CTRL0_RXSEQSTART_BITS                          1
#define DSC_2_0_DSC_CTRL0_RXSEQSTART_SHIFT                         15

/* dsc_2_0 :: dsc_ctrl0 :: forceRxSeqDone [14:14] */
#define DSC_2_0_DSC_CTRL0_FORCERXSEQDONE_MASK                      0x4000
#define DSC_2_0_DSC_CTRL0_FORCERXSEQDONE_ALIGN                     0
#define DSC_2_0_DSC_CTRL0_FORCERXSEQDONE_BITS                      1
#define DSC_2_0_DSC_CTRL0_FORCERXSEQDONE_SHIFT                     14

/* dsc_2_0 :: dsc_ctrl0 :: test_bus_sel [13:10] */
#define DSC_2_0_DSC_CTRL0_TEST_BUS_SEL_MASK                        0x3c00
#define DSC_2_0_DSC_CTRL0_TEST_BUS_SEL_ALIGN                       0
#define DSC_2_0_DSC_CTRL0_TEST_BUS_SEL_BITS                        4
#define DSC_2_0_DSC_CTRL0_TEST_BUS_SEL_SHIFT                       10
#define DSC_2_0_DSC_CTRL0_TEST_BUS_SEL_Off                         0
#define DSC_2_0_DSC_CTRL0_TEST_BUS_SEL_OSx2data                    1
#define DSC_2_0_DSC_CTRL0_TEST_BUS_SEL_OSx1data_m1                 2
#define DSC_2_0_DSC_CTRL0_TEST_BUS_SEL_BR_data_m1_p1               3
#define DSC_2_0_DSC_CTRL0_TEST_BUS_SEL_cdrPhaseVco                 4
#define DSC_2_0_DSC_CTRL0_TEST_BUS_SEL_cdrIntg                     6
#define DSC_2_0_DSC_CTRL0_TEST_BUS_SEL_cdrPhaseErr                 7
#define DSC_2_0_DSC_CTRL0_TEST_BUS_SEL_dfeAccEvenOdd               8
#define DSC_2_0_DSC_CTRL0_TEST_BUS_SEL_dfeVgasumDfe                9
#define DSC_2_0_DSC_CTRL0_TEST_BUS_SEL_dfeTrnsum                   10

/* dsc_2_0 :: dsc_ctrl0 :: rx_m1_thresh_zero [09:09] */
#define DSC_2_0_DSC_CTRL0_RX_M1_THRESH_ZERO_MASK                   0x0200
#define DSC_2_0_DSC_CTRL0_RX_M1_THRESH_ZERO_ALIGN                  0
#define DSC_2_0_DSC_CTRL0_RX_M1_THRESH_ZERO_BITS                   1
#define DSC_2_0_DSC_CTRL0_RX_M1_THRESH_ZERO_SHIFT                  9

/* dsc_2_0 :: dsc_ctrl0 :: rx_thresh_sel [08:07] */
#define DSC_2_0_DSC_CTRL0_RX_THRESH_SEL_MASK                       0x0180
#define DSC_2_0_DSC_CTRL0_RX_THRESH_SEL_ALIGN                      0
#define DSC_2_0_DSC_CTRL0_RX_THRESH_SEL_BITS                       2
#define DSC_2_0_DSC_CTRL0_RX_THRESH_SEL_SHIFT                      7

/* dsc_2_0 :: dsc_ctrl0 :: rx_pf_ctrl [06:04] */
#define DSC_2_0_DSC_CTRL0_RX_PF_CTRL_MASK                          0x0070
#define DSC_2_0_DSC_CTRL0_RX_PF_CTRL_ALIGN                         0
#define DSC_2_0_DSC_CTRL0_RX_PF_CTRL_BITS                          3
#define DSC_2_0_DSC_CTRL0_RX_PF_CTRL_SHIFT                         4

/* dsc_2_0 :: dsc_ctrl0 :: cdrbr_sel [03:03] */
#define DSC_2_0_DSC_CTRL0_CDRBR_SEL_MASK                           0x0008
#define DSC_2_0_DSC_CTRL0_CDRBR_SEL_ALIGN                          0
#define DSC_2_0_DSC_CTRL0_CDRBR_SEL_BITS                           1
#define DSC_2_0_DSC_CTRL0_CDRBR_SEL_SHIFT                          3

/* dsc_2_0 :: dsc_ctrl0 :: oscdr_force_mode_en [02:02] */
#define DSC_2_0_DSC_CTRL0_OSCDR_FORCE_MODE_EN_MASK                 0x0004
#define DSC_2_0_DSC_CTRL0_OSCDR_FORCE_MODE_EN_ALIGN                0
#define DSC_2_0_DSC_CTRL0_OSCDR_FORCE_MODE_EN_BITS                 1
#define DSC_2_0_DSC_CTRL0_OSCDR_FORCE_MODE_EN_SHIFT                2

/* dsc_2_0 :: dsc_ctrl0 :: oscdr_mode [01:00] */
#define DSC_2_0_DSC_CTRL0_OSCDR_MODE_MASK                          0x0003
#define DSC_2_0_DSC_CTRL0_OSCDR_MODE_ALIGN                         0
#define DSC_2_0_DSC_CTRL0_OSCDR_MODE_BITS                          2
#define DSC_2_0_DSC_CTRL0_OSCDR_MODE_SHIFT                         0


/****************************************************************************
 * dsc_2_0 :: dsc_ctrl1
 ***************************************************************************/
/* dsc_2_0 :: dsc_ctrl1 :: reserved_for_eco0 [15:15] */
#define DSC_2_0_DSC_CTRL1_RESERVED_FOR_ECO0_MASK                   0x8000
#define DSC_2_0_DSC_CTRL1_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC_2_0_DSC_CTRL1_RESERVED_FOR_ECO0_BITS                   1
#define DSC_2_0_DSC_CTRL1_RESERVED_FOR_ECO0_SHIFT                  15

/* dsc_2_0 :: dsc_ctrl1 :: p1_odd_ctrl [14:10] */
#define DSC_2_0_DSC_CTRL1_P1_ODD_CTRL_MASK                         0x7c00
#define DSC_2_0_DSC_CTRL1_P1_ODD_CTRL_ALIGN                        0
#define DSC_2_0_DSC_CTRL1_P1_ODD_CTRL_BITS                         5
#define DSC_2_0_DSC_CTRL1_P1_ODD_CTRL_SHIFT                        10

/* dsc_2_0 :: dsc_ctrl1 :: p1_evn_ctrl [09:05] */
#define DSC_2_0_DSC_CTRL1_P1_EVN_CTRL_MASK                         0x03e0
#define DSC_2_0_DSC_CTRL1_P1_EVN_CTRL_ALIGN                        0
#define DSC_2_0_DSC_CTRL1_P1_EVN_CTRL_BITS                         5
#define DSC_2_0_DSC_CTRL1_P1_EVN_CTRL_SHIFT                        5

/* dsc_2_0 :: dsc_ctrl1 :: d_odd_ctrl [04:00] */
#define DSC_2_0_DSC_CTRL1_D_ODD_CTRL_MASK                          0x001f
#define DSC_2_0_DSC_CTRL1_D_ODD_CTRL_ALIGN                         0
#define DSC_2_0_DSC_CTRL1_D_ODD_CTRL_BITS                          5
#define DSC_2_0_DSC_CTRL1_D_ODD_CTRL_SHIFT                         0


/****************************************************************************
 * dsc_2_0 :: dsc_ctrl2
 ***************************************************************************/
/* dsc_2_0 :: dsc_ctrl2 :: reserved_for_eco0 [15:15] */
#define DSC_2_0_DSC_CTRL2_RESERVED_FOR_ECO0_MASK                   0x8000
#define DSC_2_0_DSC_CTRL2_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC_2_0_DSC_CTRL2_RESERVED_FOR_ECO0_BITS                   1
#define DSC_2_0_DSC_CTRL2_RESERVED_FOR_ECO0_SHIFT                  15

/* dsc_2_0 :: dsc_ctrl2 :: d_evn_ctrl [14:10] */
#define DSC_2_0_DSC_CTRL2_D_EVN_CTRL_MASK                          0x7c00
#define DSC_2_0_DSC_CTRL2_D_EVN_CTRL_ALIGN                         0
#define DSC_2_0_DSC_CTRL2_D_EVN_CTRL_BITS                          5
#define DSC_2_0_DSC_CTRL2_D_EVN_CTRL_SHIFT                         10

/* dsc_2_0 :: dsc_ctrl2 :: m1_odd_ctrl [09:05] */
#define DSC_2_0_DSC_CTRL2_M1_ODD_CTRL_MASK                         0x03e0
#define DSC_2_0_DSC_CTRL2_M1_ODD_CTRL_ALIGN                        0
#define DSC_2_0_DSC_CTRL2_M1_ODD_CTRL_BITS                         5
#define DSC_2_0_DSC_CTRL2_M1_ODD_CTRL_SHIFT                        5

/* dsc_2_0 :: dsc_ctrl2 :: m1_evn_ctrl [04:00] */
#define DSC_2_0_DSC_CTRL2_M1_EVN_CTRL_MASK                         0x001f
#define DSC_2_0_DSC_CTRL2_M1_EVN_CTRL_ALIGN                        0
#define DSC_2_0_DSC_CTRL2_M1_EVN_CTRL_BITS                         5
#define DSC_2_0_DSC_CTRL2_M1_EVN_CTRL_SHIFT                        0


/****************************************************************************
 * XGXS16G_USER_dsc_2_1
 ***************************************************************************/
/****************************************************************************
 * dsc_2_1 :: sm_status0
 ***************************************************************************/
/* dsc_2_1 :: sm_status0 :: reserved_for_eco0 [15:04] */
#define DSC_2_1_SM_STATUS0_RESERVED_FOR_ECO0_MASK                  0xfff0
#define DSC_2_1_SM_STATUS0_RESERVED_FOR_ECO0_ALIGN                 0
#define DSC_2_1_SM_STATUS0_RESERVED_FOR_ECO0_BITS                  12
#define DSC_2_1_SM_STATUS0_RESERVED_FOR_ECO0_SHIFT                 4

/* dsc_2_1 :: sm_status0 :: dsc_state [03:00] */
#define DSC_2_1_SM_STATUS0_DSC_STATE_MASK                          0x000f
#define DSC_2_1_SM_STATUS0_DSC_STATE_ALIGN                         0
#define DSC_2_1_SM_STATUS0_DSC_STATE_BITS                          4
#define DSC_2_1_SM_STATUS0_DSC_STATE_SHIFT                         0


/****************************************************************************
 * dsc_2_1 :: sm_ctrl0
 ***************************************************************************/
/* dsc_2_1 :: sm_ctrl0 :: acqvga_timeout [15:11] */
#define DSC_2_1_SM_CTRL0_ACQVGA_TIMEOUT_MASK                       0xf800
#define DSC_2_1_SM_CTRL0_ACQVGA_TIMEOUT_ALIGN                      0
#define DSC_2_1_SM_CTRL0_ACQVGA_TIMEOUT_BITS                       5
#define DSC_2_1_SM_CTRL0_ACQVGA_TIMEOUT_SHIFT                      11

/* dsc_2_1 :: sm_ctrl0 :: tuning_sm_en [10:10] */
#define DSC_2_1_SM_CTRL0_TUNING_SM_EN_MASK                         0x0400
#define DSC_2_1_SM_CTRL0_TUNING_SM_EN_ALIGN                        0
#define DSC_2_1_SM_CTRL0_TUNING_SM_EN_BITS                         1
#define DSC_2_1_SM_CTRL0_TUNING_SM_EN_SHIFT                        10

/* dsc_2_1 :: sm_ctrl0 :: train2_req [09:09] */
#define DSC_2_1_SM_CTRL0_TRAIN2_REQ_MASK                           0x0200
#define DSC_2_1_SM_CTRL0_TRAIN2_REQ_ALIGN                          0
#define DSC_2_1_SM_CTRL0_TRAIN2_REQ_BITS                           1
#define DSC_2_1_SM_CTRL0_TRAIN2_REQ_SHIFT                          9

/* dsc_2_1 :: sm_ctrl0 :: train1_req [08:08] */
#define DSC_2_1_SM_CTRL0_TRAIN1_REQ_MASK                           0x0100
#define DSC_2_1_SM_CTRL0_TRAIN1_REQ_ALIGN                          0
#define DSC_2_1_SM_CTRL0_TRAIN1_REQ_BITS                           1
#define DSC_2_1_SM_CTRL0_TRAIN1_REQ_SHIFT                          8

/* dsc_2_1 :: sm_ctrl0 :: soft_ack [07:07] */
#define DSC_2_1_SM_CTRL0_SOFT_ACK_MASK                             0x0080
#define DSC_2_1_SM_CTRL0_SOFT_ACK_ALIGN                            0
#define DSC_2_1_SM_CTRL0_SOFT_ACK_BITS                             1
#define DSC_2_1_SM_CTRL0_SOFT_ACK_SHIFT                            7

/* dsc_2_1 :: sm_ctrl0 :: train_mode_en [06:06] */
#define DSC_2_1_SM_CTRL0_TRAIN_MODE_EN_MASK                        0x0040
#define DSC_2_1_SM_CTRL0_TRAIN_MODE_EN_ALIGN                       0
#define DSC_2_1_SM_CTRL0_TRAIN_MODE_EN_BITS                        1
#define DSC_2_1_SM_CTRL0_TRAIN_MODE_EN_SHIFT                       6

/* dsc_2_1 :: sm_ctrl0 :: vga_frzval [05:05] */
#define DSC_2_1_SM_CTRL0_VGA_FRZVAL_MASK                           0x0020
#define DSC_2_1_SM_CTRL0_VGA_FRZVAL_ALIGN                          0
#define DSC_2_1_SM_CTRL0_VGA_FRZVAL_BITS                           1
#define DSC_2_1_SM_CTRL0_VGA_FRZVAL_SHIFT                          5

/* dsc_2_1 :: sm_ctrl0 :: vga_frcfrz [04:04] */
#define DSC_2_1_SM_CTRL0_VGA_FRCFRZ_MASK                           0x0010
#define DSC_2_1_SM_CTRL0_VGA_FRCFRZ_ALIGN                          0
#define DSC_2_1_SM_CTRL0_VGA_FRCFRZ_BITS                           1
#define DSC_2_1_SM_CTRL0_VGA_FRCFRZ_SHIFT                          4

/* dsc_2_1 :: sm_ctrl0 :: dfe_frzval [03:03] */
#define DSC_2_1_SM_CTRL0_DFE_FRZVAL_MASK                           0x0008
#define DSC_2_1_SM_CTRL0_DFE_FRZVAL_ALIGN                          0
#define DSC_2_1_SM_CTRL0_DFE_FRZVAL_BITS                           1
#define DSC_2_1_SM_CTRL0_DFE_FRZVAL_SHIFT                          3

/* dsc_2_1 :: sm_ctrl0 :: dfe_frcfrz [02:02] */
#define DSC_2_1_SM_CTRL0_DFE_FRCFRZ_MASK                           0x0004
#define DSC_2_1_SM_CTRL0_DFE_FRCFRZ_ALIGN                          0
#define DSC_2_1_SM_CTRL0_DFE_FRCFRZ_BITS                           1
#define DSC_2_1_SM_CTRL0_DFE_FRCFRZ_SHIFT                          2

/* dsc_2_1 :: sm_ctrl0 :: dsc_clr_val [01:01] */
#define DSC_2_1_SM_CTRL0_DSC_CLR_VAL_MASK                          0x0002
#define DSC_2_1_SM_CTRL0_DSC_CLR_VAL_ALIGN                         0
#define DSC_2_1_SM_CTRL0_DSC_CLR_VAL_BITS                          1
#define DSC_2_1_SM_CTRL0_DSC_CLR_VAL_SHIFT                         1

/* dsc_2_1 :: sm_ctrl0 :: dsc_clr_frc [00:00] */
#define DSC_2_1_SM_CTRL0_DSC_CLR_FRC_MASK                          0x0001
#define DSC_2_1_SM_CTRL0_DSC_CLR_FRC_ALIGN                         0
#define DSC_2_1_SM_CTRL0_DSC_CLR_FRC_BITS                          1
#define DSC_2_1_SM_CTRL0_DSC_CLR_FRC_SHIFT                         0


/****************************************************************************
 * dsc_2_1 :: sm_ctrl1
 ***************************************************************************/
/* dsc_2_1 :: sm_ctrl1 :: fast_timer [15:15] */
#define DSC_2_1_SM_CTRL1_FAST_TIMER_MASK                           0x8000
#define DSC_2_1_SM_CTRL1_FAST_TIMER_ALIGN                          0
#define DSC_2_1_SM_CTRL1_FAST_TIMER_BITS                           1
#define DSC_2_1_SM_CTRL1_FAST_TIMER_SHIFT                          15

/* dsc_2_1 :: sm_ctrl1 :: acq2_timeout [14:10] */
#define DSC_2_1_SM_CTRL1_ACQ2_TIMEOUT_MASK                         0x7c00
#define DSC_2_1_SM_CTRL1_ACQ2_TIMEOUT_ALIGN                        0
#define DSC_2_1_SM_CTRL1_ACQ2_TIMEOUT_BITS                         5
#define DSC_2_1_SM_CTRL1_ACQ2_TIMEOUT_SHIFT                        10

/* dsc_2_1 :: sm_ctrl1 :: acq1_timeout [09:05] */
#define DSC_2_1_SM_CTRL1_ACQ1_TIMEOUT_MASK                         0x03e0
#define DSC_2_1_SM_CTRL1_ACQ1_TIMEOUT_ALIGN                        0
#define DSC_2_1_SM_CTRL1_ACQ1_TIMEOUT_BITS                         5
#define DSC_2_1_SM_CTRL1_ACQ1_TIMEOUT_SHIFT                        5

/* dsc_2_1 :: sm_ctrl1 :: acqcdr_timeout [04:00] */
#define DSC_2_1_SM_CTRL1_ACQCDR_TIMEOUT_MASK                       0x001f
#define DSC_2_1_SM_CTRL1_ACQCDR_TIMEOUT_ALIGN                      0
#define DSC_2_1_SM_CTRL1_ACQCDR_TIMEOUT_BITS                       5
#define DSC_2_1_SM_CTRL1_ACQCDR_TIMEOUT_SHIFT                      0


/****************************************************************************
 * dsc_2_1 :: sm_ctrl2
 ***************************************************************************/
/* dsc_2_1 :: sm_ctrl2 :: reserved_for_eco0 [15:15] */
#define DSC_2_1_SM_CTRL2_RESERVED_FOR_ECO0_MASK                    0x8000
#define DSC_2_1_SM_CTRL2_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC_2_1_SM_CTRL2_RESERVED_FOR_ECO0_BITS                    1
#define DSC_2_1_SM_CTRL2_RESERVED_FOR_ECO0_SHIFT                   15

/* dsc_2_1 :: sm_ctrl2 :: cdrbr_bwsel_prop_acqcdr [14:12] */
#define DSC_2_1_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_MASK              0x7000
#define DSC_2_1_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_ALIGN             0
#define DSC_2_1_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_BITS              3
#define DSC_2_1_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_SHIFT             12

/* dsc_2_1 :: sm_ctrl2 :: dfe_gain_acq2 [11:10] */
#define DSC_2_1_SM_CTRL2_DFE_GAIN_ACQ2_MASK                        0x0c00
#define DSC_2_1_SM_CTRL2_DFE_GAIN_ACQ2_ALIGN                       0
#define DSC_2_1_SM_CTRL2_DFE_GAIN_ACQ2_BITS                        2
#define DSC_2_1_SM_CTRL2_DFE_GAIN_ACQ2_SHIFT                       10

/* dsc_2_1 :: sm_ctrl2 :: dfe_gain_acq1 [09:08] */
#define DSC_2_1_SM_CTRL2_DFE_GAIN_ACQ1_MASK                        0x0300
#define DSC_2_1_SM_CTRL2_DFE_GAIN_ACQ1_ALIGN                       0
#define DSC_2_1_SM_CTRL2_DFE_GAIN_ACQ1_BITS                        2
#define DSC_2_1_SM_CTRL2_DFE_GAIN_ACQ1_SHIFT                       8

/* dsc_2_1 :: sm_ctrl2 :: vga_gain_acq2 [07:06] */
#define DSC_2_1_SM_CTRL2_VGA_GAIN_ACQ2_MASK                        0x00c0
#define DSC_2_1_SM_CTRL2_VGA_GAIN_ACQ2_ALIGN                       0
#define DSC_2_1_SM_CTRL2_VGA_GAIN_ACQ2_BITS                        2
#define DSC_2_1_SM_CTRL2_VGA_GAIN_ACQ2_SHIFT                       6

/* dsc_2_1 :: sm_ctrl2 :: vga_gain_acq1 [05:04] */
#define DSC_2_1_SM_CTRL2_VGA_GAIN_ACQ1_MASK                        0x0030
#define DSC_2_1_SM_CTRL2_VGA_GAIN_ACQ1_ALIGN                       0
#define DSC_2_1_SM_CTRL2_VGA_GAIN_ACQ1_BITS                        2
#define DSC_2_1_SM_CTRL2_VGA_GAIN_ACQ1_SHIFT                       4

/* dsc_2_1 :: sm_ctrl2 :: vga_gain_acqcdr [03:02] */
#define DSC_2_1_SM_CTRL2_VGA_GAIN_ACQCDR_MASK                      0x000c
#define DSC_2_1_SM_CTRL2_VGA_GAIN_ACQCDR_ALIGN                     0
#define DSC_2_1_SM_CTRL2_VGA_GAIN_ACQCDR_BITS                      2
#define DSC_2_1_SM_CTRL2_VGA_GAIN_ACQCDR_SHIFT                     2

/* dsc_2_1 :: sm_ctrl2 :: vga_gain_acqvga [01:00] */
#define DSC_2_1_SM_CTRL2_VGA_GAIN_ACQVGA_MASK                      0x0003
#define DSC_2_1_SM_CTRL2_VGA_GAIN_ACQVGA_ALIGN                     0
#define DSC_2_1_SM_CTRL2_VGA_GAIN_ACQVGA_BITS                      2
#define DSC_2_1_SM_CTRL2_VGA_GAIN_ACQVGA_SHIFT                     0


/****************************************************************************
 * dsc_2_1 :: sm_ctrl3
 ***************************************************************************/
/* dsc_2_1 :: sm_ctrl3 :: reserved_for_eco0 [15:12] */
#define DSC_2_1_SM_CTRL3_RESERVED_FOR_ECO0_MASK                    0xf000
#define DSC_2_1_SM_CTRL3_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC_2_1_SM_CTRL3_RESERVED_FOR_ECO0_BITS                    4
#define DSC_2_1_SM_CTRL3_RESERVED_FOR_ECO0_SHIFT                   12

/* dsc_2_1 :: sm_ctrl3 :: cdrbr_bwsel_integ_acq2 [11:10] */
#define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_MASK               0x0c00
#define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_ALIGN              0
#define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_BITS               2
#define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_SHIFT              10

/* dsc_2_1 :: sm_ctrl3 :: cdrbr_bwsel_integ_acq1 [09:08] */
#define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_MASK               0x0300
#define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_ALIGN              0
#define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_BITS               2
#define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_SHIFT              8

/* dsc_2_1 :: sm_ctrl3 :: cdrbr_bwsel_integ_acqcdr [07:06] */
#define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_MASK             0x00c0
#define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_ALIGN            0
#define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_BITS             2
#define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_SHIFT            6

/* dsc_2_1 :: sm_ctrl3 :: cdrbr_bwsel_prop_acq2 [05:03] */
#define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_MASK                0x0038
#define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_ALIGN               0
#define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_BITS                3
#define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_SHIFT               3

/* dsc_2_1 :: sm_ctrl3 :: cdrbr_bwsel_prop_acq1 [02:00] */
#define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_MASK                0x0007
#define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_ALIGN               0
#define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_BITS                3
#define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_SHIFT               0


/****************************************************************************
 * dsc_2_1 :: sm_ctrl4
 ***************************************************************************/
/* dsc_2_1 :: sm_ctrl4 :: cdros_bwsel_integ_acq1_2 [15:12] */
#define DSC_2_1_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_MASK             0xf000
#define DSC_2_1_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_ALIGN            0
#define DSC_2_1_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_BITS             4
#define DSC_2_1_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_SHIFT            12

/* dsc_2_1 :: sm_ctrl4 :: cdros_bwsel_integ_acqcdr [11:08] */
#define DSC_2_1_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_MASK             0x0f00
#define DSC_2_1_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_ALIGN            0
#define DSC_2_1_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_BITS             4
#define DSC_2_1_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_SHIFT            8

/* dsc_2_1 :: sm_ctrl4 :: cdros_bwsel_prop_acq1_2 [07:04] */
#define DSC_2_1_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_MASK              0x00f0
#define DSC_2_1_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_ALIGN             0
#define DSC_2_1_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_BITS              4
#define DSC_2_1_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_SHIFT             4

/* dsc_2_1 :: sm_ctrl4 :: cdros_bwsel_prop_acqcdr [03:00] */
#define DSC_2_1_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_MASK              0x000f
#define DSC_2_1_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_ALIGN             0
#define DSC_2_1_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_BITS              4
#define DSC_2_1_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_SHIFT             0


/****************************************************************************
 * dsc_2_1 :: dsc_status0
 ***************************************************************************/
/* dsc_2_1 :: dsc_status0 :: data_15_to_0 [15:00] */
#define DSC_2_1_DSC_STATUS0_DATA_15_TO_0_MASK                      0xffff
#define DSC_2_1_DSC_STATUS0_DATA_15_TO_0_ALIGN                     0
#define DSC_2_1_DSC_STATUS0_DATA_15_TO_0_BITS                      16
#define DSC_2_1_DSC_STATUS0_DATA_15_TO_0_SHIFT                     0


/****************************************************************************
 * dsc_2_1 :: dsc_status1
 ***************************************************************************/
/* dsc_2_1 :: dsc_status1 :: p1err_11_to_0 [15:04] */
#define DSC_2_1_DSC_STATUS1_P1ERR_11_TO_0_MASK                     0xfff0
#define DSC_2_1_DSC_STATUS1_P1ERR_11_TO_0_ALIGN                    0
#define DSC_2_1_DSC_STATUS1_P1ERR_11_TO_0_BITS                     12
#define DSC_2_1_DSC_STATUS1_P1ERR_11_TO_0_SHIFT                    4

/* dsc_2_1 :: dsc_status1 :: data_19_to_16 [03:00] */
#define DSC_2_1_DSC_STATUS1_DATA_19_TO_16_MASK                     0x000f
#define DSC_2_1_DSC_STATUS1_DATA_19_TO_16_ALIGN                    0
#define DSC_2_1_DSC_STATUS1_DATA_19_TO_16_BITS                     4
#define DSC_2_1_DSC_STATUS1_DATA_19_TO_16_SHIFT                    0


/****************************************************************************
 * dsc_2_1 :: dsc_status2
 ***************************************************************************/
/* dsc_2_1 :: dsc_status2 :: m1err_7_to_0 [15:08] */
#define DSC_2_1_DSC_STATUS2_M1ERR_7_TO_0_MASK                      0xff00
#define DSC_2_1_DSC_STATUS2_M1ERR_7_TO_0_ALIGN                     0
#define DSC_2_1_DSC_STATUS2_M1ERR_7_TO_0_BITS                      8
#define DSC_2_1_DSC_STATUS2_M1ERR_7_TO_0_SHIFT                     8

/* dsc_2_1 :: dsc_status2 :: p1err_19_to_12 [07:00] */
#define DSC_2_1_DSC_STATUS2_P1ERR_19_TO_12_MASK                    0x00ff
#define DSC_2_1_DSC_STATUS2_P1ERR_19_TO_12_ALIGN                   0
#define DSC_2_1_DSC_STATUS2_P1ERR_19_TO_12_BITS                    8
#define DSC_2_1_DSC_STATUS2_P1ERR_19_TO_12_SHIFT                   0


/****************************************************************************
 * dsc_2_1 :: dsc_status3
 ***************************************************************************/
/* dsc_2_1 :: dsc_status3 :: reserved_for_eco0 [15:12] */
#define DSC_2_1_DSC_STATUS3_RESERVED_FOR_ECO0_MASK                 0xf000
#define DSC_2_1_DSC_STATUS3_RESERVED_FOR_ECO0_ALIGN                0
#define DSC_2_1_DSC_STATUS3_RESERVED_FOR_ECO0_BITS                 4
#define DSC_2_1_DSC_STATUS3_RESERVED_FOR_ECO0_SHIFT                12

/* dsc_2_1 :: dsc_status3 :: m1err_19_to_8 [11:00] */
#define DSC_2_1_DSC_STATUS3_M1ERR_19_TO_8_MASK                     0x0fff
#define DSC_2_1_DSC_STATUS3_M1ERR_19_TO_8_ALIGN                    0
#define DSC_2_1_DSC_STATUS3_M1ERR_19_TO_8_BITS                     12
#define DSC_2_1_DSC_STATUS3_M1ERR_19_TO_8_SHIFT                    0


/****************************************************************************
 * dsc_2_1 :: dsc_ctrl0
 ***************************************************************************/
/* dsc_2_1 :: dsc_ctrl0 :: rxSeqStart [15:15] */
#define DSC_2_1_DSC_CTRL0_RXSEQSTART_MASK                          0x8000
#define DSC_2_1_DSC_CTRL0_RXSEQSTART_ALIGN                         0
#define DSC_2_1_DSC_CTRL0_RXSEQSTART_BITS                          1
#define DSC_2_1_DSC_CTRL0_RXSEQSTART_SHIFT                         15

/* dsc_2_1 :: dsc_ctrl0 :: forceRxSeqDone [14:14] */
#define DSC_2_1_DSC_CTRL0_FORCERXSEQDONE_MASK                      0x4000
#define DSC_2_1_DSC_CTRL0_FORCERXSEQDONE_ALIGN                     0
#define DSC_2_1_DSC_CTRL0_FORCERXSEQDONE_BITS                      1
#define DSC_2_1_DSC_CTRL0_FORCERXSEQDONE_SHIFT                     14

/* dsc_2_1 :: dsc_ctrl0 :: test_bus_sel [13:10] */
#define DSC_2_1_DSC_CTRL0_TEST_BUS_SEL_MASK                        0x3c00
#define DSC_2_1_DSC_CTRL0_TEST_BUS_SEL_ALIGN                       0
#define DSC_2_1_DSC_CTRL0_TEST_BUS_SEL_BITS                        4
#define DSC_2_1_DSC_CTRL0_TEST_BUS_SEL_SHIFT                       10
#define DSC_2_1_DSC_CTRL0_TEST_BUS_SEL_Off                         0
#define DSC_2_1_DSC_CTRL0_TEST_BUS_SEL_OSx2data                    1
#define DSC_2_1_DSC_CTRL0_TEST_BUS_SEL_OSx1data_m1                 2
#define DSC_2_1_DSC_CTRL0_TEST_BUS_SEL_BR_data_m1_p1               3
#define DSC_2_1_DSC_CTRL0_TEST_BUS_SEL_cdrPhaseVco                 4
#define DSC_2_1_DSC_CTRL0_TEST_BUS_SEL_cdrIntg                     6
#define DSC_2_1_DSC_CTRL0_TEST_BUS_SEL_cdrPhaseErr                 7
#define DSC_2_1_DSC_CTRL0_TEST_BUS_SEL_dfeAccEvenOdd               8
#define DSC_2_1_DSC_CTRL0_TEST_BUS_SEL_dfeVgasumDfe                9
#define DSC_2_1_DSC_CTRL0_TEST_BUS_SEL_dfeTrnsum                   10

/* dsc_2_1 :: dsc_ctrl0 :: rx_m1_thresh_zero [09:09] */
#define DSC_2_1_DSC_CTRL0_RX_M1_THRESH_ZERO_MASK                   0x0200
#define DSC_2_1_DSC_CTRL0_RX_M1_THRESH_ZERO_ALIGN                  0
#define DSC_2_1_DSC_CTRL0_RX_M1_THRESH_ZERO_BITS                   1
#define DSC_2_1_DSC_CTRL0_RX_M1_THRESH_ZERO_SHIFT                  9

/* dsc_2_1 :: dsc_ctrl0 :: rx_thresh_sel [08:07] */
#define DSC_2_1_DSC_CTRL0_RX_THRESH_SEL_MASK                       0x0180
#define DSC_2_1_DSC_CTRL0_RX_THRESH_SEL_ALIGN                      0
#define DSC_2_1_DSC_CTRL0_RX_THRESH_SEL_BITS                       2
#define DSC_2_1_DSC_CTRL0_RX_THRESH_SEL_SHIFT                      7

/* dsc_2_1 :: dsc_ctrl0 :: rx_pf_ctrl [06:04] */
#define DSC_2_1_DSC_CTRL0_RX_PF_CTRL_MASK                          0x0070
#define DSC_2_1_DSC_CTRL0_RX_PF_CTRL_ALIGN                         0
#define DSC_2_1_DSC_CTRL0_RX_PF_CTRL_BITS                          3
#define DSC_2_1_DSC_CTRL0_RX_PF_CTRL_SHIFT                         4

/* dsc_2_1 :: dsc_ctrl0 :: cdrbr_sel [03:03] */
#define DSC_2_1_DSC_CTRL0_CDRBR_SEL_MASK                           0x0008
#define DSC_2_1_DSC_CTRL0_CDRBR_SEL_ALIGN                          0
#define DSC_2_1_DSC_CTRL0_CDRBR_SEL_BITS                           1
#define DSC_2_1_DSC_CTRL0_CDRBR_SEL_SHIFT                          3

/* dsc_2_1 :: dsc_ctrl0 :: oscdr_force_mode_en [02:02] */
#define DSC_2_1_DSC_CTRL0_OSCDR_FORCE_MODE_EN_MASK                 0x0004
#define DSC_2_1_DSC_CTRL0_OSCDR_FORCE_MODE_EN_ALIGN                0
#define DSC_2_1_DSC_CTRL0_OSCDR_FORCE_MODE_EN_BITS                 1
#define DSC_2_1_DSC_CTRL0_OSCDR_FORCE_MODE_EN_SHIFT                2

/* dsc_2_1 :: dsc_ctrl0 :: oscdr_mode [01:00] */
#define DSC_2_1_DSC_CTRL0_OSCDR_MODE_MASK                          0x0003
#define DSC_2_1_DSC_CTRL0_OSCDR_MODE_ALIGN                         0
#define DSC_2_1_DSC_CTRL0_OSCDR_MODE_BITS                          2
#define DSC_2_1_DSC_CTRL0_OSCDR_MODE_SHIFT                         0


/****************************************************************************
 * dsc_2_1 :: dsc_ctrl1
 ***************************************************************************/
/* dsc_2_1 :: dsc_ctrl1 :: reserved_for_eco0 [15:15] */
#define DSC_2_1_DSC_CTRL1_RESERVED_FOR_ECO0_MASK                   0x8000
#define DSC_2_1_DSC_CTRL1_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC_2_1_DSC_CTRL1_RESERVED_FOR_ECO0_BITS                   1
#define DSC_2_1_DSC_CTRL1_RESERVED_FOR_ECO0_SHIFT                  15

/* dsc_2_1 :: dsc_ctrl1 :: p1_odd_ctrl [14:10] */
#define DSC_2_1_DSC_CTRL1_P1_ODD_CTRL_MASK                         0x7c00
#define DSC_2_1_DSC_CTRL1_P1_ODD_CTRL_ALIGN                        0
#define DSC_2_1_DSC_CTRL1_P1_ODD_CTRL_BITS                         5
#define DSC_2_1_DSC_CTRL1_P1_ODD_CTRL_SHIFT                        10

/* dsc_2_1 :: dsc_ctrl1 :: p1_evn_ctrl [09:05] */
#define DSC_2_1_DSC_CTRL1_P1_EVN_CTRL_MASK                         0x03e0
#define DSC_2_1_DSC_CTRL1_P1_EVN_CTRL_ALIGN                        0
#define DSC_2_1_DSC_CTRL1_P1_EVN_CTRL_BITS                         5
#define DSC_2_1_DSC_CTRL1_P1_EVN_CTRL_SHIFT                        5

/* dsc_2_1 :: dsc_ctrl1 :: d_odd_ctrl [04:00] */
#define DSC_2_1_DSC_CTRL1_D_ODD_CTRL_MASK                          0x001f
#define DSC_2_1_DSC_CTRL1_D_ODD_CTRL_ALIGN                         0
#define DSC_2_1_DSC_CTRL1_D_ODD_CTRL_BITS                          5
#define DSC_2_1_DSC_CTRL1_D_ODD_CTRL_SHIFT                         0


/****************************************************************************
 * dsc_2_1 :: dsc_ctrl2
 ***************************************************************************/
/* dsc_2_1 :: dsc_ctrl2 :: reserved_for_eco0 [15:15] */
#define DSC_2_1_DSC_CTRL2_RESERVED_FOR_ECO0_MASK                   0x8000
#define DSC_2_1_DSC_CTRL2_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC_2_1_DSC_CTRL2_RESERVED_FOR_ECO0_BITS                   1
#define DSC_2_1_DSC_CTRL2_RESERVED_FOR_ECO0_SHIFT                  15

/* dsc_2_1 :: dsc_ctrl2 :: d_evn_ctrl [14:10] */
#define DSC_2_1_DSC_CTRL2_D_EVN_CTRL_MASK                          0x7c00
#define DSC_2_1_DSC_CTRL2_D_EVN_CTRL_ALIGN                         0
#define DSC_2_1_DSC_CTRL2_D_EVN_CTRL_BITS                          5
#define DSC_2_1_DSC_CTRL2_D_EVN_CTRL_SHIFT                         10

/* dsc_2_1 :: dsc_ctrl2 :: m1_odd_ctrl [09:05] */
#define DSC_2_1_DSC_CTRL2_M1_ODD_CTRL_MASK                         0x03e0
#define DSC_2_1_DSC_CTRL2_M1_ODD_CTRL_ALIGN                        0
#define DSC_2_1_DSC_CTRL2_M1_ODD_CTRL_BITS                         5
#define DSC_2_1_DSC_CTRL2_M1_ODD_CTRL_SHIFT                        5

/* dsc_2_1 :: dsc_ctrl2 :: m1_evn_ctrl [04:00] */
#define DSC_2_1_DSC_CTRL2_M1_EVN_CTRL_MASK                         0x001f
#define DSC_2_1_DSC_CTRL2_M1_EVN_CTRL_ALIGN                        0
#define DSC_2_1_DSC_CTRL2_M1_EVN_CTRL_BITS                         5
#define DSC_2_1_DSC_CTRL2_M1_EVN_CTRL_SHIFT                        0


/****************************************************************************
 * XGXS16G_USER_dsc_2_2
 ***************************************************************************/
/****************************************************************************
 * dsc_2_2 :: sm_status0
 ***************************************************************************/
/* dsc_2_2 :: sm_status0 :: reserved_for_eco0 [15:04] */
#define DSC_2_2_SM_STATUS0_RESERVED_FOR_ECO0_MASK                  0xfff0
#define DSC_2_2_SM_STATUS0_RESERVED_FOR_ECO0_ALIGN                 0
#define DSC_2_2_SM_STATUS0_RESERVED_FOR_ECO0_BITS                  12
#define DSC_2_2_SM_STATUS0_RESERVED_FOR_ECO0_SHIFT                 4

/* dsc_2_2 :: sm_status0 :: dsc_state [03:00] */
#define DSC_2_2_SM_STATUS0_DSC_STATE_MASK                          0x000f
#define DSC_2_2_SM_STATUS0_DSC_STATE_ALIGN                         0
#define DSC_2_2_SM_STATUS0_DSC_STATE_BITS                          4
#define DSC_2_2_SM_STATUS0_DSC_STATE_SHIFT                         0


/****************************************************************************
 * dsc_2_2 :: sm_ctrl0
 ***************************************************************************/
/* dsc_2_2 :: sm_ctrl0 :: acqvga_timeout [15:11] */
#define DSC_2_2_SM_CTRL0_ACQVGA_TIMEOUT_MASK                       0xf800
#define DSC_2_2_SM_CTRL0_ACQVGA_TIMEOUT_ALIGN                      0
#define DSC_2_2_SM_CTRL0_ACQVGA_TIMEOUT_BITS                       5
#define DSC_2_2_SM_CTRL0_ACQVGA_TIMEOUT_SHIFT                      11

/* dsc_2_2 :: sm_ctrl0 :: tuning_sm_en [10:10] */
#define DSC_2_2_SM_CTRL0_TUNING_SM_EN_MASK                         0x0400
#define DSC_2_2_SM_CTRL0_TUNING_SM_EN_ALIGN                        0
#define DSC_2_2_SM_CTRL0_TUNING_SM_EN_BITS                         1
#define DSC_2_2_SM_CTRL0_TUNING_SM_EN_SHIFT                        10

/* dsc_2_2 :: sm_ctrl0 :: train2_req [09:09] */
#define DSC_2_2_SM_CTRL0_TRAIN2_REQ_MASK                           0x0200
#define DSC_2_2_SM_CTRL0_TRAIN2_REQ_ALIGN                          0
#define DSC_2_2_SM_CTRL0_TRAIN2_REQ_BITS                           1
#define DSC_2_2_SM_CTRL0_TRAIN2_REQ_SHIFT                          9

/* dsc_2_2 :: sm_ctrl0 :: train1_req [08:08] */
#define DSC_2_2_SM_CTRL0_TRAIN1_REQ_MASK                           0x0100
#define DSC_2_2_SM_CTRL0_TRAIN1_REQ_ALIGN                          0
#define DSC_2_2_SM_CTRL0_TRAIN1_REQ_BITS                           1
#define DSC_2_2_SM_CTRL0_TRAIN1_REQ_SHIFT                          8

/* dsc_2_2 :: sm_ctrl0 :: soft_ack [07:07] */
#define DSC_2_2_SM_CTRL0_SOFT_ACK_MASK                             0x0080
#define DSC_2_2_SM_CTRL0_SOFT_ACK_ALIGN                            0
#define DSC_2_2_SM_CTRL0_SOFT_ACK_BITS                             1
#define DSC_2_2_SM_CTRL0_SOFT_ACK_SHIFT                            7

/* dsc_2_2 :: sm_ctrl0 :: train_mode_en [06:06] */
#define DSC_2_2_SM_CTRL0_TRAIN_MODE_EN_MASK                        0x0040
#define DSC_2_2_SM_CTRL0_TRAIN_MODE_EN_ALIGN                       0
#define DSC_2_2_SM_CTRL0_TRAIN_MODE_EN_BITS                        1
#define DSC_2_2_SM_CTRL0_TRAIN_MODE_EN_SHIFT                       6

/* dsc_2_2 :: sm_ctrl0 :: vga_frzval [05:05] */
#define DSC_2_2_SM_CTRL0_VGA_FRZVAL_MASK                           0x0020
#define DSC_2_2_SM_CTRL0_VGA_FRZVAL_ALIGN                          0
#define DSC_2_2_SM_CTRL0_VGA_FRZVAL_BITS                           1
#define DSC_2_2_SM_CTRL0_VGA_FRZVAL_SHIFT                          5

/* dsc_2_2 :: sm_ctrl0 :: vga_frcfrz [04:04] */
#define DSC_2_2_SM_CTRL0_VGA_FRCFRZ_MASK                           0x0010
#define DSC_2_2_SM_CTRL0_VGA_FRCFRZ_ALIGN                          0
#define DSC_2_2_SM_CTRL0_VGA_FRCFRZ_BITS                           1
#define DSC_2_2_SM_CTRL0_VGA_FRCFRZ_SHIFT                          4

/* dsc_2_2 :: sm_ctrl0 :: dfe_frzval [03:03] */
#define DSC_2_2_SM_CTRL0_DFE_FRZVAL_MASK                           0x0008
#define DSC_2_2_SM_CTRL0_DFE_FRZVAL_ALIGN                          0
#define DSC_2_2_SM_CTRL0_DFE_FRZVAL_BITS                           1
#define DSC_2_2_SM_CTRL0_DFE_FRZVAL_SHIFT                          3

/* dsc_2_2 :: sm_ctrl0 :: dfe_frcfrz [02:02] */
#define DSC_2_2_SM_CTRL0_DFE_FRCFRZ_MASK                           0x0004
#define DSC_2_2_SM_CTRL0_DFE_FRCFRZ_ALIGN                          0
#define DSC_2_2_SM_CTRL0_DFE_FRCFRZ_BITS                           1
#define DSC_2_2_SM_CTRL0_DFE_FRCFRZ_SHIFT                          2

/* dsc_2_2 :: sm_ctrl0 :: dsc_clr_val [01:01] */
#define DSC_2_2_SM_CTRL0_DSC_CLR_VAL_MASK                          0x0002
#define DSC_2_2_SM_CTRL0_DSC_CLR_VAL_ALIGN                         0
#define DSC_2_2_SM_CTRL0_DSC_CLR_VAL_BITS                          1
#define DSC_2_2_SM_CTRL0_DSC_CLR_VAL_SHIFT                         1

/* dsc_2_2 :: sm_ctrl0 :: dsc_clr_frc [00:00] */
#define DSC_2_2_SM_CTRL0_DSC_CLR_FRC_MASK                          0x0001
#define DSC_2_2_SM_CTRL0_DSC_CLR_FRC_ALIGN                         0
#define DSC_2_2_SM_CTRL0_DSC_CLR_FRC_BITS                          1
#define DSC_2_2_SM_CTRL0_DSC_CLR_FRC_SHIFT                         0


/****************************************************************************
 * dsc_2_2 :: sm_ctrl1
 ***************************************************************************/
/* dsc_2_2 :: sm_ctrl1 :: fast_timer [15:15] */
#define DSC_2_2_SM_CTRL1_FAST_TIMER_MASK                           0x8000
#define DSC_2_2_SM_CTRL1_FAST_TIMER_ALIGN                          0
#define DSC_2_2_SM_CTRL1_FAST_TIMER_BITS                           1
#define DSC_2_2_SM_CTRL1_FAST_TIMER_SHIFT                          15

/* dsc_2_2 :: sm_ctrl1 :: acq2_timeout [14:10] */
#define DSC_2_2_SM_CTRL1_ACQ2_TIMEOUT_MASK                         0x7c00
#define DSC_2_2_SM_CTRL1_ACQ2_TIMEOUT_ALIGN                        0
#define DSC_2_2_SM_CTRL1_ACQ2_TIMEOUT_BITS                         5
#define DSC_2_2_SM_CTRL1_ACQ2_TIMEOUT_SHIFT                        10

/* dsc_2_2 :: sm_ctrl1 :: acq1_timeout [09:05] */
#define DSC_2_2_SM_CTRL1_ACQ1_TIMEOUT_MASK                         0x03e0
#define DSC_2_2_SM_CTRL1_ACQ1_TIMEOUT_ALIGN                        0
#define DSC_2_2_SM_CTRL1_ACQ1_TIMEOUT_BITS                         5
#define DSC_2_2_SM_CTRL1_ACQ1_TIMEOUT_SHIFT                        5

/* dsc_2_2 :: sm_ctrl1 :: acqcdr_timeout [04:00] */
#define DSC_2_2_SM_CTRL1_ACQCDR_TIMEOUT_MASK                       0x001f
#define DSC_2_2_SM_CTRL1_ACQCDR_TIMEOUT_ALIGN                      0
#define DSC_2_2_SM_CTRL1_ACQCDR_TIMEOUT_BITS                       5
#define DSC_2_2_SM_CTRL1_ACQCDR_TIMEOUT_SHIFT                      0


/****************************************************************************
 * dsc_2_2 :: sm_ctrl2
 ***************************************************************************/
/* dsc_2_2 :: sm_ctrl2 :: reserved_for_eco0 [15:15] */
#define DSC_2_2_SM_CTRL2_RESERVED_FOR_ECO0_MASK                    0x8000
#define DSC_2_2_SM_CTRL2_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC_2_2_SM_CTRL2_RESERVED_FOR_ECO0_BITS                    1
#define DSC_2_2_SM_CTRL2_RESERVED_FOR_ECO0_SHIFT                   15

/* dsc_2_2 :: sm_ctrl2 :: cdrbr_bwsel_prop_acqcdr [14:12] */
#define DSC_2_2_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_MASK              0x7000
#define DSC_2_2_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_ALIGN             0
#define DSC_2_2_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_BITS              3
#define DSC_2_2_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_SHIFT             12

/* dsc_2_2 :: sm_ctrl2 :: dfe_gain_acq2 [11:10] */
#define DSC_2_2_SM_CTRL2_DFE_GAIN_ACQ2_MASK                        0x0c00
#define DSC_2_2_SM_CTRL2_DFE_GAIN_ACQ2_ALIGN                       0
#define DSC_2_2_SM_CTRL2_DFE_GAIN_ACQ2_BITS                        2
#define DSC_2_2_SM_CTRL2_DFE_GAIN_ACQ2_SHIFT                       10

/* dsc_2_2 :: sm_ctrl2 :: dfe_gain_acq1 [09:08] */
#define DSC_2_2_SM_CTRL2_DFE_GAIN_ACQ1_MASK                        0x0300
#define DSC_2_2_SM_CTRL2_DFE_GAIN_ACQ1_ALIGN                       0
#define DSC_2_2_SM_CTRL2_DFE_GAIN_ACQ1_BITS                        2
#define DSC_2_2_SM_CTRL2_DFE_GAIN_ACQ1_SHIFT                       8

/* dsc_2_2 :: sm_ctrl2 :: vga_gain_acq2 [07:06] */
#define DSC_2_2_SM_CTRL2_VGA_GAIN_ACQ2_MASK                        0x00c0
#define DSC_2_2_SM_CTRL2_VGA_GAIN_ACQ2_ALIGN                       0
#define DSC_2_2_SM_CTRL2_VGA_GAIN_ACQ2_BITS                        2
#define DSC_2_2_SM_CTRL2_VGA_GAIN_ACQ2_SHIFT                       6

/* dsc_2_2 :: sm_ctrl2 :: vga_gain_acq1 [05:04] */
#define DSC_2_2_SM_CTRL2_VGA_GAIN_ACQ1_MASK                        0x0030
#define DSC_2_2_SM_CTRL2_VGA_GAIN_ACQ1_ALIGN                       0
#define DSC_2_2_SM_CTRL2_VGA_GAIN_ACQ1_BITS                        2
#define DSC_2_2_SM_CTRL2_VGA_GAIN_ACQ1_SHIFT                       4

/* dsc_2_2 :: sm_ctrl2 :: vga_gain_acqcdr [03:02] */
#define DSC_2_2_SM_CTRL2_VGA_GAIN_ACQCDR_MASK                      0x000c
#define DSC_2_2_SM_CTRL2_VGA_GAIN_ACQCDR_ALIGN                     0
#define DSC_2_2_SM_CTRL2_VGA_GAIN_ACQCDR_BITS                      2
#define DSC_2_2_SM_CTRL2_VGA_GAIN_ACQCDR_SHIFT                     2

/* dsc_2_2 :: sm_ctrl2 :: vga_gain_acqvga [01:00] */
#define DSC_2_2_SM_CTRL2_VGA_GAIN_ACQVGA_MASK                      0x0003
#define DSC_2_2_SM_CTRL2_VGA_GAIN_ACQVGA_ALIGN                     0
#define DSC_2_2_SM_CTRL2_VGA_GAIN_ACQVGA_BITS                      2
#define DSC_2_2_SM_CTRL2_VGA_GAIN_ACQVGA_SHIFT                     0


/****************************************************************************
 * dsc_2_2 :: sm_ctrl3
 ***************************************************************************/
/* dsc_2_2 :: sm_ctrl3 :: reserved_for_eco0 [15:12] */
#define DSC_2_2_SM_CTRL3_RESERVED_FOR_ECO0_MASK                    0xf000
#define DSC_2_2_SM_CTRL3_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC_2_2_SM_CTRL3_RESERVED_FOR_ECO0_BITS                    4
#define DSC_2_2_SM_CTRL3_RESERVED_FOR_ECO0_SHIFT                   12

/* dsc_2_2 :: sm_ctrl3 :: cdrbr_bwsel_integ_acq2 [11:10] */
#define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_MASK               0x0c00
#define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_ALIGN              0
#define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_BITS               2
#define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_SHIFT              10

/* dsc_2_2 :: sm_ctrl3 :: cdrbr_bwsel_integ_acq1 [09:08] */
#define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_MASK               0x0300
#define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_ALIGN              0
#define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_BITS               2
#define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_SHIFT              8

/* dsc_2_2 :: sm_ctrl3 :: cdrbr_bwsel_integ_acqcdr [07:06] */
#define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_MASK             0x00c0
#define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_ALIGN            0
#define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_BITS             2
#define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_SHIFT            6

/* dsc_2_2 :: sm_ctrl3 :: cdrbr_bwsel_prop_acq2 [05:03] */
#define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_MASK                0x0038
#define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_ALIGN               0
#define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_BITS                3
#define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_SHIFT               3

/* dsc_2_2 :: sm_ctrl3 :: cdrbr_bwsel_prop_acq1 [02:00] */
#define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_MASK                0x0007
#define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_ALIGN               0
#define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_BITS                3
#define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_SHIFT               0


/****************************************************************************
 * dsc_2_2 :: sm_ctrl4
 ***************************************************************************/
/* dsc_2_2 :: sm_ctrl4 :: cdros_bwsel_integ_acq1_2 [15:12] */
#define DSC_2_2_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_MASK             0xf000
#define DSC_2_2_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_ALIGN            0
#define DSC_2_2_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_BITS             4
#define DSC_2_2_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_SHIFT            12

/* dsc_2_2 :: sm_ctrl4 :: cdros_bwsel_integ_acqcdr [11:08] */
#define DSC_2_2_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_MASK             0x0f00
#define DSC_2_2_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_ALIGN            0
#define DSC_2_2_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_BITS             4
#define DSC_2_2_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_SHIFT            8

/* dsc_2_2 :: sm_ctrl4 :: cdros_bwsel_prop_acq1_2 [07:04] */
#define DSC_2_2_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_MASK              0x00f0
#define DSC_2_2_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_ALIGN             0
#define DSC_2_2_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_BITS              4
#define DSC_2_2_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_SHIFT             4

/* dsc_2_2 :: sm_ctrl4 :: cdros_bwsel_prop_acqcdr [03:00] */
#define DSC_2_2_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_MASK              0x000f
#define DSC_2_2_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_ALIGN             0
#define DSC_2_2_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_BITS              4
#define DSC_2_2_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_SHIFT             0


/****************************************************************************
 * dsc_2_2 :: dsc_status0
 ***************************************************************************/
/* dsc_2_2 :: dsc_status0 :: data_15_to_0 [15:00] */
#define DSC_2_2_DSC_STATUS0_DATA_15_TO_0_MASK                      0xffff
#define DSC_2_2_DSC_STATUS0_DATA_15_TO_0_ALIGN                     0
#define DSC_2_2_DSC_STATUS0_DATA_15_TO_0_BITS                      16
#define DSC_2_2_DSC_STATUS0_DATA_15_TO_0_SHIFT                     0


/****************************************************************************
 * dsc_2_2 :: dsc_status1
 ***************************************************************************/
/* dsc_2_2 :: dsc_status1 :: p1err_11_to_0 [15:04] */
#define DSC_2_2_DSC_STATUS1_P1ERR_11_TO_0_MASK                     0xfff0
#define DSC_2_2_DSC_STATUS1_P1ERR_11_TO_0_ALIGN                    0
#define DSC_2_2_DSC_STATUS1_P1ERR_11_TO_0_BITS                     12
#define DSC_2_2_DSC_STATUS1_P1ERR_11_TO_0_SHIFT                    4

/* dsc_2_2 :: dsc_status1 :: data_19_to_16 [03:00] */
#define DSC_2_2_DSC_STATUS1_DATA_19_TO_16_MASK                     0x000f
#define DSC_2_2_DSC_STATUS1_DATA_19_TO_16_ALIGN                    0
#define DSC_2_2_DSC_STATUS1_DATA_19_TO_16_BITS                     4
#define DSC_2_2_DSC_STATUS1_DATA_19_TO_16_SHIFT                    0


/****************************************************************************
 * dsc_2_2 :: dsc_status2
 ***************************************************************************/
/* dsc_2_2 :: dsc_status2 :: m1err_7_to_0 [15:08] */
#define DSC_2_2_DSC_STATUS2_M1ERR_7_TO_0_MASK                      0xff00
#define DSC_2_2_DSC_STATUS2_M1ERR_7_TO_0_ALIGN                     0
#define DSC_2_2_DSC_STATUS2_M1ERR_7_TO_0_BITS                      8
#define DSC_2_2_DSC_STATUS2_M1ERR_7_TO_0_SHIFT                     8

/* dsc_2_2 :: dsc_status2 :: p1err_19_to_12 [07:00] */
#define DSC_2_2_DSC_STATUS2_P1ERR_19_TO_12_MASK                    0x00ff
#define DSC_2_2_DSC_STATUS2_P1ERR_19_TO_12_ALIGN                   0
#define DSC_2_2_DSC_STATUS2_P1ERR_19_TO_12_BITS                    8
#define DSC_2_2_DSC_STATUS2_P1ERR_19_TO_12_SHIFT                   0


/****************************************************************************
 * dsc_2_2 :: dsc_status3
 ***************************************************************************/
/* dsc_2_2 :: dsc_status3 :: reserved_for_eco0 [15:12] */
#define DSC_2_2_DSC_STATUS3_RESERVED_FOR_ECO0_MASK                 0xf000
#define DSC_2_2_DSC_STATUS3_RESERVED_FOR_ECO0_ALIGN                0
#define DSC_2_2_DSC_STATUS3_RESERVED_FOR_ECO0_BITS                 4
#define DSC_2_2_DSC_STATUS3_RESERVED_FOR_ECO0_SHIFT                12

/* dsc_2_2 :: dsc_status3 :: m1err_19_to_8 [11:00] */
#define DSC_2_2_DSC_STATUS3_M1ERR_19_TO_8_MASK                     0x0fff
#define DSC_2_2_DSC_STATUS3_M1ERR_19_TO_8_ALIGN                    0
#define DSC_2_2_DSC_STATUS3_M1ERR_19_TO_8_BITS                     12
#define DSC_2_2_DSC_STATUS3_M1ERR_19_TO_8_SHIFT                    0


/****************************************************************************
 * dsc_2_2 :: dsc_ctrl0
 ***************************************************************************/
/* dsc_2_2 :: dsc_ctrl0 :: rxSeqStart [15:15] */
#define DSC_2_2_DSC_CTRL0_RXSEQSTART_MASK                          0x8000
#define DSC_2_2_DSC_CTRL0_RXSEQSTART_ALIGN                         0
#define DSC_2_2_DSC_CTRL0_RXSEQSTART_BITS                          1
#define DSC_2_2_DSC_CTRL0_RXSEQSTART_SHIFT                         15

/* dsc_2_2 :: dsc_ctrl0 :: forceRxSeqDone [14:14] */
#define DSC_2_2_DSC_CTRL0_FORCERXSEQDONE_MASK                      0x4000
#define DSC_2_2_DSC_CTRL0_FORCERXSEQDONE_ALIGN                     0
#define DSC_2_2_DSC_CTRL0_FORCERXSEQDONE_BITS                      1
#define DSC_2_2_DSC_CTRL0_FORCERXSEQDONE_SHIFT                     14

/* dsc_2_2 :: dsc_ctrl0 :: test_bus_sel [13:10] */
#define DSC_2_2_DSC_CTRL0_TEST_BUS_SEL_MASK                        0x3c00
#define DSC_2_2_DSC_CTRL0_TEST_BUS_SEL_ALIGN                       0
#define DSC_2_2_DSC_CTRL0_TEST_BUS_SEL_BITS                        4
#define DSC_2_2_DSC_CTRL0_TEST_BUS_SEL_SHIFT                       10
#define DSC_2_2_DSC_CTRL0_TEST_BUS_SEL_Off                         0
#define DSC_2_2_DSC_CTRL0_TEST_BUS_SEL_OSx2data                    1
#define DSC_2_2_DSC_CTRL0_TEST_BUS_SEL_OSx1data_m1                 2
#define DSC_2_2_DSC_CTRL0_TEST_BUS_SEL_BR_data_m1_p1               3
#define DSC_2_2_DSC_CTRL0_TEST_BUS_SEL_cdrPhaseVco                 4
#define DSC_2_2_DSC_CTRL0_TEST_BUS_SEL_cdrIntg                     6
#define DSC_2_2_DSC_CTRL0_TEST_BUS_SEL_cdrPhaseErr                 7
#define DSC_2_2_DSC_CTRL0_TEST_BUS_SEL_dfeAccEvenOdd               8
#define DSC_2_2_DSC_CTRL0_TEST_BUS_SEL_dfeVgasumDfe                9
#define DSC_2_2_DSC_CTRL0_TEST_BUS_SEL_dfeTrnsum                   10

/* dsc_2_2 :: dsc_ctrl0 :: rx_m1_thresh_zero [09:09] */
#define DSC_2_2_DSC_CTRL0_RX_M1_THRESH_ZERO_MASK                   0x0200
#define DSC_2_2_DSC_CTRL0_RX_M1_THRESH_ZERO_ALIGN                  0
#define DSC_2_2_DSC_CTRL0_RX_M1_THRESH_ZERO_BITS                   1
#define DSC_2_2_DSC_CTRL0_RX_M1_THRESH_ZERO_SHIFT                  9

/* dsc_2_2 :: dsc_ctrl0 :: rx_thresh_sel [08:07] */
#define DSC_2_2_DSC_CTRL0_RX_THRESH_SEL_MASK                       0x0180
#define DSC_2_2_DSC_CTRL0_RX_THRESH_SEL_ALIGN                      0
#define DSC_2_2_DSC_CTRL0_RX_THRESH_SEL_BITS                       2
#define DSC_2_2_DSC_CTRL0_RX_THRESH_SEL_SHIFT                      7

/* dsc_2_2 :: dsc_ctrl0 :: rx_pf_ctrl [06:04] */
#define DSC_2_2_DSC_CTRL0_RX_PF_CTRL_MASK                          0x0070
#define DSC_2_2_DSC_CTRL0_RX_PF_CTRL_ALIGN                         0
#define DSC_2_2_DSC_CTRL0_RX_PF_CTRL_BITS                          3
#define DSC_2_2_DSC_CTRL0_RX_PF_CTRL_SHIFT                         4

/* dsc_2_2 :: dsc_ctrl0 :: cdrbr_sel [03:03] */
#define DSC_2_2_DSC_CTRL0_CDRBR_SEL_MASK                           0x0008
#define DSC_2_2_DSC_CTRL0_CDRBR_SEL_ALIGN                          0
#define DSC_2_2_DSC_CTRL0_CDRBR_SEL_BITS                           1
#define DSC_2_2_DSC_CTRL0_CDRBR_SEL_SHIFT                          3

/* dsc_2_2 :: dsc_ctrl0 :: oscdr_force_mode_en [02:02] */
#define DSC_2_2_DSC_CTRL0_OSCDR_FORCE_MODE_EN_MASK                 0x0004
#define DSC_2_2_DSC_CTRL0_OSCDR_FORCE_MODE_EN_ALIGN                0
#define DSC_2_2_DSC_CTRL0_OSCDR_FORCE_MODE_EN_BITS                 1
#define DSC_2_2_DSC_CTRL0_OSCDR_FORCE_MODE_EN_SHIFT                2

/* dsc_2_2 :: dsc_ctrl0 :: oscdr_mode [01:00] */
#define DSC_2_2_DSC_CTRL0_OSCDR_MODE_MASK                          0x0003
#define DSC_2_2_DSC_CTRL0_OSCDR_MODE_ALIGN                         0
#define DSC_2_2_DSC_CTRL0_OSCDR_MODE_BITS                          2
#define DSC_2_2_DSC_CTRL0_OSCDR_MODE_SHIFT                         0


/****************************************************************************
 * dsc_2_2 :: dsc_ctrl1
 ***************************************************************************/
/* dsc_2_2 :: dsc_ctrl1 :: reserved_for_eco0 [15:15] */
#define DSC_2_2_DSC_CTRL1_RESERVED_FOR_ECO0_MASK                   0x8000
#define DSC_2_2_DSC_CTRL1_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC_2_2_DSC_CTRL1_RESERVED_FOR_ECO0_BITS                   1
#define DSC_2_2_DSC_CTRL1_RESERVED_FOR_ECO0_SHIFT                  15

/* dsc_2_2 :: dsc_ctrl1 :: p1_odd_ctrl [14:10] */
#define DSC_2_2_DSC_CTRL1_P1_ODD_CTRL_MASK                         0x7c00
#define DSC_2_2_DSC_CTRL1_P1_ODD_CTRL_ALIGN                        0
#define DSC_2_2_DSC_CTRL1_P1_ODD_CTRL_BITS                         5
#define DSC_2_2_DSC_CTRL1_P1_ODD_CTRL_SHIFT                        10

/* dsc_2_2 :: dsc_ctrl1 :: p1_evn_ctrl [09:05] */
#define DSC_2_2_DSC_CTRL1_P1_EVN_CTRL_MASK                         0x03e0
#define DSC_2_2_DSC_CTRL1_P1_EVN_CTRL_ALIGN                        0
#define DSC_2_2_DSC_CTRL1_P1_EVN_CTRL_BITS                         5
#define DSC_2_2_DSC_CTRL1_P1_EVN_CTRL_SHIFT                        5

/* dsc_2_2 :: dsc_ctrl1 :: d_odd_ctrl [04:00] */
#define DSC_2_2_DSC_CTRL1_D_ODD_CTRL_MASK                          0x001f
#define DSC_2_2_DSC_CTRL1_D_ODD_CTRL_ALIGN                         0
#define DSC_2_2_DSC_CTRL1_D_ODD_CTRL_BITS                          5
#define DSC_2_2_DSC_CTRL1_D_ODD_CTRL_SHIFT                         0


/****************************************************************************
 * dsc_2_2 :: dsc_ctrl2
 ***************************************************************************/
/* dsc_2_2 :: dsc_ctrl2 :: reserved_for_eco0 [15:15] */
#define DSC_2_2_DSC_CTRL2_RESERVED_FOR_ECO0_MASK                   0x8000
#define DSC_2_2_DSC_CTRL2_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC_2_2_DSC_CTRL2_RESERVED_FOR_ECO0_BITS                   1
#define DSC_2_2_DSC_CTRL2_RESERVED_FOR_ECO0_SHIFT                  15

/* dsc_2_2 :: dsc_ctrl2 :: d_evn_ctrl [14:10] */
#define DSC_2_2_DSC_CTRL2_D_EVN_CTRL_MASK                          0x7c00
#define DSC_2_2_DSC_CTRL2_D_EVN_CTRL_ALIGN                         0
#define DSC_2_2_DSC_CTRL2_D_EVN_CTRL_BITS                          5
#define DSC_2_2_DSC_CTRL2_D_EVN_CTRL_SHIFT                         10

/* dsc_2_2 :: dsc_ctrl2 :: m1_odd_ctrl [09:05] */
#define DSC_2_2_DSC_CTRL2_M1_ODD_CTRL_MASK                         0x03e0
#define DSC_2_2_DSC_CTRL2_M1_ODD_CTRL_ALIGN                        0
#define DSC_2_2_DSC_CTRL2_M1_ODD_CTRL_BITS                         5
#define DSC_2_2_DSC_CTRL2_M1_ODD_CTRL_SHIFT                        5

/* dsc_2_2 :: dsc_ctrl2 :: m1_evn_ctrl [04:00] */
#define DSC_2_2_DSC_CTRL2_M1_EVN_CTRL_MASK                         0x001f
#define DSC_2_2_DSC_CTRL2_M1_EVN_CTRL_ALIGN                        0
#define DSC_2_2_DSC_CTRL2_M1_EVN_CTRL_BITS                         5
#define DSC_2_2_DSC_CTRL2_M1_EVN_CTRL_SHIFT                        0


/****************************************************************************
 * XGXS16G_USER_dsc_2_3
 ***************************************************************************/
/****************************************************************************
 * dsc_2_3 :: sm_status0
 ***************************************************************************/
/* dsc_2_3 :: sm_status0 :: reserved_for_eco0 [15:04] */
#define DSC_2_3_SM_STATUS0_RESERVED_FOR_ECO0_MASK                  0xfff0
#define DSC_2_3_SM_STATUS0_RESERVED_FOR_ECO0_ALIGN                 0
#define DSC_2_3_SM_STATUS0_RESERVED_FOR_ECO0_BITS                  12
#define DSC_2_3_SM_STATUS0_RESERVED_FOR_ECO0_SHIFT                 4

/* dsc_2_3 :: sm_status0 :: dsc_state [03:00] */
#define DSC_2_3_SM_STATUS0_DSC_STATE_MASK                          0x000f
#define DSC_2_3_SM_STATUS0_DSC_STATE_ALIGN                         0
#define DSC_2_3_SM_STATUS0_DSC_STATE_BITS                          4
#define DSC_2_3_SM_STATUS0_DSC_STATE_SHIFT                         0


/****************************************************************************
 * dsc_2_3 :: sm_ctrl0
 ***************************************************************************/
/* dsc_2_3 :: sm_ctrl0 :: acqvga_timeout [15:11] */
#define DSC_2_3_SM_CTRL0_ACQVGA_TIMEOUT_MASK                       0xf800
#define DSC_2_3_SM_CTRL0_ACQVGA_TIMEOUT_ALIGN                      0
#define DSC_2_3_SM_CTRL0_ACQVGA_TIMEOUT_BITS                       5
#define DSC_2_3_SM_CTRL0_ACQVGA_TIMEOUT_SHIFT                      11

/* dsc_2_3 :: sm_ctrl0 :: tuning_sm_en [10:10] */
#define DSC_2_3_SM_CTRL0_TUNING_SM_EN_MASK                         0x0400
#define DSC_2_3_SM_CTRL0_TUNING_SM_EN_ALIGN                        0
#define DSC_2_3_SM_CTRL0_TUNING_SM_EN_BITS                         1
#define DSC_2_3_SM_CTRL0_TUNING_SM_EN_SHIFT                        10

/* dsc_2_3 :: sm_ctrl0 :: train2_req [09:09] */
#define DSC_2_3_SM_CTRL0_TRAIN2_REQ_MASK                           0x0200
#define DSC_2_3_SM_CTRL0_TRAIN2_REQ_ALIGN                          0
#define DSC_2_3_SM_CTRL0_TRAIN2_REQ_BITS                           1
#define DSC_2_3_SM_CTRL0_TRAIN2_REQ_SHIFT                          9

/* dsc_2_3 :: sm_ctrl0 :: train1_req [08:08] */
#define DSC_2_3_SM_CTRL0_TRAIN1_REQ_MASK                           0x0100
#define DSC_2_3_SM_CTRL0_TRAIN1_REQ_ALIGN                          0
#define DSC_2_3_SM_CTRL0_TRAIN1_REQ_BITS                           1
#define DSC_2_3_SM_CTRL0_TRAIN1_REQ_SHIFT                          8

/* dsc_2_3 :: sm_ctrl0 :: soft_ack [07:07] */
#define DSC_2_3_SM_CTRL0_SOFT_ACK_MASK                             0x0080
#define DSC_2_3_SM_CTRL0_SOFT_ACK_ALIGN                            0
#define DSC_2_3_SM_CTRL0_SOFT_ACK_BITS                             1
#define DSC_2_3_SM_CTRL0_SOFT_ACK_SHIFT                            7

/* dsc_2_3 :: sm_ctrl0 :: train_mode_en [06:06] */
#define DSC_2_3_SM_CTRL0_TRAIN_MODE_EN_MASK                        0x0040
#define DSC_2_3_SM_CTRL0_TRAIN_MODE_EN_ALIGN                       0
#define DSC_2_3_SM_CTRL0_TRAIN_MODE_EN_BITS                        1
#define DSC_2_3_SM_CTRL0_TRAIN_MODE_EN_SHIFT                       6

/* dsc_2_3 :: sm_ctrl0 :: vga_frzval [05:05] */
#define DSC_2_3_SM_CTRL0_VGA_FRZVAL_MASK                           0x0020
#define DSC_2_3_SM_CTRL0_VGA_FRZVAL_ALIGN                          0
#define DSC_2_3_SM_CTRL0_VGA_FRZVAL_BITS                           1
#define DSC_2_3_SM_CTRL0_VGA_FRZVAL_SHIFT                          5

/* dsc_2_3 :: sm_ctrl0 :: vga_frcfrz [04:04] */
#define DSC_2_3_SM_CTRL0_VGA_FRCFRZ_MASK                           0x0010
#define DSC_2_3_SM_CTRL0_VGA_FRCFRZ_ALIGN                          0
#define DSC_2_3_SM_CTRL0_VGA_FRCFRZ_BITS                           1
#define DSC_2_3_SM_CTRL0_VGA_FRCFRZ_SHIFT                          4

/* dsc_2_3 :: sm_ctrl0 :: dfe_frzval [03:03] */
#define DSC_2_3_SM_CTRL0_DFE_FRZVAL_MASK                           0x0008
#define DSC_2_3_SM_CTRL0_DFE_FRZVAL_ALIGN                          0
#define DSC_2_3_SM_CTRL0_DFE_FRZVAL_BITS                           1
#define DSC_2_3_SM_CTRL0_DFE_FRZVAL_SHIFT                          3

/* dsc_2_3 :: sm_ctrl0 :: dfe_frcfrz [02:02] */
#define DSC_2_3_SM_CTRL0_DFE_FRCFRZ_MASK                           0x0004
#define DSC_2_3_SM_CTRL0_DFE_FRCFRZ_ALIGN                          0
#define DSC_2_3_SM_CTRL0_DFE_FRCFRZ_BITS                           1
#define DSC_2_3_SM_CTRL0_DFE_FRCFRZ_SHIFT                          2

/* dsc_2_3 :: sm_ctrl0 :: dsc_clr_val [01:01] */
#define DSC_2_3_SM_CTRL0_DSC_CLR_VAL_MASK                          0x0002
#define DSC_2_3_SM_CTRL0_DSC_CLR_VAL_ALIGN                         0
#define DSC_2_3_SM_CTRL0_DSC_CLR_VAL_BITS                          1
#define DSC_2_3_SM_CTRL0_DSC_CLR_VAL_SHIFT                         1

/* dsc_2_3 :: sm_ctrl0 :: dsc_clr_frc [00:00] */
#define DSC_2_3_SM_CTRL0_DSC_CLR_FRC_MASK                          0x0001
#define DSC_2_3_SM_CTRL0_DSC_CLR_FRC_ALIGN                         0
#define DSC_2_3_SM_CTRL0_DSC_CLR_FRC_BITS                          1
#define DSC_2_3_SM_CTRL0_DSC_CLR_FRC_SHIFT                         0


/****************************************************************************
 * dsc_2_3 :: sm_ctrl1
 ***************************************************************************/
/* dsc_2_3 :: sm_ctrl1 :: fast_timer [15:15] */
#define DSC_2_3_SM_CTRL1_FAST_TIMER_MASK                           0x8000
#define DSC_2_3_SM_CTRL1_FAST_TIMER_ALIGN                          0
#define DSC_2_3_SM_CTRL1_FAST_TIMER_BITS                           1
#define DSC_2_3_SM_CTRL1_FAST_TIMER_SHIFT                          15

/* dsc_2_3 :: sm_ctrl1 :: acq2_timeout [14:10] */
#define DSC_2_3_SM_CTRL1_ACQ2_TIMEOUT_MASK                         0x7c00
#define DSC_2_3_SM_CTRL1_ACQ2_TIMEOUT_ALIGN                        0
#define DSC_2_3_SM_CTRL1_ACQ2_TIMEOUT_BITS                         5
#define DSC_2_3_SM_CTRL1_ACQ2_TIMEOUT_SHIFT                        10

/* dsc_2_3 :: sm_ctrl1 :: acq1_timeout [09:05] */
#define DSC_2_3_SM_CTRL1_ACQ1_TIMEOUT_MASK                         0x03e0
#define DSC_2_3_SM_CTRL1_ACQ1_TIMEOUT_ALIGN                        0
#define DSC_2_3_SM_CTRL1_ACQ1_TIMEOUT_BITS                         5
#define DSC_2_3_SM_CTRL1_ACQ1_TIMEOUT_SHIFT                        5

/* dsc_2_3 :: sm_ctrl1 :: acqcdr_timeout [04:00] */
#define DSC_2_3_SM_CTRL1_ACQCDR_TIMEOUT_MASK                       0x001f
#define DSC_2_3_SM_CTRL1_ACQCDR_TIMEOUT_ALIGN                      0
#define DSC_2_3_SM_CTRL1_ACQCDR_TIMEOUT_BITS                       5
#define DSC_2_3_SM_CTRL1_ACQCDR_TIMEOUT_SHIFT                      0


/****************************************************************************
 * dsc_2_3 :: sm_ctrl2
 ***************************************************************************/
/* dsc_2_3 :: sm_ctrl2 :: reserved_for_eco0 [15:15] */
#define DSC_2_3_SM_CTRL2_RESERVED_FOR_ECO0_MASK                    0x8000
#define DSC_2_3_SM_CTRL2_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC_2_3_SM_CTRL2_RESERVED_FOR_ECO0_BITS                    1
#define DSC_2_3_SM_CTRL2_RESERVED_FOR_ECO0_SHIFT                   15

/* dsc_2_3 :: sm_ctrl2 :: cdrbr_bwsel_prop_acqcdr [14:12] */
#define DSC_2_3_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_MASK              0x7000
#define DSC_2_3_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_ALIGN             0
#define DSC_2_3_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_BITS              3
#define DSC_2_3_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_SHIFT             12

/* dsc_2_3 :: sm_ctrl2 :: dfe_gain_acq2 [11:10] */
#define DSC_2_3_SM_CTRL2_DFE_GAIN_ACQ2_MASK                        0x0c00
#define DSC_2_3_SM_CTRL2_DFE_GAIN_ACQ2_ALIGN                       0
#define DSC_2_3_SM_CTRL2_DFE_GAIN_ACQ2_BITS                        2
#define DSC_2_3_SM_CTRL2_DFE_GAIN_ACQ2_SHIFT                       10

/* dsc_2_3 :: sm_ctrl2 :: dfe_gain_acq1 [09:08] */
#define DSC_2_3_SM_CTRL2_DFE_GAIN_ACQ1_MASK                        0x0300
#define DSC_2_3_SM_CTRL2_DFE_GAIN_ACQ1_ALIGN                       0
#define DSC_2_3_SM_CTRL2_DFE_GAIN_ACQ1_BITS                        2
#define DSC_2_3_SM_CTRL2_DFE_GAIN_ACQ1_SHIFT                       8

/* dsc_2_3 :: sm_ctrl2 :: vga_gain_acq2 [07:06] */
#define DSC_2_3_SM_CTRL2_VGA_GAIN_ACQ2_MASK                        0x00c0
#define DSC_2_3_SM_CTRL2_VGA_GAIN_ACQ2_ALIGN                       0
#define DSC_2_3_SM_CTRL2_VGA_GAIN_ACQ2_BITS                        2
#define DSC_2_3_SM_CTRL2_VGA_GAIN_ACQ2_SHIFT                       6

/* dsc_2_3 :: sm_ctrl2 :: vga_gain_acq1 [05:04] */
#define DSC_2_3_SM_CTRL2_VGA_GAIN_ACQ1_MASK                        0x0030
#define DSC_2_3_SM_CTRL2_VGA_GAIN_ACQ1_ALIGN                       0
#define DSC_2_3_SM_CTRL2_VGA_GAIN_ACQ1_BITS                        2
#define DSC_2_3_SM_CTRL2_VGA_GAIN_ACQ1_SHIFT                       4

/* dsc_2_3 :: sm_ctrl2 :: vga_gain_acqcdr [03:02] */
#define DSC_2_3_SM_CTRL2_VGA_GAIN_ACQCDR_MASK                      0x000c
#define DSC_2_3_SM_CTRL2_VGA_GAIN_ACQCDR_ALIGN                     0
#define DSC_2_3_SM_CTRL2_VGA_GAIN_ACQCDR_BITS                      2
#define DSC_2_3_SM_CTRL2_VGA_GAIN_ACQCDR_SHIFT                     2

/* dsc_2_3 :: sm_ctrl2 :: vga_gain_acqvga [01:00] */
#define DSC_2_3_SM_CTRL2_VGA_GAIN_ACQVGA_MASK                      0x0003
#define DSC_2_3_SM_CTRL2_VGA_GAIN_ACQVGA_ALIGN                     0
#define DSC_2_3_SM_CTRL2_VGA_GAIN_ACQVGA_BITS                      2
#define DSC_2_3_SM_CTRL2_VGA_GAIN_ACQVGA_SHIFT                     0


/****************************************************************************
 * dsc_2_3 :: sm_ctrl3
 ***************************************************************************/
/* dsc_2_3 :: sm_ctrl3 :: reserved_for_eco0 [15:12] */
#define DSC_2_3_SM_CTRL3_RESERVED_FOR_ECO0_MASK                    0xf000
#define DSC_2_3_SM_CTRL3_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC_2_3_SM_CTRL3_RESERVED_FOR_ECO0_BITS                    4
#define DSC_2_3_SM_CTRL3_RESERVED_FOR_ECO0_SHIFT                   12

/* dsc_2_3 :: sm_ctrl3 :: cdrbr_bwsel_integ_acq2 [11:10] */
#define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_MASK               0x0c00
#define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_ALIGN              0
#define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_BITS               2
#define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_SHIFT              10

/* dsc_2_3 :: sm_ctrl3 :: cdrbr_bwsel_integ_acq1 [09:08] */
#define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_MASK               0x0300
#define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_ALIGN              0
#define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_BITS               2
#define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_SHIFT              8

/* dsc_2_3 :: sm_ctrl3 :: cdrbr_bwsel_integ_acqcdr [07:06] */
#define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_MASK             0x00c0
#define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_ALIGN            0
#define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_BITS             2
#define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_SHIFT            6

/* dsc_2_3 :: sm_ctrl3 :: cdrbr_bwsel_prop_acq2 [05:03] */
#define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_MASK                0x0038
#define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_ALIGN               0
#define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_BITS                3
#define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_SHIFT               3

/* dsc_2_3 :: sm_ctrl3 :: cdrbr_bwsel_prop_acq1 [02:00] */
#define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_MASK                0x0007
#define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_ALIGN               0
#define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_BITS                3
#define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_SHIFT               0


/****************************************************************************
 * dsc_2_3 :: sm_ctrl4
 ***************************************************************************/
/* dsc_2_3 :: sm_ctrl4 :: cdros_bwsel_integ_acq1_2 [15:12] */
#define DSC_2_3_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_MASK             0xf000
#define DSC_2_3_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_ALIGN            0
#define DSC_2_3_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_BITS             4
#define DSC_2_3_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_SHIFT            12

/* dsc_2_3 :: sm_ctrl4 :: cdros_bwsel_integ_acqcdr [11:08] */
#define DSC_2_3_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_MASK             0x0f00
#define DSC_2_3_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_ALIGN            0
#define DSC_2_3_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_BITS             4
#define DSC_2_3_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_SHIFT            8

/* dsc_2_3 :: sm_ctrl4 :: cdros_bwsel_prop_acq1_2 [07:04] */
#define DSC_2_3_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_MASK              0x00f0
#define DSC_2_3_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_ALIGN             0
#define DSC_2_3_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_BITS              4
#define DSC_2_3_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_SHIFT             4

/* dsc_2_3 :: sm_ctrl4 :: cdros_bwsel_prop_acqcdr [03:00] */
#define DSC_2_3_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_MASK              0x000f
#define DSC_2_3_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_ALIGN             0
#define DSC_2_3_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_BITS              4
#define DSC_2_3_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_SHIFT             0


/****************************************************************************
 * dsc_2_3 :: dsc_status0
 ***************************************************************************/
/* dsc_2_3 :: dsc_status0 :: data_15_to_0 [15:00] */
#define DSC_2_3_DSC_STATUS0_DATA_15_TO_0_MASK                      0xffff
#define DSC_2_3_DSC_STATUS0_DATA_15_TO_0_ALIGN                     0
#define DSC_2_3_DSC_STATUS0_DATA_15_TO_0_BITS                      16
#define DSC_2_3_DSC_STATUS0_DATA_15_TO_0_SHIFT                     0


/****************************************************************************
 * dsc_2_3 :: dsc_status1
 ***************************************************************************/
/* dsc_2_3 :: dsc_status1 :: p1err_11_to_0 [15:04] */
#define DSC_2_3_DSC_STATUS1_P1ERR_11_TO_0_MASK                     0xfff0
#define DSC_2_3_DSC_STATUS1_P1ERR_11_TO_0_ALIGN                    0
#define DSC_2_3_DSC_STATUS1_P1ERR_11_TO_0_BITS                     12
#define DSC_2_3_DSC_STATUS1_P1ERR_11_TO_0_SHIFT                    4

/* dsc_2_3 :: dsc_status1 :: data_19_to_16 [03:00] */
#define DSC_2_3_DSC_STATUS1_DATA_19_TO_16_MASK                     0x000f
#define DSC_2_3_DSC_STATUS1_DATA_19_TO_16_ALIGN                    0
#define DSC_2_3_DSC_STATUS1_DATA_19_TO_16_BITS                     4
#define DSC_2_3_DSC_STATUS1_DATA_19_TO_16_SHIFT                    0


/****************************************************************************
 * dsc_2_3 :: dsc_status2
 ***************************************************************************/
/* dsc_2_3 :: dsc_status2 :: m1err_7_to_0 [15:08] */
#define DSC_2_3_DSC_STATUS2_M1ERR_7_TO_0_MASK                      0xff00
#define DSC_2_3_DSC_STATUS2_M1ERR_7_TO_0_ALIGN                     0
#define DSC_2_3_DSC_STATUS2_M1ERR_7_TO_0_BITS                      8
#define DSC_2_3_DSC_STATUS2_M1ERR_7_TO_0_SHIFT                     8

/* dsc_2_3 :: dsc_status2 :: p1err_19_to_12 [07:00] */
#define DSC_2_3_DSC_STATUS2_P1ERR_19_TO_12_MASK                    0x00ff
#define DSC_2_3_DSC_STATUS2_P1ERR_19_TO_12_ALIGN                   0
#define DSC_2_3_DSC_STATUS2_P1ERR_19_TO_12_BITS                    8
#define DSC_2_3_DSC_STATUS2_P1ERR_19_TO_12_SHIFT                   0


/****************************************************************************
 * dsc_2_3 :: dsc_status3
 ***************************************************************************/
/* dsc_2_3 :: dsc_status3 :: reserved_for_eco0 [15:12] */
#define DSC_2_3_DSC_STATUS3_RESERVED_FOR_ECO0_MASK                 0xf000
#define DSC_2_3_DSC_STATUS3_RESERVED_FOR_ECO0_ALIGN                0
#define DSC_2_3_DSC_STATUS3_RESERVED_FOR_ECO0_BITS                 4
#define DSC_2_3_DSC_STATUS3_RESERVED_FOR_ECO0_SHIFT                12

/* dsc_2_3 :: dsc_status3 :: m1err_19_to_8 [11:00] */
#define DSC_2_3_DSC_STATUS3_M1ERR_19_TO_8_MASK                     0x0fff
#define DSC_2_3_DSC_STATUS3_M1ERR_19_TO_8_ALIGN                    0
#define DSC_2_3_DSC_STATUS3_M1ERR_19_TO_8_BITS                     12
#define DSC_2_3_DSC_STATUS3_M1ERR_19_TO_8_SHIFT                    0


/****************************************************************************
 * dsc_2_3 :: dsc_ctrl0
 ***************************************************************************/
/* dsc_2_3 :: dsc_ctrl0 :: rxSeqStart [15:15] */
#define DSC_2_3_DSC_CTRL0_RXSEQSTART_MASK                          0x8000
#define DSC_2_3_DSC_CTRL0_RXSEQSTART_ALIGN                         0
#define DSC_2_3_DSC_CTRL0_RXSEQSTART_BITS                          1
#define DSC_2_3_DSC_CTRL0_RXSEQSTART_SHIFT                         15

/* dsc_2_3 :: dsc_ctrl0 :: forceRxSeqDone [14:14] */
#define DSC_2_3_DSC_CTRL0_FORCERXSEQDONE_MASK                      0x4000
#define DSC_2_3_DSC_CTRL0_FORCERXSEQDONE_ALIGN                     0
#define DSC_2_3_DSC_CTRL0_FORCERXSEQDONE_BITS                      1
#define DSC_2_3_DSC_CTRL0_FORCERXSEQDONE_SHIFT                     14

/* dsc_2_3 :: dsc_ctrl0 :: test_bus_sel [13:10] */
#define DSC_2_3_DSC_CTRL0_TEST_BUS_SEL_MASK                        0x3c00
#define DSC_2_3_DSC_CTRL0_TEST_BUS_SEL_ALIGN                       0
#define DSC_2_3_DSC_CTRL0_TEST_BUS_SEL_BITS                        4
#define DSC_2_3_DSC_CTRL0_TEST_BUS_SEL_SHIFT                       10
#define DSC_2_3_DSC_CTRL0_TEST_BUS_SEL_Off                         0
#define DSC_2_3_DSC_CTRL0_TEST_BUS_SEL_OSx2data                    1
#define DSC_2_3_DSC_CTRL0_TEST_BUS_SEL_OSx1data_m1                 2
#define DSC_2_3_DSC_CTRL0_TEST_BUS_SEL_BR_data_m1_p1               3
#define DSC_2_3_DSC_CTRL0_TEST_BUS_SEL_cdrPhaseVco                 4
#define DSC_2_3_DSC_CTRL0_TEST_BUS_SEL_cdrIntg                     6
#define DSC_2_3_DSC_CTRL0_TEST_BUS_SEL_cdrPhaseErr                 7
#define DSC_2_3_DSC_CTRL0_TEST_BUS_SEL_dfeAccEvenOdd               8
#define DSC_2_3_DSC_CTRL0_TEST_BUS_SEL_dfeVgasumDfe                9
#define DSC_2_3_DSC_CTRL0_TEST_BUS_SEL_dfeTrnsum                   10

/* dsc_2_3 :: dsc_ctrl0 :: rx_m1_thresh_zero [09:09] */
#define DSC_2_3_DSC_CTRL0_RX_M1_THRESH_ZERO_MASK                   0x0200
#define DSC_2_3_DSC_CTRL0_RX_M1_THRESH_ZERO_ALIGN                  0
#define DSC_2_3_DSC_CTRL0_RX_M1_THRESH_ZERO_BITS                   1
#define DSC_2_3_DSC_CTRL0_RX_M1_THRESH_ZERO_SHIFT                  9

/* dsc_2_3 :: dsc_ctrl0 :: rx_thresh_sel [08:07] */
#define DSC_2_3_DSC_CTRL0_RX_THRESH_SEL_MASK                       0x0180
#define DSC_2_3_DSC_CTRL0_RX_THRESH_SEL_ALIGN                      0
#define DSC_2_3_DSC_CTRL0_RX_THRESH_SEL_BITS                       2
#define DSC_2_3_DSC_CTRL0_RX_THRESH_SEL_SHIFT                      7

/* dsc_2_3 :: dsc_ctrl0 :: rx_pf_ctrl [06:04] */
#define DSC_2_3_DSC_CTRL0_RX_PF_CTRL_MASK                          0x0070
#define DSC_2_3_DSC_CTRL0_RX_PF_CTRL_ALIGN                         0
#define DSC_2_3_DSC_CTRL0_RX_PF_CTRL_BITS                          3
#define DSC_2_3_DSC_CTRL0_RX_PF_CTRL_SHIFT                         4

/* dsc_2_3 :: dsc_ctrl0 :: cdrbr_sel [03:03] */
#define DSC_2_3_DSC_CTRL0_CDRBR_SEL_MASK                           0x0008
#define DSC_2_3_DSC_CTRL0_CDRBR_SEL_ALIGN                          0
#define DSC_2_3_DSC_CTRL0_CDRBR_SEL_BITS                           1
#define DSC_2_3_DSC_CTRL0_CDRBR_SEL_SHIFT                          3

/* dsc_2_3 :: dsc_ctrl0 :: oscdr_force_mode_en [02:02] */
#define DSC_2_3_DSC_CTRL0_OSCDR_FORCE_MODE_EN_MASK                 0x0004
#define DSC_2_3_DSC_CTRL0_OSCDR_FORCE_MODE_EN_ALIGN                0
#define DSC_2_3_DSC_CTRL0_OSCDR_FORCE_MODE_EN_BITS                 1
#define DSC_2_3_DSC_CTRL0_OSCDR_FORCE_MODE_EN_SHIFT                2

/* dsc_2_3 :: dsc_ctrl0 :: oscdr_mode [01:00] */
#define DSC_2_3_DSC_CTRL0_OSCDR_MODE_MASK                          0x0003
#define DSC_2_3_DSC_CTRL0_OSCDR_MODE_ALIGN                         0
#define DSC_2_3_DSC_CTRL0_OSCDR_MODE_BITS                          2
#define DSC_2_3_DSC_CTRL0_OSCDR_MODE_SHIFT                         0


/****************************************************************************
 * dsc_2_3 :: dsc_ctrl1
 ***************************************************************************/
/* dsc_2_3 :: dsc_ctrl1 :: reserved_for_eco0 [15:15] */
#define DSC_2_3_DSC_CTRL1_RESERVED_FOR_ECO0_MASK                   0x8000
#define DSC_2_3_DSC_CTRL1_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC_2_3_DSC_CTRL1_RESERVED_FOR_ECO0_BITS                   1
#define DSC_2_3_DSC_CTRL1_RESERVED_FOR_ECO0_SHIFT                  15

/* dsc_2_3 :: dsc_ctrl1 :: p1_odd_ctrl [14:10] */
#define DSC_2_3_DSC_CTRL1_P1_ODD_CTRL_MASK                         0x7c00
#define DSC_2_3_DSC_CTRL1_P1_ODD_CTRL_ALIGN                        0
#define DSC_2_3_DSC_CTRL1_P1_ODD_CTRL_BITS                         5
#define DSC_2_3_DSC_CTRL1_P1_ODD_CTRL_SHIFT                        10

/* dsc_2_3 :: dsc_ctrl1 :: p1_evn_ctrl [09:05] */
#define DSC_2_3_DSC_CTRL1_P1_EVN_CTRL_MASK                         0x03e0
#define DSC_2_3_DSC_CTRL1_P1_EVN_CTRL_ALIGN                        0
#define DSC_2_3_DSC_CTRL1_P1_EVN_CTRL_BITS                         5
#define DSC_2_3_DSC_CTRL1_P1_EVN_CTRL_SHIFT                        5

/* dsc_2_3 :: dsc_ctrl1 :: d_odd_ctrl [04:00] */
#define DSC_2_3_DSC_CTRL1_D_ODD_CTRL_MASK                          0x001f
#define DSC_2_3_DSC_CTRL1_D_ODD_CTRL_ALIGN                         0
#define DSC_2_3_DSC_CTRL1_D_ODD_CTRL_BITS                          5
#define DSC_2_3_DSC_CTRL1_D_ODD_CTRL_SHIFT                         0


/****************************************************************************
 * dsc_2_3 :: dsc_ctrl2
 ***************************************************************************/
/* dsc_2_3 :: dsc_ctrl2 :: reserved_for_eco0 [15:15] */
#define DSC_2_3_DSC_CTRL2_RESERVED_FOR_ECO0_MASK                   0x8000
#define DSC_2_3_DSC_CTRL2_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC_2_3_DSC_CTRL2_RESERVED_FOR_ECO0_BITS                   1
#define DSC_2_3_DSC_CTRL2_RESERVED_FOR_ECO0_SHIFT                  15

/* dsc_2_3 :: dsc_ctrl2 :: d_evn_ctrl [14:10] */
#define DSC_2_3_DSC_CTRL2_D_EVN_CTRL_MASK                          0x7c00
#define DSC_2_3_DSC_CTRL2_D_EVN_CTRL_ALIGN                         0
#define DSC_2_3_DSC_CTRL2_D_EVN_CTRL_BITS                          5
#define DSC_2_3_DSC_CTRL2_D_EVN_CTRL_SHIFT                         10

/* dsc_2_3 :: dsc_ctrl2 :: m1_odd_ctrl [09:05] */
#define DSC_2_3_DSC_CTRL2_M1_ODD_CTRL_MASK                         0x03e0
#define DSC_2_3_DSC_CTRL2_M1_ODD_CTRL_ALIGN                        0
#define DSC_2_3_DSC_CTRL2_M1_ODD_CTRL_BITS                         5
#define DSC_2_3_DSC_CTRL2_M1_ODD_CTRL_SHIFT                        5

/* dsc_2_3 :: dsc_ctrl2 :: m1_evn_ctrl [04:00] */
#define DSC_2_3_DSC_CTRL2_M1_EVN_CTRL_MASK                         0x001f
#define DSC_2_3_DSC_CTRL2_M1_EVN_CTRL_ALIGN                        0
#define DSC_2_3_DSC_CTRL2_M1_EVN_CTRL_BITS                         5
#define DSC_2_3_DSC_CTRL2_M1_EVN_CTRL_SHIFT                        0


/****************************************************************************
 * XGXS16G_USER_dsc_2_A
 ***************************************************************************/
/****************************************************************************
 * dsc_2_A :: sm_status0
 ***************************************************************************/
/* dsc_2_A :: sm_status0 :: reserved_for_eco0 [15:04] */
#define DSC_2_A_SM_STATUS0_RESERVED_FOR_ECO0_MASK                  0xfff0
#define DSC_2_A_SM_STATUS0_RESERVED_FOR_ECO0_ALIGN                 0
#define DSC_2_A_SM_STATUS0_RESERVED_FOR_ECO0_BITS                  12
#define DSC_2_A_SM_STATUS0_RESERVED_FOR_ECO0_SHIFT                 4

/* dsc_2_A :: sm_status0 :: dsc_state [03:00] */
#define DSC_2_A_SM_STATUS0_DSC_STATE_MASK                          0x000f
#define DSC_2_A_SM_STATUS0_DSC_STATE_ALIGN                         0
#define DSC_2_A_SM_STATUS0_DSC_STATE_BITS                          4
#define DSC_2_A_SM_STATUS0_DSC_STATE_SHIFT                         0


/****************************************************************************
 * dsc_2_A :: sm_ctrl0
 ***************************************************************************/
/* dsc_2_A :: sm_ctrl0 :: acqvga_timeout [15:11] */
#define DSC_2_A_SM_CTRL0_ACQVGA_TIMEOUT_MASK                       0xf800
#define DSC_2_A_SM_CTRL0_ACQVGA_TIMEOUT_ALIGN                      0
#define DSC_2_A_SM_CTRL0_ACQVGA_TIMEOUT_BITS                       5
#define DSC_2_A_SM_CTRL0_ACQVGA_TIMEOUT_SHIFT                      11

/* dsc_2_A :: sm_ctrl0 :: tuning_sm_en [10:10] */
#define DSC_2_A_SM_CTRL0_TUNING_SM_EN_MASK                         0x0400
#define DSC_2_A_SM_CTRL0_TUNING_SM_EN_ALIGN                        0
#define DSC_2_A_SM_CTRL0_TUNING_SM_EN_BITS                         1
#define DSC_2_A_SM_CTRL0_TUNING_SM_EN_SHIFT                        10

/* dsc_2_A :: sm_ctrl0 :: train2_req [09:09] */
#define DSC_2_A_SM_CTRL0_TRAIN2_REQ_MASK                           0x0200
#define DSC_2_A_SM_CTRL0_TRAIN2_REQ_ALIGN                          0
#define DSC_2_A_SM_CTRL0_TRAIN2_REQ_BITS                           1
#define DSC_2_A_SM_CTRL0_TRAIN2_REQ_SHIFT                          9

/* dsc_2_A :: sm_ctrl0 :: train1_req [08:08] */
#define DSC_2_A_SM_CTRL0_TRAIN1_REQ_MASK                           0x0100
#define DSC_2_A_SM_CTRL0_TRAIN1_REQ_ALIGN                          0
#define DSC_2_A_SM_CTRL0_TRAIN1_REQ_BITS                           1
#define DSC_2_A_SM_CTRL0_TRAIN1_REQ_SHIFT                          8

/* dsc_2_A :: sm_ctrl0 :: soft_ack [07:07] */
#define DSC_2_A_SM_CTRL0_SOFT_ACK_MASK                             0x0080
#define DSC_2_A_SM_CTRL0_SOFT_ACK_ALIGN                            0
#define DSC_2_A_SM_CTRL0_SOFT_ACK_BITS                             1
#define DSC_2_A_SM_CTRL0_SOFT_ACK_SHIFT                            7

/* dsc_2_A :: sm_ctrl0 :: train_mode_en [06:06] */
#define DSC_2_A_SM_CTRL0_TRAIN_MODE_EN_MASK                        0x0040
#define DSC_2_A_SM_CTRL0_TRAIN_MODE_EN_ALIGN                       0
#define DSC_2_A_SM_CTRL0_TRAIN_MODE_EN_BITS                        1
#define DSC_2_A_SM_CTRL0_TRAIN_MODE_EN_SHIFT                       6

/* dsc_2_A :: sm_ctrl0 :: vga_frzval [05:05] */
#define DSC_2_A_SM_CTRL0_VGA_FRZVAL_MASK                           0x0020
#define DSC_2_A_SM_CTRL0_VGA_FRZVAL_ALIGN                          0
#define DSC_2_A_SM_CTRL0_VGA_FRZVAL_BITS                           1
#define DSC_2_A_SM_CTRL0_VGA_FRZVAL_SHIFT                          5

/* dsc_2_A :: sm_ctrl0 :: vga_frcfrz [04:04] */
#define DSC_2_A_SM_CTRL0_VGA_FRCFRZ_MASK                           0x0010
#define DSC_2_A_SM_CTRL0_VGA_FRCFRZ_ALIGN                          0
#define DSC_2_A_SM_CTRL0_VGA_FRCFRZ_BITS                           1
#define DSC_2_A_SM_CTRL0_VGA_FRCFRZ_SHIFT                          4

/* dsc_2_A :: sm_ctrl0 :: dfe_frzval [03:03] */
#define DSC_2_A_SM_CTRL0_DFE_FRZVAL_MASK                           0x0008
#define DSC_2_A_SM_CTRL0_DFE_FRZVAL_ALIGN                          0
#define DSC_2_A_SM_CTRL0_DFE_FRZVAL_BITS                           1
#define DSC_2_A_SM_CTRL0_DFE_FRZVAL_SHIFT                          3

/* dsc_2_A :: sm_ctrl0 :: dfe_frcfrz [02:02] */
#define DSC_2_A_SM_CTRL0_DFE_FRCFRZ_MASK                           0x0004
#define DSC_2_A_SM_CTRL0_DFE_FRCFRZ_ALIGN                          0
#define DSC_2_A_SM_CTRL0_DFE_FRCFRZ_BITS                           1
#define DSC_2_A_SM_CTRL0_DFE_FRCFRZ_SHIFT                          2

/* dsc_2_A :: sm_ctrl0 :: dsc_clr_val [01:01] */
#define DSC_2_A_SM_CTRL0_DSC_CLR_VAL_MASK                          0x0002
#define DSC_2_A_SM_CTRL0_DSC_CLR_VAL_ALIGN                         0
#define DSC_2_A_SM_CTRL0_DSC_CLR_VAL_BITS                          1
#define DSC_2_A_SM_CTRL0_DSC_CLR_VAL_SHIFT                         1

/* dsc_2_A :: sm_ctrl0 :: dsc_clr_frc [00:00] */
#define DSC_2_A_SM_CTRL0_DSC_CLR_FRC_MASK                          0x0001
#define DSC_2_A_SM_CTRL0_DSC_CLR_FRC_ALIGN                         0
#define DSC_2_A_SM_CTRL0_DSC_CLR_FRC_BITS                          1
#define DSC_2_A_SM_CTRL0_DSC_CLR_FRC_SHIFT                         0


/****************************************************************************
 * dsc_2_A :: sm_ctrl1
 ***************************************************************************/
/* dsc_2_A :: sm_ctrl1 :: fast_timer [15:15] */
#define DSC_2_A_SM_CTRL1_FAST_TIMER_MASK                           0x8000
#define DSC_2_A_SM_CTRL1_FAST_TIMER_ALIGN                          0
#define DSC_2_A_SM_CTRL1_FAST_TIMER_BITS                           1
#define DSC_2_A_SM_CTRL1_FAST_TIMER_SHIFT                          15

/* dsc_2_A :: sm_ctrl1 :: acq2_timeout [14:10] */
#define DSC_2_A_SM_CTRL1_ACQ2_TIMEOUT_MASK                         0x7c00
#define DSC_2_A_SM_CTRL1_ACQ2_TIMEOUT_ALIGN                        0
#define DSC_2_A_SM_CTRL1_ACQ2_TIMEOUT_BITS                         5
#define DSC_2_A_SM_CTRL1_ACQ2_TIMEOUT_SHIFT                        10

/* dsc_2_A :: sm_ctrl1 :: acq1_timeout [09:05] */
#define DSC_2_A_SM_CTRL1_ACQ1_TIMEOUT_MASK                         0x03e0
#define DSC_2_A_SM_CTRL1_ACQ1_TIMEOUT_ALIGN                        0
#define DSC_2_A_SM_CTRL1_ACQ1_TIMEOUT_BITS                         5
#define DSC_2_A_SM_CTRL1_ACQ1_TIMEOUT_SHIFT                        5

/* dsc_2_A :: sm_ctrl1 :: acqcdr_timeout [04:00] */
#define DSC_2_A_SM_CTRL1_ACQCDR_TIMEOUT_MASK                       0x001f
#define DSC_2_A_SM_CTRL1_ACQCDR_TIMEOUT_ALIGN                      0
#define DSC_2_A_SM_CTRL1_ACQCDR_TIMEOUT_BITS                       5
#define DSC_2_A_SM_CTRL1_ACQCDR_TIMEOUT_SHIFT                      0


/****************************************************************************
 * dsc_2_A :: sm_ctrl2
 ***************************************************************************/
/* dsc_2_A :: sm_ctrl2 :: reserved_for_eco0 [15:15] */
#define DSC_2_A_SM_CTRL2_RESERVED_FOR_ECO0_MASK                    0x8000
#define DSC_2_A_SM_CTRL2_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC_2_A_SM_CTRL2_RESERVED_FOR_ECO0_BITS                    1
#define DSC_2_A_SM_CTRL2_RESERVED_FOR_ECO0_SHIFT                   15

/* dsc_2_A :: sm_ctrl2 :: cdrbr_bwsel_prop_acqcdr [14:12] */
#define DSC_2_A_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_MASK              0x7000
#define DSC_2_A_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_ALIGN             0
#define DSC_2_A_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_BITS              3
#define DSC_2_A_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_SHIFT             12

/* dsc_2_A :: sm_ctrl2 :: dfe_gain_acq2 [11:10] */
#define DSC_2_A_SM_CTRL2_DFE_GAIN_ACQ2_MASK                        0x0c00
#define DSC_2_A_SM_CTRL2_DFE_GAIN_ACQ2_ALIGN                       0
#define DSC_2_A_SM_CTRL2_DFE_GAIN_ACQ2_BITS                        2
#define DSC_2_A_SM_CTRL2_DFE_GAIN_ACQ2_SHIFT                       10

/* dsc_2_A :: sm_ctrl2 :: dfe_gain_acq1 [09:08] */
#define DSC_2_A_SM_CTRL2_DFE_GAIN_ACQ1_MASK                        0x0300
#define DSC_2_A_SM_CTRL2_DFE_GAIN_ACQ1_ALIGN                       0
#define DSC_2_A_SM_CTRL2_DFE_GAIN_ACQ1_BITS                        2
#define DSC_2_A_SM_CTRL2_DFE_GAIN_ACQ1_SHIFT                       8

/* dsc_2_A :: sm_ctrl2 :: vga_gain_acq2 [07:06] */
#define DSC_2_A_SM_CTRL2_VGA_GAIN_ACQ2_MASK                        0x00c0
#define DSC_2_A_SM_CTRL2_VGA_GAIN_ACQ2_ALIGN                       0
#define DSC_2_A_SM_CTRL2_VGA_GAIN_ACQ2_BITS                        2
#define DSC_2_A_SM_CTRL2_VGA_GAIN_ACQ2_SHIFT                       6

/* dsc_2_A :: sm_ctrl2 :: vga_gain_acq1 [05:04] */
#define DSC_2_A_SM_CTRL2_VGA_GAIN_ACQ1_MASK                        0x0030
#define DSC_2_A_SM_CTRL2_VGA_GAIN_ACQ1_ALIGN                       0
#define DSC_2_A_SM_CTRL2_VGA_GAIN_ACQ1_BITS                        2
#define DSC_2_A_SM_CTRL2_VGA_GAIN_ACQ1_SHIFT                       4

/* dsc_2_A :: sm_ctrl2 :: vga_gain_acqcdr [03:02] */
#define DSC_2_A_SM_CTRL2_VGA_GAIN_ACQCDR_MASK                      0x000c
#define DSC_2_A_SM_CTRL2_VGA_GAIN_ACQCDR_ALIGN                     0
#define DSC_2_A_SM_CTRL2_VGA_GAIN_ACQCDR_BITS                      2
#define DSC_2_A_SM_CTRL2_VGA_GAIN_ACQCDR_SHIFT                     2

/* dsc_2_A :: sm_ctrl2 :: vga_gain_acqvga [01:00] */
#define DSC_2_A_SM_CTRL2_VGA_GAIN_ACQVGA_MASK                      0x0003
#define DSC_2_A_SM_CTRL2_VGA_GAIN_ACQVGA_ALIGN                     0
#define DSC_2_A_SM_CTRL2_VGA_GAIN_ACQVGA_BITS                      2
#define DSC_2_A_SM_CTRL2_VGA_GAIN_ACQVGA_SHIFT                     0


/****************************************************************************
 * dsc_2_A :: sm_ctrl3
 ***************************************************************************/
/* dsc_2_A :: sm_ctrl3 :: reserved_for_eco0 [15:12] */
#define DSC_2_A_SM_CTRL3_RESERVED_FOR_ECO0_MASK                    0xf000
#define DSC_2_A_SM_CTRL3_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC_2_A_SM_CTRL3_RESERVED_FOR_ECO0_BITS                    4
#define DSC_2_A_SM_CTRL3_RESERVED_FOR_ECO0_SHIFT                   12

/* dsc_2_A :: sm_ctrl3 :: cdrbr_bwsel_integ_acq2 [11:10] */
#define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_MASK               0x0c00
#define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_ALIGN              0
#define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_BITS               2
#define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_SHIFT              10

/* dsc_2_A :: sm_ctrl3 :: cdrbr_bwsel_integ_acq1 [09:08] */
#define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_MASK               0x0300
#define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_ALIGN              0
#define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_BITS               2
#define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_SHIFT              8

/* dsc_2_A :: sm_ctrl3 :: cdrbr_bwsel_integ_acqcdr [07:06] */
#define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_MASK             0x00c0
#define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_ALIGN            0
#define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_BITS             2
#define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_SHIFT            6

/* dsc_2_A :: sm_ctrl3 :: cdrbr_bwsel_prop_acq2 [05:03] */
#define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_MASK                0x0038
#define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_ALIGN               0
#define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_BITS                3
#define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_SHIFT               3

/* dsc_2_A :: sm_ctrl3 :: cdrbr_bwsel_prop_acq1 [02:00] */
#define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_MASK                0x0007
#define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_ALIGN               0
#define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_BITS                3
#define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_SHIFT               0


/****************************************************************************
 * dsc_2_A :: sm_ctrl4
 ***************************************************************************/
/* dsc_2_A :: sm_ctrl4 :: cdros_bwsel_integ_acq1_2 [15:12] */
#define DSC_2_A_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_MASK             0xf000
#define DSC_2_A_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_ALIGN            0
#define DSC_2_A_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_BITS             4
#define DSC_2_A_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_SHIFT            12

/* dsc_2_A :: sm_ctrl4 :: cdros_bwsel_integ_acqcdr [11:08] */
#define DSC_2_A_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_MASK             0x0f00
#define DSC_2_A_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_ALIGN            0
#define DSC_2_A_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_BITS             4
#define DSC_2_A_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_SHIFT            8

/* dsc_2_A :: sm_ctrl4 :: cdros_bwsel_prop_acq1_2 [07:04] */
#define DSC_2_A_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_MASK              0x00f0
#define DSC_2_A_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_ALIGN             0
#define DSC_2_A_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_BITS              4
#define DSC_2_A_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_SHIFT             4

/* dsc_2_A :: sm_ctrl4 :: cdros_bwsel_prop_acqcdr [03:00] */
#define DSC_2_A_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_MASK              0x000f
#define DSC_2_A_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_ALIGN             0
#define DSC_2_A_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_BITS              4
#define DSC_2_A_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_SHIFT             0


/****************************************************************************
 * dsc_2_A :: dsc_status0
 ***************************************************************************/
/* dsc_2_A :: dsc_status0 :: data_15_to_0 [15:00] */
#define DSC_2_A_DSC_STATUS0_DATA_15_TO_0_MASK                      0xffff
#define DSC_2_A_DSC_STATUS0_DATA_15_TO_0_ALIGN                     0
#define DSC_2_A_DSC_STATUS0_DATA_15_TO_0_BITS                      16
#define DSC_2_A_DSC_STATUS0_DATA_15_TO_0_SHIFT                     0


/****************************************************************************
 * dsc_2_A :: dsc_status1
 ***************************************************************************/
/* dsc_2_A :: dsc_status1 :: p1err_11_to_0 [15:04] */
#define DSC_2_A_DSC_STATUS1_P1ERR_11_TO_0_MASK                     0xfff0
#define DSC_2_A_DSC_STATUS1_P1ERR_11_TO_0_ALIGN                    0
#define DSC_2_A_DSC_STATUS1_P1ERR_11_TO_0_BITS                     12
#define DSC_2_A_DSC_STATUS1_P1ERR_11_TO_0_SHIFT                    4

/* dsc_2_A :: dsc_status1 :: data_19_to_16 [03:00] */
#define DSC_2_A_DSC_STATUS1_DATA_19_TO_16_MASK                     0x000f
#define DSC_2_A_DSC_STATUS1_DATA_19_TO_16_ALIGN                    0
#define DSC_2_A_DSC_STATUS1_DATA_19_TO_16_BITS                     4
#define DSC_2_A_DSC_STATUS1_DATA_19_TO_16_SHIFT                    0


/****************************************************************************
 * dsc_2_A :: dsc_status2
 ***************************************************************************/
/* dsc_2_A :: dsc_status2 :: m1err_7_to_0 [15:08] */
#define DSC_2_A_DSC_STATUS2_M1ERR_7_TO_0_MASK                      0xff00
#define DSC_2_A_DSC_STATUS2_M1ERR_7_TO_0_ALIGN                     0
#define DSC_2_A_DSC_STATUS2_M1ERR_7_TO_0_BITS                      8
#define DSC_2_A_DSC_STATUS2_M1ERR_7_TO_0_SHIFT                     8

/* dsc_2_A :: dsc_status2 :: p1err_19_to_12 [07:00] */
#define DSC_2_A_DSC_STATUS2_P1ERR_19_TO_12_MASK                    0x00ff
#define DSC_2_A_DSC_STATUS2_P1ERR_19_TO_12_ALIGN                   0
#define DSC_2_A_DSC_STATUS2_P1ERR_19_TO_12_BITS                    8
#define DSC_2_A_DSC_STATUS2_P1ERR_19_TO_12_SHIFT                   0


/****************************************************************************
 * dsc_2_A :: dsc_status3
 ***************************************************************************/
/* dsc_2_A :: dsc_status3 :: reserved_for_eco0 [15:12] */
#define DSC_2_A_DSC_STATUS3_RESERVED_FOR_ECO0_MASK                 0xf000
#define DSC_2_A_DSC_STATUS3_RESERVED_FOR_ECO0_ALIGN                0
#define DSC_2_A_DSC_STATUS3_RESERVED_FOR_ECO0_BITS                 4
#define DSC_2_A_DSC_STATUS3_RESERVED_FOR_ECO0_SHIFT                12

/* dsc_2_A :: dsc_status3 :: m1err_19_to_8 [11:00] */
#define DSC_2_A_DSC_STATUS3_M1ERR_19_TO_8_MASK                     0x0fff
#define DSC_2_A_DSC_STATUS3_M1ERR_19_TO_8_ALIGN                    0
#define DSC_2_A_DSC_STATUS3_M1ERR_19_TO_8_BITS                     12
#define DSC_2_A_DSC_STATUS3_M1ERR_19_TO_8_SHIFT                    0


/****************************************************************************
 * dsc_2_A :: dsc_ctrl0
 ***************************************************************************/
/* dsc_2_A :: dsc_ctrl0 :: rxSeqStart [15:15] */
#define DSC_2_A_DSC_CTRL0_RXSEQSTART_MASK                          0x8000
#define DSC_2_A_DSC_CTRL0_RXSEQSTART_ALIGN                         0
#define DSC_2_A_DSC_CTRL0_RXSEQSTART_BITS                          1
#define DSC_2_A_DSC_CTRL0_RXSEQSTART_SHIFT                         15

/* dsc_2_A :: dsc_ctrl0 :: forceRxSeqDone [14:14] */
#define DSC_2_A_DSC_CTRL0_FORCERXSEQDONE_MASK                      0x4000
#define DSC_2_A_DSC_CTRL0_FORCERXSEQDONE_ALIGN                     0
#define DSC_2_A_DSC_CTRL0_FORCERXSEQDONE_BITS                      1
#define DSC_2_A_DSC_CTRL0_FORCERXSEQDONE_SHIFT                     14

/* dsc_2_A :: dsc_ctrl0 :: test_bus_sel [13:10] */
#define DSC_2_A_DSC_CTRL0_TEST_BUS_SEL_MASK                        0x3c00
#define DSC_2_A_DSC_CTRL0_TEST_BUS_SEL_ALIGN                       0
#define DSC_2_A_DSC_CTRL0_TEST_BUS_SEL_BITS                        4
#define DSC_2_A_DSC_CTRL0_TEST_BUS_SEL_SHIFT                       10
#define DSC_2_A_DSC_CTRL0_TEST_BUS_SEL_Off                         0
#define DSC_2_A_DSC_CTRL0_TEST_BUS_SEL_OSx2data                    1
#define DSC_2_A_DSC_CTRL0_TEST_BUS_SEL_OSx1data_m1                 2
#define DSC_2_A_DSC_CTRL0_TEST_BUS_SEL_BR_data_m1_p1               3
#define DSC_2_A_DSC_CTRL0_TEST_BUS_SEL_cdrPhaseVco                 4
#define DSC_2_A_DSC_CTRL0_TEST_BUS_SEL_cdrIntg                     6
#define DSC_2_A_DSC_CTRL0_TEST_BUS_SEL_cdrPhaseErr                 7
#define DSC_2_A_DSC_CTRL0_TEST_BUS_SEL_dfeAccEvenOdd               8
#define DSC_2_A_DSC_CTRL0_TEST_BUS_SEL_dfeVgasumDfe                9
#define DSC_2_A_DSC_CTRL0_TEST_BUS_SEL_dfeTrnsum                   10

/* dsc_2_A :: dsc_ctrl0 :: rx_m1_thresh_zero [09:09] */
#define DSC_2_A_DSC_CTRL0_RX_M1_THRESH_ZERO_MASK                   0x0200
#define DSC_2_A_DSC_CTRL0_RX_M1_THRESH_ZERO_ALIGN                  0
#define DSC_2_A_DSC_CTRL0_RX_M1_THRESH_ZERO_BITS                   1
#define DSC_2_A_DSC_CTRL0_RX_M1_THRESH_ZERO_SHIFT                  9

/* dsc_2_A :: dsc_ctrl0 :: rx_thresh_sel [08:07] */
#define DSC_2_A_DSC_CTRL0_RX_THRESH_SEL_MASK                       0x0180
#define DSC_2_A_DSC_CTRL0_RX_THRESH_SEL_ALIGN                      0
#define DSC_2_A_DSC_CTRL0_RX_THRESH_SEL_BITS                       2
#define DSC_2_A_DSC_CTRL0_RX_THRESH_SEL_SHIFT                      7

/* dsc_2_A :: dsc_ctrl0 :: rx_pf_ctrl [06:04] */
#define DSC_2_A_DSC_CTRL0_RX_PF_CTRL_MASK                          0x0070
#define DSC_2_A_DSC_CTRL0_RX_PF_CTRL_ALIGN                         0
#define DSC_2_A_DSC_CTRL0_RX_PF_CTRL_BITS                          3
#define DSC_2_A_DSC_CTRL0_RX_PF_CTRL_SHIFT                         4

/* dsc_2_A :: dsc_ctrl0 :: cdrbr_sel [03:03] */
#define DSC_2_A_DSC_CTRL0_CDRBR_SEL_MASK                           0x0008
#define DSC_2_A_DSC_CTRL0_CDRBR_SEL_ALIGN                          0
#define DSC_2_A_DSC_CTRL0_CDRBR_SEL_BITS                           1
#define DSC_2_A_DSC_CTRL0_CDRBR_SEL_SHIFT                          3

/* dsc_2_A :: dsc_ctrl0 :: oscdr_force_mode_en [02:02] */
#define DSC_2_A_DSC_CTRL0_OSCDR_FORCE_MODE_EN_MASK                 0x0004
#define DSC_2_A_DSC_CTRL0_OSCDR_FORCE_MODE_EN_ALIGN                0
#define DSC_2_A_DSC_CTRL0_OSCDR_FORCE_MODE_EN_BITS                 1
#define DSC_2_A_DSC_CTRL0_OSCDR_FORCE_MODE_EN_SHIFT                2

/* dsc_2_A :: dsc_ctrl0 :: oscdr_mode [01:00] */
#define DSC_2_A_DSC_CTRL0_OSCDR_MODE_MASK                          0x0003
#define DSC_2_A_DSC_CTRL0_OSCDR_MODE_ALIGN                         0
#define DSC_2_A_DSC_CTRL0_OSCDR_MODE_BITS                          2
#define DSC_2_A_DSC_CTRL0_OSCDR_MODE_SHIFT                         0


/****************************************************************************
 * dsc_2_A :: dsc_ctrl1
 ***************************************************************************/
/* dsc_2_A :: dsc_ctrl1 :: reserved_for_eco0 [15:15] */
#define DSC_2_A_DSC_CTRL1_RESERVED_FOR_ECO0_MASK                   0x8000
#define DSC_2_A_DSC_CTRL1_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC_2_A_DSC_CTRL1_RESERVED_FOR_ECO0_BITS                   1
#define DSC_2_A_DSC_CTRL1_RESERVED_FOR_ECO0_SHIFT                  15

/* dsc_2_A :: dsc_ctrl1 :: p1_odd_ctrl [14:10] */
#define DSC_2_A_DSC_CTRL1_P1_ODD_CTRL_MASK                         0x7c00
#define DSC_2_A_DSC_CTRL1_P1_ODD_CTRL_ALIGN                        0
#define DSC_2_A_DSC_CTRL1_P1_ODD_CTRL_BITS                         5
#define DSC_2_A_DSC_CTRL1_P1_ODD_CTRL_SHIFT                        10

/* dsc_2_A :: dsc_ctrl1 :: p1_evn_ctrl [09:05] */
#define DSC_2_A_DSC_CTRL1_P1_EVN_CTRL_MASK                         0x03e0
#define DSC_2_A_DSC_CTRL1_P1_EVN_CTRL_ALIGN                        0
#define DSC_2_A_DSC_CTRL1_P1_EVN_CTRL_BITS                         5
#define DSC_2_A_DSC_CTRL1_P1_EVN_CTRL_SHIFT                        5

/* dsc_2_A :: dsc_ctrl1 :: d_odd_ctrl [04:00] */
#define DSC_2_A_DSC_CTRL1_D_ODD_CTRL_MASK                          0x001f
#define DSC_2_A_DSC_CTRL1_D_ODD_CTRL_ALIGN                         0
#define DSC_2_A_DSC_CTRL1_D_ODD_CTRL_BITS                          5
#define DSC_2_A_DSC_CTRL1_D_ODD_CTRL_SHIFT                         0


/****************************************************************************
 * dsc_2_A :: dsc_ctrl2
 ***************************************************************************/
/* dsc_2_A :: dsc_ctrl2 :: reserved_for_eco0 [15:15] */
#define DSC_2_A_DSC_CTRL2_RESERVED_FOR_ECO0_MASK                   0x8000
#define DSC_2_A_DSC_CTRL2_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC_2_A_DSC_CTRL2_RESERVED_FOR_ECO0_BITS                   1
#define DSC_2_A_DSC_CTRL2_RESERVED_FOR_ECO0_SHIFT                  15

/* dsc_2_A :: dsc_ctrl2 :: d_evn_ctrl [14:10] */
#define DSC_2_A_DSC_CTRL2_D_EVN_CTRL_MASK                          0x7c00
#define DSC_2_A_DSC_CTRL2_D_EVN_CTRL_ALIGN                         0
#define DSC_2_A_DSC_CTRL2_D_EVN_CTRL_BITS                          5
#define DSC_2_A_DSC_CTRL2_D_EVN_CTRL_SHIFT                         10

/* dsc_2_A :: dsc_ctrl2 :: m1_odd_ctrl [09:05] */
#define DSC_2_A_DSC_CTRL2_M1_ODD_CTRL_MASK                         0x03e0
#define DSC_2_A_DSC_CTRL2_M1_ODD_CTRL_ALIGN                        0
#define DSC_2_A_DSC_CTRL2_M1_ODD_CTRL_BITS                         5
#define DSC_2_A_DSC_CTRL2_M1_ODD_CTRL_SHIFT                        5

/* dsc_2_A :: dsc_ctrl2 :: m1_evn_ctrl [04:00] */
#define DSC_2_A_DSC_CTRL2_M1_EVN_CTRL_MASK                         0x001f
#define DSC_2_A_DSC_CTRL2_M1_EVN_CTRL_ALIGN                        0
#define DSC_2_A_DSC_CTRL2_M1_EVN_CTRL_BITS                         5
#define DSC_2_A_DSC_CTRL2_M1_EVN_CTRL_SHIFT                        0


/****************************************************************************
 * XGXS16G_USER_SerdesDigital
 ***************************************************************************/
/****************************************************************************
 * SerdesDigital :: Control1000X1
 ***************************************************************************/
/* SerdesDigital :: Control1000X1 :: reserved0 [15:15] */
#define SERDESDIGITAL_CONTROL1000X1_RESERVED0_MASK                 0x8000
#define SERDESDIGITAL_CONTROL1000X1_RESERVED0_ALIGN                0
#define SERDESDIGITAL_CONTROL1000X1_RESERVED0_BITS                 1
#define SERDESDIGITAL_CONTROL1000X1_RESERVED0_SHIFT                15

/* SerdesDigital :: Control1000X1 :: disable_signal_detect_filter [14:14] */
#define SERDESDIGITAL_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_MASK 0x4000
#define SERDESDIGITAL_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_ALIGN 0
#define SERDESDIGITAL_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_BITS 1
#define SERDESDIGITAL_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_SHIFT 14

/* SerdesDigital :: Control1000X1 :: master_mdio_phy_sel [13:13] */
#define SERDESDIGITAL_CONTROL1000X1_MASTER_MDIO_PHY_SEL_MASK       0x2000
#define SERDESDIGITAL_CONTROL1000X1_MASTER_MDIO_PHY_SEL_ALIGN      0
#define SERDESDIGITAL_CONTROL1000X1_MASTER_MDIO_PHY_SEL_BITS       1
#define SERDESDIGITAL_CONTROL1000X1_MASTER_MDIO_PHY_SEL_SHIFT      13

/* SerdesDigital :: Control1000X1 :: serdes_tx_amplitude_override [12:12] */
#define SERDESDIGITAL_CONTROL1000X1_SERDES_TX_AMPLITUDE_OVERRIDE_MASK 0x1000
#define SERDESDIGITAL_CONTROL1000X1_SERDES_TX_AMPLITUDE_OVERRIDE_ALIGN 0
#define SERDESDIGITAL_CONTROL1000X1_SERDES_TX_AMPLITUDE_OVERRIDE_BITS 1
#define SERDESDIGITAL_CONTROL1000X1_SERDES_TX_AMPLITUDE_OVERRIDE_SHIFT 12

/* SerdesDigital :: Control1000X1 :: sel_rx_pkts_for_cntr [11:11] */
#define SERDESDIGITAL_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_MASK      0x0800
#define SERDESDIGITAL_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_ALIGN     0
#define SERDESDIGITAL_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_BITS      1
#define SERDESDIGITAL_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_SHIFT     11

/* SerdesDigital :: Control1000X1 :: remote_loopback [10:10] */
#define SERDESDIGITAL_CONTROL1000X1_REMOTE_LOOPBACK_MASK           0x0400
#define SERDESDIGITAL_CONTROL1000X1_REMOTE_LOOPBACK_ALIGN          0
#define SERDESDIGITAL_CONTROL1000X1_REMOTE_LOOPBACK_BITS           1
#define SERDESDIGITAL_CONTROL1000X1_REMOTE_LOOPBACK_SHIFT          10

/* SerdesDigital :: Control1000X1 :: zero_comma_detector_phase [09:09] */
#define SERDESDIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_MASK 0x0200
#define SERDESDIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_ALIGN 0
#define SERDESDIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_BITS 1
#define SERDESDIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_SHIFT 9

/* SerdesDigital :: Control1000X1 :: comma_det_en [08:08] */
#define SERDESDIGITAL_CONTROL1000X1_COMMA_DET_EN_MASK              0x0100
#define SERDESDIGITAL_CONTROL1000X1_COMMA_DET_EN_ALIGN             0
#define SERDESDIGITAL_CONTROL1000X1_COMMA_DET_EN_BITS              1
#define SERDESDIGITAL_CONTROL1000X1_COMMA_DET_EN_SHIFT             8

/* SerdesDigital :: Control1000X1 :: crc_checker_disable [07:07] */
#define SERDESDIGITAL_CONTROL1000X1_CRC_CHECKER_DISABLE_MASK       0x0080
#define SERDESDIGITAL_CONTROL1000X1_CRC_CHECKER_DISABLE_ALIGN      0
#define SERDESDIGITAL_CONTROL1000X1_CRC_CHECKER_DISABLE_BITS       1
#define SERDESDIGITAL_CONTROL1000X1_CRC_CHECKER_DISABLE_SHIFT      7

/* SerdesDigital :: Control1000X1 :: disable_pll_pwrdwn [06:06] */
#define SERDESDIGITAL_CONTROL1000X1_DISABLE_PLL_PWRDWN_MASK        0x0040
#define SERDESDIGITAL_CONTROL1000X1_DISABLE_PLL_PWRDWN_ALIGN       0
#define SERDESDIGITAL_CONTROL1000X1_DISABLE_PLL_PWRDWN_BITS        1
#define SERDESDIGITAL_CONTROL1000X1_DISABLE_PLL_PWRDWN_SHIFT       6

/* SerdesDigital :: Control1000X1 :: sgmii_master_mode [05:05] */
#define SERDESDIGITAL_CONTROL1000X1_SGMII_MASTER_MODE_MASK         0x0020
#define SERDESDIGITAL_CONTROL1000X1_SGMII_MASTER_MODE_ALIGN        0
#define SERDESDIGITAL_CONTROL1000X1_SGMII_MASTER_MODE_BITS         1
#define SERDESDIGITAL_CONTROL1000X1_SGMII_MASTER_MODE_SHIFT        5

/* SerdesDigital :: Control1000X1 :: autodet_en [04:04] */
#define SERDESDIGITAL_CONTROL1000X1_AUTODET_EN_MASK                0x0010
#define SERDESDIGITAL_CONTROL1000X1_AUTODET_EN_ALIGN               0
#define SERDESDIGITAL_CONTROL1000X1_AUTODET_EN_BITS                1
#define SERDESDIGITAL_CONTROL1000X1_AUTODET_EN_SHIFT               4

/* SerdesDigital :: Control1000X1 :: invert_signal_detect [03:03] */
#define SERDESDIGITAL_CONTROL1000X1_INVERT_SIGNAL_DETECT_MASK      0x0008
#define SERDESDIGITAL_CONTROL1000X1_INVERT_SIGNAL_DETECT_ALIGN     0
#define SERDESDIGITAL_CONTROL1000X1_INVERT_SIGNAL_DETECT_BITS      1
#define SERDESDIGITAL_CONTROL1000X1_INVERT_SIGNAL_DETECT_SHIFT     3

/* SerdesDigital :: Control1000X1 :: signal_detect_en [02:02] */
#define SERDESDIGITAL_CONTROL1000X1_SIGNAL_DETECT_EN_MASK          0x0004
#define SERDESDIGITAL_CONTROL1000X1_SIGNAL_DETECT_EN_ALIGN         0
#define SERDESDIGITAL_CONTROL1000X1_SIGNAL_DETECT_EN_BITS          1
#define SERDESDIGITAL_CONTROL1000X1_SIGNAL_DETECT_EN_SHIFT         2

/* SerdesDigital :: Control1000X1 :: tbi_interface [01:01] */
#define SERDESDIGITAL_CONTROL1000X1_TBI_INTERFACE_MASK             0x0002
#define SERDESDIGITAL_CONTROL1000X1_TBI_INTERFACE_ALIGN            0
#define SERDESDIGITAL_CONTROL1000X1_TBI_INTERFACE_BITS             1
#define SERDESDIGITAL_CONTROL1000X1_TBI_INTERFACE_SHIFT            1

/* SerdesDigital :: Control1000X1 :: fiber_mode_1000X [00:00] */
#define SERDESDIGITAL_CONTROL1000X1_FIBER_MODE_1000X_MASK          0x0001
#define SERDESDIGITAL_CONTROL1000X1_FIBER_MODE_1000X_ALIGN         0
#define SERDESDIGITAL_CONTROL1000X1_FIBER_MODE_1000X_BITS          1
#define SERDESDIGITAL_CONTROL1000X1_FIBER_MODE_1000X_SHIFT         0


/****************************************************************************
 * SerdesDigital :: Control1000X2
 ***************************************************************************/
/* SerdesDigital :: Control1000X2 :: disable_extend_fdx_only [15:15] */
#define SERDESDIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_MASK   0x8000
#define SERDESDIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_ALIGN  0
#define SERDESDIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_BITS   1
#define SERDESDIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_SHIFT  15

/* SerdesDigital :: Control1000X2 :: clear_ber_counter [14:14] */
#define SERDESDIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_MASK         0x4000
#define SERDESDIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_ALIGN        0
#define SERDESDIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_BITS         1
#define SERDESDIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_SHIFT        14

/* SerdesDigital :: Control1000X2 :: transmit_idlejam_seq_test [13:13] */
#define SERDESDIGITAL_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_MASK 0x2000
#define SERDESDIGITAL_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_ALIGN 0
#define SERDESDIGITAL_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_BITS 1
#define SERDESDIGITAL_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_SHIFT 13

/* SerdesDigital :: Control1000X2 :: transmit_packet_seq_test [12:12] */
#define SERDESDIGITAL_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_MASK  0x1000
#define SERDESDIGITAL_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_ALIGN 0
#define SERDESDIGITAL_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_BITS  1
#define SERDESDIGITAL_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_SHIFT 12

/* SerdesDigital :: Control1000X2 :: test_cntr [11:11] */
#define SERDESDIGITAL_CONTROL1000X2_TEST_CNTR_MASK                 0x0800
#define SERDESDIGITAL_CONTROL1000X2_TEST_CNTR_ALIGN                0
#define SERDESDIGITAL_CONTROL1000X2_TEST_CNTR_BITS                 1
#define SERDESDIGITAL_CONTROL1000X2_TEST_CNTR_SHIFT                11

/* SerdesDigital :: Control1000X2 :: bypass_pcs_tx [10:10] */
#define SERDESDIGITAL_CONTROL1000X2_BYPASS_PCS_TX_MASK             0x0400
#define SERDESDIGITAL_CONTROL1000X2_BYPASS_PCS_TX_ALIGN            0
#define SERDESDIGITAL_CONTROL1000X2_BYPASS_PCS_TX_BITS             1
#define SERDESDIGITAL_CONTROL1000X2_BYPASS_PCS_TX_SHIFT            10

/* SerdesDigital :: Control1000X2 :: bypass_pcs_rx [09:09] */
#define SERDESDIGITAL_CONTROL1000X2_BYPASS_PCS_RX_MASK             0x0200
#define SERDESDIGITAL_CONTROL1000X2_BYPASS_PCS_RX_ALIGN            0
#define SERDESDIGITAL_CONTROL1000X2_BYPASS_PCS_RX_BITS             1
#define SERDESDIGITAL_CONTROL1000X2_BYPASS_PCS_RX_SHIFT            9

/* SerdesDigital :: Control1000X2 :: disable_TRRR_generation [08:08] */
#define SERDESDIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_MASK   0x0100
#define SERDESDIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_ALIGN  0
#define SERDESDIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_BITS   1
#define SERDESDIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_SHIFT  8

/* SerdesDigital :: Control1000X2 :: disable_carrier_extend [07:07] */
#define SERDESDIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_MASK    0x0080
#define SERDESDIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_ALIGN   0
#define SERDESDIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_BITS    1
#define SERDESDIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_SHIFT   7

/* SerdesDigital :: Control1000X2 :: autoneg_fast_timers [06:06] */
#define SERDESDIGITAL_CONTROL1000X2_AUTONEG_FAST_TIMERS_MASK       0x0040
#define SERDESDIGITAL_CONTROL1000X2_AUTONEG_FAST_TIMERS_ALIGN      0
#define SERDESDIGITAL_CONTROL1000X2_AUTONEG_FAST_TIMERS_BITS       1
#define SERDESDIGITAL_CONTROL1000X2_AUTONEG_FAST_TIMERS_SHIFT      6

/* SerdesDigital :: Control1000X2 :: force_xmit_data_on_txside [05:05] */
#define SERDESDIGITAL_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_MASK 0x0020
#define SERDESDIGITAL_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_ALIGN 0
#define SERDESDIGITAL_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_BITS 1
#define SERDESDIGITAL_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_SHIFT 5

/* SerdesDigital :: Control1000X2 :: disable_remote_fault_sensing [04:04] */
#define SERDESDIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_MASK 0x0010
#define SERDESDIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_ALIGN 0
#define SERDESDIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_BITS 1
#define SERDESDIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_SHIFT 4

/* SerdesDigital :: Control1000X2 :: enable_autoneg_err_timer [03:03] */
#define SERDESDIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_MASK  0x0008
#define SERDESDIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_ALIGN 0
#define SERDESDIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_BITS  1
#define SERDESDIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_SHIFT 3

/* SerdesDigital :: Control1000X2 :: filter_force_link [02:02] */
#define SERDESDIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_MASK         0x0004
#define SERDESDIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_ALIGN        0
#define SERDESDIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_BITS         1
#define SERDESDIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_SHIFT        2

/* SerdesDigital :: Control1000X2 :: disable_false_link [01:01] */
#define SERDESDIGITAL_CONTROL1000X2_DISABLE_FALSE_LINK_MASK        0x0002
#define SERDESDIGITAL_CONTROL1000X2_DISABLE_FALSE_LINK_ALIGN       0
#define SERDESDIGITAL_CONTROL1000X2_DISABLE_FALSE_LINK_BITS        1
#define SERDESDIGITAL_CONTROL1000X2_DISABLE_FALSE_LINK_SHIFT       1

/* SerdesDigital :: Control1000X2 :: enable_parallel_detection [00:00] */
#define SERDESDIGITAL_CONTROL1000X2_ENABLE_PARALLEL_DETECTION_MASK 0x0001
#define SERDESDIGITAL_CONTROL1000X2_ENABLE_PARALLEL_DETECTION_ALIGN 0
#define SERDESDIGITAL_CONTROL1000X2_ENABLE_PARALLEL_DETECTION_BITS 1
#define SERDESDIGITAL_CONTROL1000X2_ENABLE_PARALLEL_DETECTION_SHIFT 0


/****************************************************************************
 * SerdesDigital :: Control1000X3
 ***************************************************************************/
/* SerdesDigital :: Control1000X3 :: disable_packet_misalign [15:15] */
#define SERDESDIGITAL_CONTROL1000X3_DISABLE_PACKET_MISALIGN_MASK   0x8000
#define SERDESDIGITAL_CONTROL1000X3_DISABLE_PACKET_MISALIGN_ALIGN  0
#define SERDESDIGITAL_CONTROL1000X3_DISABLE_PACKET_MISALIGN_BITS   1
#define SERDESDIGITAL_CONTROL1000X3_DISABLE_PACKET_MISALIGN_SHIFT  15

/* SerdesDigital :: Control1000X3 :: rxfifo_gmii_reset [14:14] */
#define SERDESDIGITAL_CONTROL1000X3_RXFIFO_GMII_RESET_MASK         0x4000
#define SERDESDIGITAL_CONTROL1000X3_RXFIFO_GMII_RESET_ALIGN        0
#define SERDESDIGITAL_CONTROL1000X3_RXFIFO_GMII_RESET_BITS         1
#define SERDESDIGITAL_CONTROL1000X3_RXFIFO_GMII_RESET_SHIFT        14

/* SerdesDigital :: Control1000X3 :: disable_tx_crs [13:13] */
#define SERDESDIGITAL_CONTROL1000X3_DISABLE_TX_CRS_MASK            0x2000
#define SERDESDIGITAL_CONTROL1000X3_DISABLE_TX_CRS_ALIGN           0
#define SERDESDIGITAL_CONTROL1000X3_DISABLE_TX_CRS_BITS            1
#define SERDESDIGITAL_CONTROL1000X3_DISABLE_TX_CRS_SHIFT           13

/* SerdesDigital :: Control1000X3 :: invert_ext_phy_crs [12:12] */
#define SERDESDIGITAL_CONTROL1000X3_INVERT_EXT_PHY_CRS_MASK        0x1000
#define SERDESDIGITAL_CONTROL1000X3_INVERT_EXT_PHY_CRS_ALIGN       0
#define SERDESDIGITAL_CONTROL1000X3_INVERT_EXT_PHY_CRS_BITS        1
#define SERDESDIGITAL_CONTROL1000X3_INVERT_EXT_PHY_CRS_SHIFT       12

/* SerdesDigital :: Control1000X3 :: ext_phy_crs_mode [11:11] */
#define SERDESDIGITAL_CONTROL1000X3_EXT_PHY_CRS_MODE_MASK          0x0800
#define SERDESDIGITAL_CONTROL1000X3_EXT_PHY_CRS_MODE_ALIGN         0
#define SERDESDIGITAL_CONTROL1000X3_EXT_PHY_CRS_MODE_BITS          1
#define SERDESDIGITAL_CONTROL1000X3_EXT_PHY_CRS_MODE_SHIFT         11

/* SerdesDigital :: Control1000X3 :: jam_false_carrier_mode [10:10] */
#define SERDESDIGITAL_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_MASK    0x0400
#define SERDESDIGITAL_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_ALIGN   0
#define SERDESDIGITAL_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_BITS    1
#define SERDESDIGITAL_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_SHIFT   10

/* SerdesDigital :: Control1000X3 :: block_txen_mode [09:09] */
#define SERDESDIGITAL_CONTROL1000X3_BLOCK_TXEN_MODE_MASK           0x0200
#define SERDESDIGITAL_CONTROL1000X3_BLOCK_TXEN_MODE_ALIGN          0
#define SERDESDIGITAL_CONTROL1000X3_BLOCK_TXEN_MODE_BITS           1
#define SERDESDIGITAL_CONTROL1000X3_BLOCK_TXEN_MODE_SHIFT          9

/* SerdesDigital :: Control1000X3 :: force_txfifo_on [08:08] */
#define SERDESDIGITAL_CONTROL1000X3_FORCE_TXFIFO_ON_MASK           0x0100
#define SERDESDIGITAL_CONTROL1000X3_FORCE_TXFIFO_ON_ALIGN          0
#define SERDESDIGITAL_CONTROL1000X3_FORCE_TXFIFO_ON_BITS           1
#define SERDESDIGITAL_CONTROL1000X3_FORCE_TXFIFO_ON_SHIFT          8

/* SerdesDigital :: Control1000X3 :: bypass_txfifo1000 [07:07] */
#define SERDESDIGITAL_CONTROL1000X3_BYPASS_TXFIFO1000_MASK         0x0080
#define SERDESDIGITAL_CONTROL1000X3_BYPASS_TXFIFO1000_ALIGN        0
#define SERDESDIGITAL_CONTROL1000X3_BYPASS_TXFIFO1000_BITS         1
#define SERDESDIGITAL_CONTROL1000X3_BYPASS_TXFIFO1000_SHIFT        7

/* SerdesDigital :: Control1000X3 :: freq_lock_elasticity_tx [06:06] */
#define SERDESDIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_TX_MASK   0x0040
#define SERDESDIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_TX_ALIGN  0
#define SERDESDIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_TX_BITS   1
#define SERDESDIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_TX_SHIFT  6

/* SerdesDigital :: Control1000X3 :: freq_lock_elasticity_rx [05:05] */
#define SERDESDIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_RX_MASK   0x0020
#define SERDESDIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_RX_ALIGN  0
#define SERDESDIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_RX_BITS   1
#define SERDESDIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_RX_SHIFT  5

/* SerdesDigital :: Control1000X3 :: early_preamble_rx [04:04] */
#define SERDESDIGITAL_CONTROL1000X3_EARLY_PREAMBLE_RX_MASK         0x0010
#define SERDESDIGITAL_CONTROL1000X3_EARLY_PREAMBLE_RX_ALIGN        0
#define SERDESDIGITAL_CONTROL1000X3_EARLY_PREAMBLE_RX_BITS         1
#define SERDESDIGITAL_CONTROL1000X3_EARLY_PREAMBLE_RX_SHIFT        4

/* SerdesDigital :: Control1000X3 :: early_preamble_tx [03:03] */
#define SERDESDIGITAL_CONTROL1000X3_EARLY_PREAMBLE_TX_MASK         0x0008
#define SERDESDIGITAL_CONTROL1000X3_EARLY_PREAMBLE_TX_ALIGN        0
#define SERDESDIGITAL_CONTROL1000X3_EARLY_PREAMBLE_TX_BITS         1
#define SERDESDIGITAL_CONTROL1000X3_EARLY_PREAMBLE_TX_SHIFT        3

/* SerdesDigital :: Control1000X3 :: fifo_elasicity_tx_rx [02:01] */
#define SERDESDIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_RX_MASK      0x0006
#define SERDESDIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_RX_ALIGN     0
#define SERDESDIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_RX_BITS      2
#define SERDESDIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_RX_SHIFT     1

/* SerdesDigital :: Control1000X3 :: tx_fifo_rst [00:00] */
#define SERDESDIGITAL_CONTROL1000X3_TX_FIFO_RST_MASK               0x0001
#define SERDESDIGITAL_CONTROL1000X3_TX_FIFO_RST_ALIGN              0
#define SERDESDIGITAL_CONTROL1000X3_TX_FIFO_RST_BITS               1
#define SERDESDIGITAL_CONTROL1000X3_TX_FIFO_RST_SHIFT              0


/****************************************************************************
 * SerdesDigital :: Control1000X4
 ***************************************************************************/
/* SerdesDigital :: Control1000X4 :: reserved0 [15:14] */
#define SERDESDIGITAL_CONTROL1000X4_RESERVED0_MASK                 0xc000
#define SERDESDIGITAL_CONTROL1000X4_RESERVED0_ALIGN                0
#define SERDESDIGITAL_CONTROL1000X4_RESERVED0_BITS                 2
#define SERDESDIGITAL_CONTROL1000X4_RESERVED0_SHIFT                14

/* SerdesDigital :: Control1000X4 :: disable_resolution_err_restart [13:13] */
#define SERDESDIGITAL_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_MASK 0x2000
#define SERDESDIGITAL_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_ALIGN 0
#define SERDESDIGITAL_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_BITS 1
#define SERDESDIGITAL_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_SHIFT 13

/* SerdesDigital :: Control1000X4 :: enable_last_resolution_err [12:12] */
#define SERDESDIGITAL_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_MASK 0x1000
#define SERDESDIGITAL_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_ALIGN 0
#define SERDESDIGITAL_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_BITS 1
#define SERDESDIGITAL_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_SHIFT 12

/* SerdesDigital :: Control1000X4 :: tx_config_reg_sel [11:11] */
#define SERDESDIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_MASK         0x0800
#define SERDESDIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_ALIGN        0
#define SERDESDIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_BITS         1
#define SERDESDIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_SHIFT        11

/* SerdesDigital :: Control1000X4 :: zero_rxdgmii [10:10] */
#define SERDESDIGITAL_CONTROL1000X4_ZERO_RXDGMII_MASK              0x0400
#define SERDESDIGITAL_CONTROL1000X4_ZERO_RXDGMII_ALIGN             0
#define SERDESDIGITAL_CONTROL1000X4_ZERO_RXDGMII_BITS              1
#define SERDESDIGITAL_CONTROL1000X4_ZERO_RXDGMII_SHIFT             10

/* SerdesDigital :: Control1000X4 :: clear_linkdown [09:09] */
#define SERDESDIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_MASK            0x0200
#define SERDESDIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_ALIGN           0
#define SERDESDIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_BITS            1
#define SERDESDIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_SHIFT           9

/* SerdesDigital :: Control1000X4 :: latch_linkdown_enable [08:08] */
#define SERDESDIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_MASK     0x0100
#define SERDESDIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_ALIGN    0
#define SERDESDIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_BITS     1
#define SERDESDIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_SHIFT    8

/* SerdesDigital :: Control1000X4 :: link_force [07:07] */
#define SERDESDIGITAL_CONTROL1000X4_LINK_FORCE_MASK                0x0080
#define SERDESDIGITAL_CONTROL1000X4_LINK_FORCE_ALIGN               0
#define SERDESDIGITAL_CONTROL1000X4_LINK_FORCE_BITS                1
#define SERDESDIGITAL_CONTROL1000X4_LINK_FORCE_SHIFT               7

/* SerdesDigital :: Control1000X4 :: reserved1 [06:06] */
#define SERDESDIGITAL_CONTROL1000X4_RESERVED1_MASK                 0x0040
#define SERDESDIGITAL_CONTROL1000X4_RESERVED1_ALIGN                0
#define SERDESDIGITAL_CONTROL1000X4_RESERVED1_BITS                 1
#define SERDESDIGITAL_CONTROL1000X4_RESERVED1_SHIFT                6

/* SerdesDigital :: Control1000X4 :: lp_next_page_sel [05:05] */
#define SERDESDIGITAL_CONTROL1000X4_LP_NEXT_PAGE_SEL_MASK          0x0020
#define SERDESDIGITAL_CONTROL1000X4_LP_NEXT_PAGE_SEL_ALIGN         0
#define SERDESDIGITAL_CONTROL1000X4_LP_NEXT_PAGE_SEL_BITS          1
#define SERDESDIGITAL_CONTROL1000X4_LP_NEXT_PAGE_SEL_SHIFT         5

/* SerdesDigital :: Control1000X4 :: np_count_ClrnBp [04:04] */
#define SERDESDIGITAL_CONTROL1000X4_NP_COUNT_CLRNBP_MASK           0x0010
#define SERDESDIGITAL_CONTROL1000X4_NP_COUNT_CLRNBP_ALIGN          0
#define SERDESDIGITAL_CONTROL1000X4_NP_COUNT_CLRNBP_BITS           1
#define SERDESDIGITAL_CONTROL1000X4_NP_COUNT_CLRNBP_SHIFT          4

/* SerdesDigital :: Control1000X4 :: np_count_ClrnRd [03:03] */
#define SERDESDIGITAL_CONTROL1000X4_NP_COUNT_CLRNRD_MASK           0x0008
#define SERDESDIGITAL_CONTROL1000X4_NP_COUNT_CLRNRD_ALIGN          0
#define SERDESDIGITAL_CONTROL1000X4_NP_COUNT_CLRNRD_BITS           1
#define SERDESDIGITAL_CONTROL1000X4_NP_COUNT_CLRNRD_SHIFT          3

/* SerdesDigital :: Control1000X4 :: MiscRxStatus_sel [02:00] */
#define SERDESDIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_MASK          0x0007
#define SERDESDIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_ALIGN         0
#define SERDESDIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_BITS          3
#define SERDESDIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_SHIFT         0


/****************************************************************************
 * SerdesDigital :: Status1000X1
 ***************************************************************************/
/* SerdesDigital :: Status1000X1 :: txfifo_err_detected [15:15] */
#define SERDESDIGITAL_STATUS1000X1_TXFIFO_ERR_DETECTED_MASK        0x8000
#define SERDESDIGITAL_STATUS1000X1_TXFIFO_ERR_DETECTED_ALIGN       0
#define SERDESDIGITAL_STATUS1000X1_TXFIFO_ERR_DETECTED_BITS        1
#define SERDESDIGITAL_STATUS1000X1_TXFIFO_ERR_DETECTED_SHIFT       15

/* SerdesDigital :: Status1000X1 :: rxfifo_err_detected [14:14] */
#define SERDESDIGITAL_STATUS1000X1_RXFIFO_ERR_DETECTED_MASK        0x4000
#define SERDESDIGITAL_STATUS1000X1_RXFIFO_ERR_DETECTED_ALIGN       0
#define SERDESDIGITAL_STATUS1000X1_RXFIFO_ERR_DETECTED_BITS        1
#define SERDESDIGITAL_STATUS1000X1_RXFIFO_ERR_DETECTED_SHIFT       14

/* SerdesDigital :: Status1000X1 :: false_carrier_detected [13:13] */
#define SERDESDIGITAL_STATUS1000X1_FALSE_CARRIER_DETECTED_MASK     0x2000
#define SERDESDIGITAL_STATUS1000X1_FALSE_CARRIER_DETECTED_ALIGN    0
#define SERDESDIGITAL_STATUS1000X1_FALSE_CARRIER_DETECTED_BITS     1
#define SERDESDIGITAL_STATUS1000X1_FALSE_CARRIER_DETECTED_SHIFT    13

/* SerdesDigital :: Status1000X1 :: crc_err_detected [12:12] */
#define SERDESDIGITAL_STATUS1000X1_CRC_ERR_DETECTED_MASK           0x1000
#define SERDESDIGITAL_STATUS1000X1_CRC_ERR_DETECTED_ALIGN          0
#define SERDESDIGITAL_STATUS1000X1_CRC_ERR_DETECTED_BITS           1
#define SERDESDIGITAL_STATUS1000X1_CRC_ERR_DETECTED_SHIFT          12

/* SerdesDigital :: Status1000X1 :: tx_err_detected [11:11] */
#define SERDESDIGITAL_STATUS1000X1_TX_ERR_DETECTED_MASK            0x0800
#define SERDESDIGITAL_STATUS1000X1_TX_ERR_DETECTED_ALIGN           0
#define SERDESDIGITAL_STATUS1000X1_TX_ERR_DETECTED_BITS            1
#define SERDESDIGITAL_STATUS1000X1_TX_ERR_DETECTED_SHIFT           11

/* SerdesDigital :: Status1000X1 :: rx_err_detected [10:10] */
#define SERDESDIGITAL_STATUS1000X1_RX_ERR_DETECTED_MASK            0x0400
#define SERDESDIGITAL_STATUS1000X1_RX_ERR_DETECTED_ALIGN           0
#define SERDESDIGITAL_STATUS1000X1_RX_ERR_DETECTED_BITS            1
#define SERDESDIGITAL_STATUS1000X1_RX_ERR_DETECTED_SHIFT           10

/* SerdesDigital :: Status1000X1 :: carrier_extend_err_detected [09:09] */
#define SERDESDIGITAL_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_MASK 0x0200
#define SERDESDIGITAL_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_ALIGN 0
#define SERDESDIGITAL_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_BITS 1
#define SERDESDIGITAL_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_SHIFT 9

/* SerdesDigital :: Status1000X1 :: early_end_extension_detected [08:08] */
#define SERDESDIGITAL_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_MASK 0x0100
#define SERDESDIGITAL_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_ALIGN 0
#define SERDESDIGITAL_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_BITS 1
#define SERDESDIGITAL_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_SHIFT 8

/* SerdesDigital :: Status1000X1 :: link_status_change [07:07] */
#define SERDESDIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_MASK         0x0080
#define SERDESDIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_ALIGN        0
#define SERDESDIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_BITS         1
#define SERDESDIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_SHIFT        7

/* SerdesDigital :: Status1000X1 :: pause_resolution_rxside [06:06] */
#define SERDESDIGITAL_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_MASK    0x0040
#define SERDESDIGITAL_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_ALIGN   0
#define SERDESDIGITAL_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_BITS    1
#define SERDESDIGITAL_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_SHIFT   6

/* SerdesDigital :: Status1000X1 :: pause_resolution_txside [05:05] */
#define SERDESDIGITAL_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_MASK    0x0020
#define SERDESDIGITAL_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_ALIGN   0
#define SERDESDIGITAL_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_BITS    1
#define SERDESDIGITAL_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_SHIFT   5

/* SerdesDigital :: Status1000X1 :: speed_status [04:03] */
#define SERDESDIGITAL_STATUS1000X1_SPEED_STATUS_MASK               0x0018
#define SERDESDIGITAL_STATUS1000X1_SPEED_STATUS_ALIGN              0
#define SERDESDIGITAL_STATUS1000X1_SPEED_STATUS_BITS               2
#define SERDESDIGITAL_STATUS1000X1_SPEED_STATUS_SHIFT              3

/* SerdesDigital :: Status1000X1 :: duplex_status [02:02] */
#define SERDESDIGITAL_STATUS1000X1_DUPLEX_STATUS_MASK              0x0004
#define SERDESDIGITAL_STATUS1000X1_DUPLEX_STATUS_ALIGN             0
#define SERDESDIGITAL_STATUS1000X1_DUPLEX_STATUS_BITS              1
#define SERDESDIGITAL_STATUS1000X1_DUPLEX_STATUS_SHIFT             2

/* SerdesDigital :: Status1000X1 :: link_status [01:01] */
#define SERDESDIGITAL_STATUS1000X1_LINK_STATUS_MASK                0x0002
#define SERDESDIGITAL_STATUS1000X1_LINK_STATUS_ALIGN               0
#define SERDESDIGITAL_STATUS1000X1_LINK_STATUS_BITS                1
#define SERDESDIGITAL_STATUS1000X1_LINK_STATUS_SHIFT               1

/* SerdesDigital :: Status1000X1 :: sgmii_mode [00:00] */
#define SERDESDIGITAL_STATUS1000X1_SGMII_MODE_MASK                 0x0001
#define SERDESDIGITAL_STATUS1000X1_SGMII_MODE_ALIGN                0
#define SERDESDIGITAL_STATUS1000X1_SGMII_MODE_BITS                 1
#define SERDESDIGITAL_STATUS1000X1_SGMII_MODE_SHIFT                0


/****************************************************************************
 * SerdesDigital :: Status1000X2
 ***************************************************************************/
/* SerdesDigital :: Status1000X2 :: sgmii_mode_change [15:15] */
#define SERDESDIGITAL_STATUS1000X2_SGMII_MODE_CHANGE_MASK          0x8000
#define SERDESDIGITAL_STATUS1000X2_SGMII_MODE_CHANGE_ALIGN         0
#define SERDESDIGITAL_STATUS1000X2_SGMII_MODE_CHANGE_BITS          1
#define SERDESDIGITAL_STATUS1000X2_SGMII_MODE_CHANGE_SHIFT         15

/* SerdesDigital :: Status1000X2 :: consistency_mismatch [14:14] */
#define SERDESDIGITAL_STATUS1000X2_CONSISTENCY_MISMATCH_MASK       0x4000
#define SERDESDIGITAL_STATUS1000X2_CONSISTENCY_MISMATCH_ALIGN      0
#define SERDESDIGITAL_STATUS1000X2_CONSISTENCY_MISMATCH_BITS       1
#define SERDESDIGITAL_STATUS1000X2_CONSISTENCY_MISMATCH_SHIFT      14

/* SerdesDigital :: Status1000X2 :: autoneg_resolution_err [13:13] */
#define SERDESDIGITAL_STATUS1000X2_AUTONEG_RESOLUTION_ERR_MASK     0x2000
#define SERDESDIGITAL_STATUS1000X2_AUTONEG_RESOLUTION_ERR_ALIGN    0
#define SERDESDIGITAL_STATUS1000X2_AUTONEG_RESOLUTION_ERR_BITS     1
#define SERDESDIGITAL_STATUS1000X2_AUTONEG_RESOLUTION_ERR_SHIFT    13

/* SerdesDigital :: Status1000X2 :: sgmii_selector_mismatch [12:12] */
#define SERDESDIGITAL_STATUS1000X2_SGMII_SELECTOR_MISMATCH_MASK    0x1000
#define SERDESDIGITAL_STATUS1000X2_SGMII_SELECTOR_MISMATCH_ALIGN   0
#define SERDESDIGITAL_STATUS1000X2_SGMII_SELECTOR_MISMATCH_BITS    1
#define SERDESDIGITAL_STATUS1000X2_SGMII_SELECTOR_MISMATCH_SHIFT   12

/* SerdesDigital :: Status1000X2 :: sync_status_fail [11:11] */
#define SERDESDIGITAL_STATUS1000X2_SYNC_STATUS_FAIL_MASK           0x0800
#define SERDESDIGITAL_STATUS1000X2_SYNC_STATUS_FAIL_ALIGN          0
#define SERDESDIGITAL_STATUS1000X2_SYNC_STATUS_FAIL_BITS           1
#define SERDESDIGITAL_STATUS1000X2_SYNC_STATUS_FAIL_SHIFT          11

/* SerdesDigital :: Status1000X2 :: sync_status_ok [10:10] */
#define SERDESDIGITAL_STATUS1000X2_SYNC_STATUS_OK_MASK             0x0400
#define SERDESDIGITAL_STATUS1000X2_SYNC_STATUS_OK_ALIGN            0
#define SERDESDIGITAL_STATUS1000X2_SYNC_STATUS_OK_BITS             1
#define SERDESDIGITAL_STATUS1000X2_SYNC_STATUS_OK_SHIFT            10

/* SerdesDigital :: Status1000X2 :: rudi_c [09:09] */
#define SERDESDIGITAL_STATUS1000X2_RUDI_C_MASK                     0x0200
#define SERDESDIGITAL_STATUS1000X2_RUDI_C_ALIGN                    0
#define SERDESDIGITAL_STATUS1000X2_RUDI_C_BITS                     1
#define SERDESDIGITAL_STATUS1000X2_RUDI_C_SHIFT                    9

/* SerdesDigital :: Status1000X2 :: rudi_I [08:08] */
#define SERDESDIGITAL_STATUS1000X2_RUDI_I_MASK                     0x0100
#define SERDESDIGITAL_STATUS1000X2_RUDI_I_ALIGN                    0
#define SERDESDIGITAL_STATUS1000X2_RUDI_I_BITS                     1
#define SERDESDIGITAL_STATUS1000X2_RUDI_I_SHIFT                    8

/* SerdesDigital :: Status1000X2 :: rudi_invalid [07:07] */
#define SERDESDIGITAL_STATUS1000X2_RUDI_INVALID_MASK               0x0080
#define SERDESDIGITAL_STATUS1000X2_RUDI_INVALID_ALIGN              0
#define SERDESDIGITAL_STATUS1000X2_RUDI_INVALID_BITS               1
#define SERDESDIGITAL_STATUS1000X2_RUDI_INVALID_SHIFT              7

/* SerdesDigital :: Status1000X2 :: linkDown_syncLoss [06:06] */
#define SERDESDIGITAL_STATUS1000X2_LINKDOWN_SYNCLOSS_MASK          0x0040
#define SERDESDIGITAL_STATUS1000X2_LINKDOWN_SYNCLOSS_ALIGN         0
#define SERDESDIGITAL_STATUS1000X2_LINKDOWN_SYNCLOSS_BITS          1
#define SERDESDIGITAL_STATUS1000X2_LINKDOWN_SYNCLOSS_SHIFT         6

/* SerdesDigital :: Status1000X2 :: idle_detect_state [05:05] */
#define SERDESDIGITAL_STATUS1000X2_IDLE_DETECT_STATE_MASK          0x0020
#define SERDESDIGITAL_STATUS1000X2_IDLE_DETECT_STATE_ALIGN         0
#define SERDESDIGITAL_STATUS1000X2_IDLE_DETECT_STATE_BITS          1
#define SERDESDIGITAL_STATUS1000X2_IDLE_DETECT_STATE_SHIFT         5

/* SerdesDigital :: Status1000X2 :: complete_acknowledge_state [04:04] */
#define SERDESDIGITAL_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_MASK 0x0010
#define SERDESDIGITAL_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_ALIGN 0
#define SERDESDIGITAL_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_BITS 1
#define SERDESDIGITAL_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_SHIFT 4

/* SerdesDigital :: Status1000X2 :: acknowledge_detect_state [03:03] */
#define SERDESDIGITAL_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_MASK   0x0008
#define SERDESDIGITAL_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_ALIGN  0
#define SERDESDIGITAL_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_BITS   1
#define SERDESDIGITAL_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_SHIFT  3

/* SerdesDigital :: Status1000X2 :: ability_detect_state [02:02] */
#define SERDESDIGITAL_STATUS1000X2_ABILITY_DETECT_STATE_MASK       0x0004
#define SERDESDIGITAL_STATUS1000X2_ABILITY_DETECT_STATE_ALIGN      0
#define SERDESDIGITAL_STATUS1000X2_ABILITY_DETECT_STATE_BITS       1
#define SERDESDIGITAL_STATUS1000X2_ABILITY_DETECT_STATE_SHIFT      2

/* union - case anError [01:01] */
/* SerdesDigital :: Status1000X2 :: an_error_state [01:01] */
#define SERDESDIGITAL_STATUS1000X2_ANERROR_AN_ERROR_STATE_MASK     0x0002
#define SERDESDIGITAL_STATUS1000X2_ANERROR_AN_ERROR_STATE_ALIGN    0
#define SERDESDIGITAL_STATUS1000X2_ANERROR_AN_ERROR_STATE_BITS     1
#define SERDESDIGITAL_STATUS1000X2_ANERROR_AN_ERROR_STATE_SHIFT    1


/* union - case anDisableLink [01:01] */
/* SerdesDigital :: Status1000X2 :: an_disable_link_ok_state [01:01] */
#define SERDESDIGITAL_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_MASK 0x0002
#define SERDESDIGITAL_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_ALIGN 0
#define SERDESDIGITAL_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_BITS 1
#define SERDESDIGITAL_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_SHIFT 1


/* SerdesDigital :: Status1000X2 :: an_enable_state [00:00] */
#define SERDESDIGITAL_STATUS1000X2_AN_ENABLE_STATE_MASK            0x0001
#define SERDESDIGITAL_STATUS1000X2_AN_ENABLE_STATE_ALIGN           0
#define SERDESDIGITAL_STATUS1000X2_AN_ENABLE_STATE_BITS            1
#define SERDESDIGITAL_STATUS1000X2_AN_ENABLE_STATE_SHIFT           0


/****************************************************************************
 * SerdesDigital :: Status1000X3
 ***************************************************************************/
/* SerdesDigital :: Status1000X3 :: reserved0 [15:13] */
#define SERDESDIGITAL_STATUS1000X3_RESERVED0_MASK                  0xe000
#define SERDESDIGITAL_STATUS1000X3_RESERVED0_ALIGN                 0
#define SERDESDIGITAL_STATUS1000X3_RESERVED0_BITS                  3
#define SERDESDIGITAL_STATUS1000X3_RESERVED0_SHIFT                 13

/* SerdesDigital :: Status1000X3 :: pd_park_an [12:12] */
#define SERDESDIGITAL_STATUS1000X3_PD_PARK_AN_MASK                 0x1000
#define SERDESDIGITAL_STATUS1000X3_PD_PARK_AN_ALIGN                0
#define SERDESDIGITAL_STATUS1000X3_PD_PARK_AN_BITS                 1
#define SERDESDIGITAL_STATUS1000X3_PD_PARK_AN_SHIFT                12

/* SerdesDigital :: Status1000X3 :: remotePhy_autosel [11:11] */
#define SERDESDIGITAL_STATUS1000X3_REMOTEPHY_AUTOSEL_MASK          0x0800
#define SERDESDIGITAL_STATUS1000X3_REMOTEPHY_AUTOSEL_ALIGN         0
#define SERDESDIGITAL_STATUS1000X3_REMOTEPHY_AUTOSEL_BITS          1
#define SERDESDIGITAL_STATUS1000X3_REMOTEPHY_AUTOSEL_SHIFT         11

/* SerdesDigital :: Status1000X3 :: latch_linkdown [10:10] */
#define SERDESDIGITAL_STATUS1000X3_LATCH_LINKDOWN_MASK             0x0400
#define SERDESDIGITAL_STATUS1000X3_LATCH_LINKDOWN_ALIGN            0
#define SERDESDIGITAL_STATUS1000X3_LATCH_LINKDOWN_BITS             1
#define SERDESDIGITAL_STATUS1000X3_LATCH_LINKDOWN_SHIFT            10

/* SerdesDigital :: Status1000X3 :: sd_filter [09:09] */
#define SERDESDIGITAL_STATUS1000X3_SD_FILTER_MASK                  0x0200
#define SERDESDIGITAL_STATUS1000X3_SD_FILTER_ALIGN                 0
#define SERDESDIGITAL_STATUS1000X3_SD_FILTER_BITS                  1
#define SERDESDIGITAL_STATUS1000X3_SD_FILTER_SHIFT                 9

/* SerdesDigital :: Status1000X3 :: sd_mux [08:08] */
#define SERDESDIGITAL_STATUS1000X3_SD_MUX_MASK                     0x0100
#define SERDESDIGITAL_STATUS1000X3_SD_MUX_ALIGN                    0
#define SERDESDIGITAL_STATUS1000X3_SD_MUX_BITS                     1
#define SERDESDIGITAL_STATUS1000X3_SD_MUX_SHIFT                    8

/* SerdesDigital :: Status1000X3 :: sd_filter_chg [07:07] */
#define SERDESDIGITAL_STATUS1000X3_SD_FILTER_CHG_MASK              0x0080
#define SERDESDIGITAL_STATUS1000X3_SD_FILTER_CHG_ALIGN             0
#define SERDESDIGITAL_STATUS1000X3_SD_FILTER_CHG_BITS              1
#define SERDESDIGITAL_STATUS1000X3_SD_FILTER_CHG_SHIFT             7

/* SerdesDigital :: Status1000X3 :: reserved1 [06:00] */
#define SERDESDIGITAL_STATUS1000X3_RESERVED1_MASK                  0x007f
#define SERDESDIGITAL_STATUS1000X3_RESERVED1_ALIGN                 0
#define SERDESDIGITAL_STATUS1000X3_RESERVED1_BITS                  7
#define SERDESDIGITAL_STATUS1000X3_RESERVED1_SHIFT                 0


/****************************************************************************
 * SerdesDigital :: CrcErr_RxPkt
 ***************************************************************************/
/* SerdesDigital :: CrcErr_RxPkt :: badCodeGroups [15:08] */
#define SERDESDIGITAL_CRCERR_RXPKT_BADCODEGROUPS_MASK              0xff00
#define SERDESDIGITAL_CRCERR_RXPKT_BADCODEGROUPS_ALIGN             0
#define SERDESDIGITAL_CRCERR_RXPKT_BADCODEGROUPS_BITS              8
#define SERDESDIGITAL_CRCERR_RXPKT_BADCODEGROUPS_SHIFT             8

/* SerdesDigital :: CrcErr_RxPkt :: crcErr_rxPkt [07:00] */
#define SERDESDIGITAL_CRCERR_RXPKT_CRCERR_RXPKT_MASK               0x00ff
#define SERDESDIGITAL_CRCERR_RXPKT_CRCERR_RXPKT_ALIGN              0
#define SERDESDIGITAL_CRCERR_RXPKT_CRCERR_RXPKT_BITS               8
#define SERDESDIGITAL_CRCERR_RXPKT_CRCERR_RXPKT_SHIFT              0


/****************************************************************************
 * SerdesDigital :: Misc1
 ***************************************************************************/
/* SerdesDigital :: Misc1 :: refclk_sel [15:13] */
#define SERDESDIGITAL_MISC1_REFCLK_SEL_MASK                        0xe000
#define SERDESDIGITAL_MISC1_REFCLK_SEL_ALIGN                       0
#define SERDESDIGITAL_MISC1_REFCLK_SEL_BITS                        3
#define SERDESDIGITAL_MISC1_REFCLK_SEL_SHIFT                       13

/* SerdesDigital :: Misc1 :: force_pll_mode_afe_sel [12:12] */
#define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_SEL_MASK            0x1000
#define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_SEL_ALIGN           0
#define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_SEL_BITS            1
#define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_SEL_SHIFT           12

/* SerdesDigital :: Misc1 :: force_pll_mode_afe [11:08] */
#define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_MASK                0x0f00
#define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_ALIGN               0
#define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_BITS                4
#define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_SHIFT               8

/* SerdesDigital :: Misc1 :: reserved0 [07:07] */
#define SERDESDIGITAL_MISC1_RESERVED0_MASK                         0x0080
#define SERDESDIGITAL_MISC1_RESERVED0_ALIGN                        0
#define SERDESDIGITAL_MISC1_RESERVED0_BITS                         1
#define SERDESDIGITAL_MISC1_RESERVED0_SHIFT                        7

/* SerdesDigital :: Misc1 :: tx_underrun_1000_dis [06:06] */
#define SERDESDIGITAL_MISC1_TX_UNDERRUN_1000_DIS_MASK              0x0040
#define SERDESDIGITAL_MISC1_TX_UNDERRUN_1000_DIS_ALIGN             0
#define SERDESDIGITAL_MISC1_TX_UNDERRUN_1000_DIS_BITS              1
#define SERDESDIGITAL_MISC1_TX_UNDERRUN_1000_DIS_SHIFT             6

/* SerdesDigital :: Misc1 :: force_ln_mode [05:05] */
#define SERDESDIGITAL_MISC1_FORCE_LN_MODE_MASK                     0x0020
#define SERDESDIGITAL_MISC1_FORCE_LN_MODE_ALIGN                    0
#define SERDESDIGITAL_MISC1_FORCE_LN_MODE_BITS                     1
#define SERDESDIGITAL_MISC1_FORCE_LN_MODE_SHIFT                    5

/* SerdesDigital :: Misc1 :: force_speed_sel [04:04] */
#define SERDESDIGITAL_MISC1_FORCE_SPEED_SEL_MASK                   0x0010
#define SERDESDIGITAL_MISC1_FORCE_SPEED_SEL_ALIGN                  0
#define SERDESDIGITAL_MISC1_FORCE_SPEED_SEL_BITS                   1
#define SERDESDIGITAL_MISC1_FORCE_SPEED_SEL_SHIFT                  4

/* SerdesDigital :: Misc1 :: force_speed [03:00] */
#define SERDESDIGITAL_MISC1_FORCE_SPEED_MASK                       0x000f
#define SERDESDIGITAL_MISC1_FORCE_SPEED_ALIGN                      0
#define SERDESDIGITAL_MISC1_FORCE_SPEED_BITS                       4
#define SERDESDIGITAL_MISC1_FORCE_SPEED_SHIFT                      0


/****************************************************************************
 * SerdesDigital :: Misc2
 ***************************************************************************/
/* SerdesDigital :: Misc2 :: rxckpl_sel_combo [15:15] */
#define SERDESDIGITAL_MISC2_RXCKPL_SEL_COMBO_MASK                  0x8000
#define SERDESDIGITAL_MISC2_RXCKPL_SEL_COMBO_ALIGN                 0
#define SERDESDIGITAL_MISC2_RXCKPL_SEL_COMBO_BITS                  1
#define SERDESDIGITAL_MISC2_RXCKPL_SEL_COMBO_SHIFT                 15

/* SerdesDigital :: Misc2 :: rxck_mii_gen_sel_force [14:14] */
#define SERDESDIGITAL_MISC2_RXCK_MII_GEN_SEL_FORCE_MASK            0x4000
#define SERDESDIGITAL_MISC2_RXCK_MII_GEN_SEL_FORCE_ALIGN           0
#define SERDESDIGITAL_MISC2_RXCK_MII_GEN_SEL_FORCE_BITS            1
#define SERDESDIGITAL_MISC2_RXCK_MII_GEN_SEL_FORCE_SHIFT           14

/* SerdesDigital :: Misc2 :: rxck_mii_gen_sel_val [13:13] */
#define SERDESDIGITAL_MISC2_RXCK_MII_GEN_SEL_VAL_MASK              0x2000
#define SERDESDIGITAL_MISC2_RXCK_MII_GEN_SEL_VAL_ALIGN             0
#define SERDESDIGITAL_MISC2_RXCK_MII_GEN_SEL_VAL_BITS              1
#define SERDESDIGITAL_MISC2_RXCK_MII_GEN_SEL_VAL_SHIFT             13

/* SerdesDigital :: Misc2 :: rlpbk_sw_force [12:12] */
#define SERDESDIGITAL_MISC2_RLPBK_SW_FORCE_MASK                    0x1000
#define SERDESDIGITAL_MISC2_RLPBK_SW_FORCE_ALIGN                   0
#define SERDESDIGITAL_MISC2_RLPBK_SW_FORCE_BITS                    1
#define SERDESDIGITAL_MISC2_RLPBK_SW_FORCE_SHIFT                   12

/* SerdesDigital :: Misc2 :: rlpbk_RxRst_en [11:11] */
#define SERDESDIGITAL_MISC2_RLPBK_RXRST_EN_MASK                    0x0800
#define SERDESDIGITAL_MISC2_RLPBK_RXRST_EN_ALIGN                   0
#define SERDESDIGITAL_MISC2_RLPBK_RXRST_EN_BITS                    1
#define SERDESDIGITAL_MISC2_RLPBK_RXRST_EN_SHIFT                   11

/* SerdesDigital :: Misc2 :: clkSigdet_bypass [10:10] */
#define SERDESDIGITAL_MISC2_CLKSIGDET_BYPASS_MASK                  0x0400
#define SERDESDIGITAL_MISC2_CLKSIGDET_BYPASS_ALIGN                 0
#define SERDESDIGITAL_MISC2_CLKSIGDET_BYPASS_BITS                  1
#define SERDESDIGITAL_MISC2_CLKSIGDET_BYPASS_SHIFT                 10

/* SerdesDigital :: Misc2 :: clk41_bypass [09:09] */
#define SERDESDIGITAL_MISC2_CLK41_BYPASS_MASK                      0x0200
#define SERDESDIGITAL_MISC2_CLK41_BYPASS_ALIGN                     0
#define SERDESDIGITAL_MISC2_CLK41_BYPASS_BITS                      1
#define SERDESDIGITAL_MISC2_CLK41_BYPASS_SHIFT                     9

/* SerdesDigital :: Misc2 :: reserved0 [08:06] */
#define SERDESDIGITAL_MISC2_RESERVED0_MASK                         0x01c0
#define SERDESDIGITAL_MISC2_RESERVED0_ALIGN                        0
#define SERDESDIGITAL_MISC2_RESERVED0_BITS                         3
#define SERDESDIGITAL_MISC2_RESERVED0_SHIFT                        6

/* SerdesDigital :: Misc2 :: pma_pmd_forced_speed_enc_en [05:05] */
#define SERDESDIGITAL_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_MASK       0x0020
#define SERDESDIGITAL_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_ALIGN      0
#define SERDESDIGITAL_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_BITS       1
#define SERDESDIGITAL_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_SHIFT      5

/* SerdesDigital :: Misc2 :: fifo_err_cya [04:04] */
#define SERDESDIGITAL_MISC2_FIFO_ERR_CYA_MASK                      0x0010
#define SERDESDIGITAL_MISC2_FIFO_ERR_CYA_ALIGN                     0
#define SERDESDIGITAL_MISC2_FIFO_ERR_CYA_BITS                      1
#define SERDESDIGITAL_MISC2_FIFO_ERR_CYA_SHIFT                     4

/* SerdesDigital :: Misc2 :: an_txdisablePhase [03:03] */
#define SERDESDIGITAL_MISC2_AN_TXDISABLEPHASE_MASK                 0x0008
#define SERDESDIGITAL_MISC2_AN_TXDISABLEPHASE_ALIGN                0
#define SERDESDIGITAL_MISC2_AN_TXDISABLEPHASE_BITS                 1
#define SERDESDIGITAL_MISC2_AN_TXDISABLEPHASE_SHIFT                3

/* SerdesDigital :: Misc2 :: an_rxSeqStartDis [02:02] */
#define SERDESDIGITAL_MISC2_AN_RXSEQSTARTDIS_MASK                  0x0004
#define SERDESDIGITAL_MISC2_AN_RXSEQSTARTDIS_ALIGN                 0
#define SERDESDIGITAL_MISC2_AN_RXSEQSTARTDIS_BITS                  1
#define SERDESDIGITAL_MISC2_AN_RXSEQSTARTDIS_SHIFT                 2

/* SerdesDigital :: Misc2 :: an_txdisable_ln [01:01] */
#define SERDESDIGITAL_MISC2_AN_TXDISABLE_LN_MASK                   0x0002
#define SERDESDIGITAL_MISC2_AN_TXDISABLE_LN_ALIGN                  0
#define SERDESDIGITAL_MISC2_AN_TXDISABLE_LN_BITS                   1
#define SERDESDIGITAL_MISC2_AN_TXDISABLE_LN_SHIFT                  1

/* SerdesDigital :: Misc2 :: an_deadTrap [00:00] */
#define SERDESDIGITAL_MISC2_AN_DEADTRAP_MASK                       0x0001
#define SERDESDIGITAL_MISC2_AN_DEADTRAP_ALIGN                      0
#define SERDESDIGITAL_MISC2_AN_DEADTRAP_BITS                       1
#define SERDESDIGITAL_MISC2_AN_DEADTRAP_SHIFT                      0


/****************************************************************************
 * SerdesDigital :: PatGenCtrl
 ***************************************************************************/
/* SerdesDigital :: PatGenCtrl :: reserved0 [15:15] */
#define SERDESDIGITAL_PATGENCTRL_RESERVED0_MASK                    0x8000
#define SERDESDIGITAL_PATGENCTRL_RESERVED0_ALIGN                   0
#define SERDESDIGITAL_PATGENCTRL_RESERVED0_BITS                    1
#define SERDESDIGITAL_PATGENCTRL_RESERVED0_SHIFT                   15

/* SerdesDigital :: PatGenCtrl :: tx_err [14:14] */
#define SERDESDIGITAL_PATGENCTRL_TX_ERR_MASK                       0x4000
#define SERDESDIGITAL_PATGENCTRL_TX_ERR_ALIGN                      0
#define SERDESDIGITAL_PATGENCTRL_TX_ERR_BITS                       1
#define SERDESDIGITAL_PATGENCTRL_TX_ERR_SHIFT                      14

/* SerdesDigital :: PatGenCtrl :: skip_crc [13:13] */
#define SERDESDIGITAL_PATGENCTRL_SKIP_CRC_MASK                     0x2000
#define SERDESDIGITAL_PATGENCTRL_SKIP_CRC_ALIGN                    0
#define SERDESDIGITAL_PATGENCTRL_SKIP_CRC_BITS                     1
#define SERDESDIGITAL_PATGENCTRL_SKIP_CRC_SHIFT                    13

/* SerdesDigital :: PatGenCtrl :: en_crc_checker_fragment_err_det [12:12] */
#define SERDESDIGITAL_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_MASK 0x1000
#define SERDESDIGITAL_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_ALIGN 0
#define SERDESDIGITAL_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_BITS 1
#define SERDESDIGITAL_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_SHIFT 12

/* SerdesDigital :: PatGenCtrl :: ipg_select [11:09] */
#define SERDESDIGITAL_PATGENCTRL_IPG_SELECT_MASK                   0x0e00
#define SERDESDIGITAL_PATGENCTRL_IPG_SELECT_ALIGN                  0
#define SERDESDIGITAL_PATGENCTRL_IPG_SELECT_BITS                   3
#define SERDESDIGITAL_PATGENCTRL_IPG_SELECT_SHIFT                  9

/* SerdesDigital :: PatGenCtrl :: pkt_size [08:03] */
#define SERDESDIGITAL_PATGENCTRL_PKT_SIZE_MASK                     0x01f8
#define SERDESDIGITAL_PATGENCTRL_PKT_SIZE_ALIGN                    0
#define SERDESDIGITAL_PATGENCTRL_PKT_SIZE_BITS                     6
#define SERDESDIGITAL_PATGENCTRL_PKT_SIZE_SHIFT                    3

/* SerdesDigital :: PatGenCtrl :: single_pass_mode [02:02] */
#define SERDESDIGITAL_PATGENCTRL_SINGLE_PASS_MODE_MASK             0x0004
#define SERDESDIGITAL_PATGENCTRL_SINGLE_PASS_MODE_ALIGN            0
#define SERDESDIGITAL_PATGENCTRL_SINGLE_PASS_MODE_BITS             1
#define SERDESDIGITAL_PATGENCTRL_SINGLE_PASS_MODE_SHIFT            2

/* SerdesDigital :: PatGenCtrl :: run_pattern_gen [01:01] */
#define SERDESDIGITAL_PATGENCTRL_RUN_PATTERN_GEN_MASK              0x0002
#define SERDESDIGITAL_PATGENCTRL_RUN_PATTERN_GEN_ALIGN             0
#define SERDESDIGITAL_PATGENCTRL_RUN_PATTERN_GEN_BITS              1
#define SERDESDIGITAL_PATGENCTRL_RUN_PATTERN_GEN_SHIFT             1

/* SerdesDigital :: PatGenCtrl :: sel_pattern_gen_data [00:00] */
#define SERDESDIGITAL_PATGENCTRL_SEL_PATTERN_GEN_DATA_MASK         0x0001
#define SERDESDIGITAL_PATGENCTRL_SEL_PATTERN_GEN_DATA_ALIGN        0
#define SERDESDIGITAL_PATGENCTRL_SEL_PATTERN_GEN_DATA_BITS         1
#define SERDESDIGITAL_PATGENCTRL_SEL_PATTERN_GEN_DATA_SHIFT        0


/****************************************************************************
 * SerdesDigital :: PatGenStat
 ***************************************************************************/
/* SerdesDigital :: PatGenStat :: reserved0 [15:04] */
#define SERDESDIGITAL_PATGENSTAT_RESERVED0_MASK                    0xfff0
#define SERDESDIGITAL_PATGENSTAT_RESERVED0_ALIGN                   0
#define SERDESDIGITAL_PATGENSTAT_RESERVED0_BITS                    12
#define SERDESDIGITAL_PATGENSTAT_RESERVED0_SHIFT                   4

/* SerdesDigital :: PatGenStat :: pattern_gen_active [03:03] */
#define SERDESDIGITAL_PATGENSTAT_PATTERN_GEN_ACTIVE_MASK           0x0008
#define SERDESDIGITAL_PATGENSTAT_PATTERN_GEN_ACTIVE_ALIGN          0
#define SERDESDIGITAL_PATGENSTAT_PATTERN_GEN_ACTIVE_BITS           1
#define SERDESDIGITAL_PATGENSTAT_PATTERN_GEN_ACTIVE_SHIFT          3

/* SerdesDigital :: PatGenStat :: pattern_gen_fsm [02:00] */
#define SERDESDIGITAL_PATGENSTAT_PATTERN_GEN_FSM_MASK              0x0007
#define SERDESDIGITAL_PATGENSTAT_PATTERN_GEN_FSM_ALIGN             0
#define SERDESDIGITAL_PATGENSTAT_PATTERN_GEN_FSM_BITS              3
#define SERDESDIGITAL_PATGENSTAT_PATTERN_GEN_FSM_SHIFT             0


/****************************************************************************
 * SerdesDigital :: TestMode
 ***************************************************************************/
/* SerdesDigital :: TestMode :: disable_reset_cnt [15:15] */
#define SERDESDIGITAL_TESTMODE_DISABLE_RESET_CNT_MASK              0x8000
#define SERDESDIGITAL_TESTMODE_DISABLE_RESET_CNT_ALIGN             0
#define SERDESDIGITAL_TESTMODE_DISABLE_RESET_CNT_BITS              1
#define SERDESDIGITAL_TESTMODE_DISABLE_RESET_CNT_SHIFT             15

/* SerdesDigital :: TestMode :: clear_packet_counters [14:14] */
#define SERDESDIGITAL_TESTMODE_CLEAR_PACKET_COUNTERS_MASK          0x4000
#define SERDESDIGITAL_TESTMODE_CLEAR_PACKET_COUNTERS_ALIGN         0
#define SERDESDIGITAL_TESTMODE_CLEAR_PACKET_COUNTERS_BITS          1
#define SERDESDIGITAL_TESTMODE_CLEAR_PACKET_COUNTERS_SHIFT         14

/* SerdesDigital :: TestMode :: reserved0 [13:12] */
#define SERDESDIGITAL_TESTMODE_RESERVED0_MASK                      0x3000
#define SERDESDIGITAL_TESTMODE_RESERVED0_ALIGN                     0
#define SERDESDIGITAL_TESTMODE_RESERVED0_BITS                      2
#define SERDESDIGITAL_TESTMODE_RESERVED0_SHIFT                     12

/* SerdesDigital :: TestMode :: test_monitor_mode2 [11:06] */
#define SERDESDIGITAL_TESTMODE_TEST_MONITOR_MODE2_MASK             0x0fc0
#define SERDESDIGITAL_TESTMODE_TEST_MONITOR_MODE2_ALIGN            0
#define SERDESDIGITAL_TESTMODE_TEST_MONITOR_MODE2_BITS             6
#define SERDESDIGITAL_TESTMODE_TEST_MONITOR_MODE2_SHIFT            6

/* SerdesDigital :: TestMode :: test_monitor_mode1 [05:00] */
#define SERDESDIGITAL_TESTMODE_TEST_MONITOR_MODE1_MASK             0x003f
#define SERDESDIGITAL_TESTMODE_TEST_MONITOR_MODE1_ALIGN            0
#define SERDESDIGITAL_TESTMODE_TEST_MONITOR_MODE1_BITS             6
#define SERDESDIGITAL_TESTMODE_TEST_MONITOR_MODE1_SHIFT            0


/****************************************************************************
 * SerdesDigital :: TxPktCnt
 ***************************************************************************/
/* SerdesDigital :: TxPktCnt :: TxPktCnt [15:00] */
#define SERDESDIGITAL_TXPKTCNT_TXPKTCNT_MASK                       0xffff
#define SERDESDIGITAL_TXPKTCNT_TXPKTCNT_ALIGN                      0
#define SERDESDIGITAL_TXPKTCNT_TXPKTCNT_BITS                       16
#define SERDESDIGITAL_TXPKTCNT_TXPKTCNT_SHIFT                      0


/****************************************************************************
 * SerdesDigital :: RxPktCnt
 ***************************************************************************/
/* SerdesDigital :: RxPktCnt :: RxPktCnt [15:00] */
#define SERDESDIGITAL_RXPKTCNT_RXPKTCNT_MASK                       0xffff
#define SERDESDIGITAL_RXPKTCNT_RXPKTCNT_ALIGN                      0
#define SERDESDIGITAL_RXPKTCNT_RXPKTCNT_BITS                       16
#define SERDESDIGITAL_RXPKTCNT_RXPKTCNT_SHIFT                      0


/****************************************************************************
 * XGXS16G_USER_serdesID
 ***************************************************************************/
/****************************************************************************
 * serdesID :: serdesID0
 ***************************************************************************/
/* serdesID :: serdesID0 :: rev_letter [15:14] */
#define SERDESID_SERDESID0_REV_LETTER_MASK                         0xc000
#define SERDESID_SERDESID0_REV_LETTER_ALIGN                        0
#define SERDESID_SERDESID0_REV_LETTER_BITS                         2
#define SERDESID_SERDESID0_REV_LETTER_SHIFT                        14

/* serdesID :: serdesID0 :: rev_number [13:11] */
#define SERDESID_SERDESID0_REV_NUMBER_MASK                         0x3800
#define SERDESID_SERDESID0_REV_NUMBER_ALIGN                        0
#define SERDESID_SERDESID0_REV_NUMBER_BITS                         3
#define SERDESID_SERDESID0_REV_NUMBER_SHIFT                        11

/* serdesID :: serdesID0 :: bonding [10:09] */
#define SERDESID_SERDESID0_BONDING_MASK                            0x0600
#define SERDESID_SERDESID0_BONDING_ALIGN                           0
#define SERDESID_SERDESID0_BONDING_BITS                            2
#define SERDESID_SERDESID0_BONDING_SHIFT                           9

/* serdesID :: serdesID0 :: tech_proc [08:06] */
#define SERDESID_SERDESID0_TECH_PROC_MASK                          0x01c0
#define SERDESID_SERDESID0_TECH_PROC_ALIGN                         0
#define SERDESID_SERDESID0_TECH_PROC_BITS                          3
#define SERDESID_SERDESID0_TECH_PROC_SHIFT                         6

/* serdesID :: serdesID0 :: model_number [05:00] */
#define SERDESID_SERDESID0_MODEL_NUMBER_MASK                       0x003f
#define SERDESID_SERDESID0_MODEL_NUMBER_ALIGN                      0
#define SERDESID_SERDESID0_MODEL_NUMBER_BITS                       6
#define SERDESID_SERDESID0_MODEL_NUMBER_SHIFT                      0


/****************************************************************************
 * serdesID :: serdesID1
 ***************************************************************************/
/* serdesID :: serdesID1 :: multiplicity [15:12] */
#define SERDESID_SERDESID1_MULTIPLICITY_MASK                       0xf000
#define SERDESID_SERDESID1_MULTIPLICITY_ALIGN                      0
#define SERDESID_SERDESID1_MULTIPLICITY_BITS                       4
#define SERDESID_SERDESID1_MULTIPLICITY_SHIFT                      12

/* serdesID :: serdesID1 :: CL37 [11:11] */
#define SERDESID_SERDESID1_CL37_MASK                               0x0800
#define SERDESID_SERDESID1_CL37_ALIGN                              0
#define SERDESID_SERDESID1_CL37_BITS                               1
#define SERDESID_SERDESID1_CL37_SHIFT                              11

/* serdesID :: serdesID1 :: CL73 [10:10] */
#define SERDESID_SERDESID1_CL73_MASK                               0x0400
#define SERDESID_SERDESID1_CL73_ALIGN                              0
#define SERDESID_SERDESID1_CL73_BITS                               1
#define SERDESID_SERDESID1_CL73_SHIFT                              10

/* serdesID :: serdesID1 :: CL36 [09:09] */
#define SERDESID_SERDESID1_CL36_MASK                               0x0200
#define SERDESID_SERDESID1_CL36_ALIGN                              0
#define SERDESID_SERDESID1_CL36_BITS                               1
#define SERDESID_SERDESID1_CL36_SHIFT                              9

/* serdesID :: serdesID1 :: CL48 [08:08] */
#define SERDESID_SERDESID1_CL48_MASK                               0x0100
#define SERDESID_SERDESID1_CL48_ALIGN                              0
#define SERDESID_SERDESID1_CL48_BITS                               1
#define SERDESID_SERDESID1_CL48_SHIFT                              8

/* serdesID :: serdesID1 :: HiGig [07:07] */
#define SERDESID_SERDESID1_HIGIG_MASK                              0x0080
#define SERDESID_SERDESID1_HIGIG_ALIGN                             0
#define SERDESID_SERDESID1_HIGIG_BITS                              1
#define SERDESID_SERDESID1_HIGIG_SHIFT                             7

/* serdesID :: serdesID1 :: HiGigII [06:06] */
#define SERDESID_SERDESID1_HIGIGII_MASK                            0x0040
#define SERDESID_SERDESID1_HIGIGII_ALIGN                           0
#define SERDESID_SERDESID1_HIGIGII_BITS                            1
#define SERDESID_SERDESID1_HIGIGII_SHIFT                           6

/* serdesID :: serdesID1 :: PCIE [05:05] */
#define SERDESID_SERDESID1_PCIE_MASK                               0x0020
#define SERDESID_SERDESID1_PCIE_ALIGN                              0
#define SERDESID_SERDESID1_PCIE_BITS                               1
#define SERDESID_SERDESID1_PCIE_SHIFT                              5

/* serdesID :: serdesID1 :: PCIE_II [04:04] */
#define SERDESID_SERDESID1_PCIE_II_MASK                            0x0010
#define SERDESID_SERDESID1_PCIE_II_ALIGN                           0
#define SERDESID_SERDESID1_PCIE_II_BITS                            1
#define SERDESID_SERDESID1_PCIE_II_SHIFT                           4

/* serdesID :: serdesID1 :: brcm_64B66B [03:03] */
#define SERDESID_SERDESID1_BRCM_64B66B_MASK                        0x0008
#define SERDESID_SERDESID1_BRCM_64B66B_ALIGN                       0
#define SERDESID_SERDESID1_BRCM_64B66B_BITS                        1
#define SERDESID_SERDESID1_BRCM_64B66B_SHIFT                       3

/* serdesID :: serdesID1 :: Scrambler [02:02] */
#define SERDESID_SERDESID1_SCRAMBLER_MASK                          0x0004
#define SERDESID_SERDESID1_SCRAMBLER_ALIGN                         0
#define SERDESID_SERDESID1_SCRAMBLER_BITS                          1
#define SERDESID_SERDESID1_SCRAMBLER_SHIFT                         2

/* serdesID :: serdesID1 :: reserved0 [01:00] */
#define SERDESID_SERDESID1_RESERVED0_MASK                          0x0003
#define SERDESID_SERDESID1_RESERVED0_ALIGN                         0
#define SERDESID_SERDESID1_RESERVED0_BITS                          2
#define SERDESID_SERDESID1_RESERVED0_SHIFT                         0


/****************************************************************************
 * serdesID :: serdesID2
 ***************************************************************************/
/* serdesID :: serdesID2 :: ID3present [15:15] */
#define SERDESID_SERDESID2_ID3PRESENT_MASK                         0x8000
#define SERDESID_SERDESID2_ID3PRESENT_ALIGN                        0
#define SERDESID_SERDESID2_ID3PRESENT_BITS                         1
#define SERDESID_SERDESID2_ID3PRESENT_SHIFT                        15

/* serdesID :: serdesID2 :: dr_25G_4L [14:14] */
#define SERDESID_SERDESID2_DR_25G_4L_MASK                          0x4000
#define SERDESID_SERDESID2_DR_25G_4L_ALIGN                         0
#define SERDESID_SERDESID2_DR_25G_4L_BITS                          1
#define SERDESID_SERDESID2_DR_25G_4L_SHIFT                         14

/* serdesID :: serdesID2 :: dr_21G_4L [13:13] */
#define SERDESID_SERDESID2_DR_21G_4L_MASK                          0x2000
#define SERDESID_SERDESID2_DR_21G_4L_ALIGN                         0
#define SERDESID_SERDESID2_DR_21G_4L_BITS                          1
#define SERDESID_SERDESID2_DR_21G_4L_SHIFT                         13

/* serdesID :: serdesID2 :: dr_20G_4L [12:12] */
#define SERDESID_SERDESID2_DR_20G_4L_MASK                          0x1000
#define SERDESID_SERDESID2_DR_20G_4L_ALIGN                         0
#define SERDESID_SERDESID2_DR_20G_4L_BITS                          1
#define SERDESID_SERDESID2_DR_20G_4L_SHIFT                         12

/* serdesID :: serdesID2 :: dr_16G_4L [11:11] */
#define SERDESID_SERDESID2_DR_16G_4L_MASK                          0x0800
#define SERDESID_SERDESID2_DR_16G_4L_ALIGN                         0
#define SERDESID_SERDESID2_DR_16G_4L_BITS                          1
#define SERDESID_SERDESID2_DR_16G_4L_SHIFT                         11

/* serdesID :: serdesID2 :: dr_15G_4L [10:10] */
#define SERDESID_SERDESID2_DR_15G_4L_MASK                          0x0400
#define SERDESID_SERDESID2_DR_15G_4L_ALIGN                         0
#define SERDESID_SERDESID2_DR_15G_4L_BITS                          1
#define SERDESID_SERDESID2_DR_15G_4L_SHIFT                         10

/* serdesID :: serdesID2 :: dr_13G_4L [09:09] */
#define SERDESID_SERDESID2_DR_13G_4L_MASK                          0x0200
#define SERDESID_SERDESID2_DR_13G_4L_ALIGN                         0
#define SERDESID_SERDESID2_DR_13G_4L_BITS                          1
#define SERDESID_SERDESID2_DR_13G_4L_SHIFT                         9

/* serdesID :: serdesID2 :: dr_12_5G_4L [08:08] */
#define SERDESID_SERDESID2_DR_12_5G_4L_MASK                        0x0100
#define SERDESID_SERDESID2_DR_12_5G_4L_ALIGN                       0
#define SERDESID_SERDESID2_DR_12_5G_4L_BITS                        1
#define SERDESID_SERDESID2_DR_12_5G_4L_SHIFT                       8

/* serdesID :: serdesID2 :: dr_12G_4L [07:07] */
#define SERDESID_SERDESID2_DR_12G_4L_MASK                          0x0080
#define SERDESID_SERDESID2_DR_12G_4L_ALIGN                         0
#define SERDESID_SERDESID2_DR_12G_4L_BITS                          1
#define SERDESID_SERDESID2_DR_12G_4L_SHIFT                         7

/* serdesID :: serdesID2 :: dr_10G_4L [06:06] */
#define SERDESID_SERDESID2_DR_10G_4L_MASK                          0x0040
#define SERDESID_SERDESID2_DR_10G_4L_ALIGN                         0
#define SERDESID_SERDESID2_DR_10G_4L_BITS                          1
#define SERDESID_SERDESID2_DR_10G_4L_SHIFT                         6

/* serdesID :: serdesID2 :: dr_6G_4L [05:05] */
#define SERDESID_SERDESID2_DR_6G_4L_MASK                           0x0020
#define SERDESID_SERDESID2_DR_6G_4L_ALIGN                          0
#define SERDESID_SERDESID2_DR_6G_4L_BITS                           1
#define SERDESID_SERDESID2_DR_6G_4L_SHIFT                          5

/* serdesID :: serdesID2 :: dr_5G_4L [04:04] */
#define SERDESID_SERDESID2_DR_5G_4L_MASK                           0x0010
#define SERDESID_SERDESID2_DR_5G_4L_ALIGN                          0
#define SERDESID_SERDESID2_DR_5G_4L_BITS                           1
#define SERDESID_SERDESID2_DR_5G_4L_SHIFT                          4

/* serdesID :: serdesID2 :: dr_2p5G_SL [03:03] */
#define SERDESID_SERDESID2_DR_2P5G_SL_MASK                         0x0008
#define SERDESID_SERDESID2_DR_2P5G_SL_ALIGN                        0
#define SERDESID_SERDESID2_DR_2P5G_SL_BITS                         1
#define SERDESID_SERDESID2_DR_2P5G_SL_SHIFT                        3

/* serdesID :: serdesID2 :: dr_1G_SL [02:02] */
#define SERDESID_SERDESID2_DR_1G_SL_MASK                           0x0004
#define SERDESID_SERDESID2_DR_1G_SL_ALIGN                          0
#define SERDESID_SERDESID2_DR_1G_SL_BITS                           1
#define SERDESID_SERDESID2_DR_1G_SL_SHIFT                          2

/* serdesID :: serdesID2 :: dr_100M_SL [01:01] */
#define SERDESID_SERDESID2_DR_100M_SL_MASK                         0x0002
#define SERDESID_SERDESID2_DR_100M_SL_ALIGN                        0
#define SERDESID_SERDESID2_DR_100M_SL_BITS                         1
#define SERDESID_SERDESID2_DR_100M_SL_SHIFT                        1

/* serdesID :: serdesID2 :: dr_10M_SL [00:00] */
#define SERDESID_SERDESID2_DR_10M_SL_MASK                          0x0001
#define SERDESID_SERDESID2_DR_10M_SL_ALIGN                         0
#define SERDESID_SERDESID2_DR_10M_SL_BITS                          1
#define SERDESID_SERDESID2_DR_10M_SL_SHIFT                         0


/****************************************************************************
 * serdesID :: serdesID3
 ***************************************************************************/
/* serdesID :: serdesID3 :: reserved0 [15:05] */
#define SERDESID_SERDESID3_RESERVED0_MASK                          0xffe0
#define SERDESID_SERDESID3_RESERVED0_ALIGN                         0
#define SERDESID_SERDESID3_RESERVED0_BITS                          11
#define SERDESID_SERDESID3_RESERVED0_SHIFT                         5

/* serdesID :: serdesID3 :: dr_6400_SL [04:04] */
#define SERDESID_SERDESID3_DR_6400_SL_MASK                         0x0010
#define SERDESID_SERDESID3_DR_6400_SL_ALIGN                        0
#define SERDESID_SERDESID3_DR_6400_SL_BITS                         1
#define SERDESID_SERDESID3_DR_6400_SL_SHIFT                        4

/* serdesID :: serdesID3 :: dr_5000_SL [03:03] */
#define SERDESID_SERDESID3_DR_5000_SL_MASK                         0x0008
#define SERDESID_SERDESID3_DR_5000_SL_ALIGN                        0
#define SERDESID_SERDESID3_DR_5000_SL_BITS                         1
#define SERDESID_SERDESID3_DR_5000_SL_SHIFT                        3

/* serdesID :: serdesID3 :: dr_4000_SL [02:02] */
#define SERDESID_SERDESID3_DR_4000_SL_MASK                         0x0004
#define SERDESID_SERDESID3_DR_4000_SL_ALIGN                        0
#define SERDESID_SERDESID3_DR_4000_SL_BITS                         1
#define SERDESID_SERDESID3_DR_4000_SL_SHIFT                        2

/* serdesID :: serdesID3 :: dr_2000_SL [01:01] */
#define SERDESID_SERDESID3_DR_2000_SL_MASK                         0x0002
#define SERDESID_SERDESID3_DR_2000_SL_ALIGN                        0
#define SERDESID_SERDESID3_DR_2000_SL_BITS                         1
#define SERDESID_SERDESID3_DR_2000_SL_SHIFT                        1

/* serdesID :: serdesID3 :: dr_100FX [00:00] */
#define SERDESID_SERDESID3_DR_100FX_MASK                           0x0001
#define SERDESID_SERDESID3_DR_100FX_ALIGN                          0
#define SERDESID_SERDESID3_DR_100FX_BITS                           1
#define SERDESID_SERDESID3_DR_100FX_SHIFT                          0


/****************************************************************************
 * XGXS16G_USER_Over1G
 ***************************************************************************/
/****************************************************************************
 * Over1G :: digctl_3_0
 ***************************************************************************/
/* Over1G :: digctl_3_0 :: an_lostLink_cnt [15:00] */
#define OVER1G_DIGCTL_3_0_AN_LOSTLINK_CNT_MASK                     0xffff
#define OVER1G_DIGCTL_3_0_AN_LOSTLINK_CNT_ALIGN                    0
#define OVER1G_DIGCTL_3_0_AN_LOSTLINK_CNT_BITS                     16
#define OVER1G_DIGCTL_3_0_AN_LOSTLINK_CNT_SHIFT                    0


/****************************************************************************
 * Over1G :: digctl_3_1
 ***************************************************************************/
/* Over1G :: digctl_3_1 :: an_switch_cnt [15:00] */
#define OVER1G_DIGCTL_3_1_AN_SWITCH_CNT_MASK                       0xffff
#define OVER1G_DIGCTL_3_1_AN_SWITCH_CNT_ALIGN                      0
#define OVER1G_DIGCTL_3_1_AN_SWITCH_CNT_BITS                       16
#define OVER1G_DIGCTL_3_1_AN_SWITCH_CNT_SHIFT                      0


/****************************************************************************
 * Over1G :: digctl_3_2
 ***************************************************************************/
/* Over1G :: digctl_3_2 :: an_link_cnt [15:00] */
#define OVER1G_DIGCTL_3_2_AN_LINK_CNT_MASK                         0xffff
#define OVER1G_DIGCTL_3_2_AN_LINK_CNT_ALIGN                        0
#define OVER1G_DIGCTL_3_2_AN_LINK_CNT_BITS                         16
#define OVER1G_DIGCTL_3_2_AN_LINK_CNT_SHIFT                        0


/****************************************************************************
 * Over1G :: digctl_3_3
 ***************************************************************************/
/* Over1G :: digctl_3_3 :: an_switch_cnt2 [15:08] */
#define OVER1G_DIGCTL_3_3_AN_SWITCH_CNT2_MASK                      0xff00
#define OVER1G_DIGCTL_3_3_AN_SWITCH_CNT2_ALIGN                     0
#define OVER1G_DIGCTL_3_3_AN_SWITCH_CNT2_BITS                      8
#define OVER1G_DIGCTL_3_3_AN_SWITCH_CNT2_SHIFT                     8

/* Over1G :: digctl_3_3 :: an_link_cnt2 [07:00] */
#define OVER1G_DIGCTL_3_3_AN_LINK_CNT2_MASK                        0x00ff
#define OVER1G_DIGCTL_3_3_AN_LINK_CNT2_ALIGN                       0
#define OVER1G_DIGCTL_3_3_AN_LINK_CNT2_BITS                        8
#define OVER1G_DIGCTL_3_3_AN_LINK_CNT2_SHIFT                       0


/****************************************************************************
 * Over1G :: digctl_3_4
 ***************************************************************************/
/* Over1G :: digctl_3_4 :: mp_number [15:05] */
#define OVER1G_DIGCTL_3_4_MP_NUMBER_MASK                           0xffe0
#define OVER1G_DIGCTL_3_4_MP_NUMBER_ALIGN                          0
#define OVER1G_DIGCTL_3_4_MP_NUMBER_BITS                           11
#define OVER1G_DIGCTL_3_4_MP_NUMBER_SHIFT                          5

/* Over1G :: digctl_3_4 :: no_fail_cnt [04:04] */
#define OVER1G_DIGCTL_3_4_NO_FAIL_CNT_MASK                         0x0010
#define OVER1G_DIGCTL_3_4_NO_FAIL_CNT_ALIGN                        0
#define OVER1G_DIGCTL_3_4_NO_FAIL_CNT_BITS                         1
#define OVER1G_DIGCTL_3_4_NO_FAIL_CNT_SHIFT                        4

/* Over1G :: digctl_3_4 :: an_fail_cnt [03:00] */
#define OVER1G_DIGCTL_3_4_AN_FAIL_CNT_MASK                         0x000f
#define OVER1G_DIGCTL_3_4_AN_FAIL_CNT_ALIGN                        0
#define OVER1G_DIGCTL_3_4_AN_FAIL_CNT_BITS                         4
#define OVER1G_DIGCTL_3_4_AN_FAIL_CNT_SHIFT                        0


/****************************************************************************
 * Over1G :: digctl_3_5
 ***************************************************************************/
/* Over1G :: digctl_3_5 :: an_ignoreLink_cnt [15:00] */
#define OVER1G_DIGCTL_3_5_AN_IGNORELINK_CNT_MASK                   0xffff
#define OVER1G_DIGCTL_3_5_AN_IGNORELINK_CNT_ALIGN                  0
#define OVER1G_DIGCTL_3_5_AN_IGNORELINK_CNT_BITS                   16
#define OVER1G_DIGCTL_3_5_AN_IGNORELINK_CNT_SHIFT                  0


/****************************************************************************
 * Over1G :: digctl_3_6
 ***************************************************************************/
/* Over1G :: digctl_3_6 :: an_lostLink_cnt2 [15:08] */
#define OVER1G_DIGCTL_3_6_AN_LOSTLINK_CNT2_MASK                    0xff00
#define OVER1G_DIGCTL_3_6_AN_LOSTLINK_CNT2_ALIGN                   0
#define OVER1G_DIGCTL_3_6_AN_LOSTLINK_CNT2_BITS                    8
#define OVER1G_DIGCTL_3_6_AN_LOSTLINK_CNT2_SHIFT                   8

/* Over1G :: digctl_3_6 :: an_ingoreLink_cnt2 [07:00] */
#define OVER1G_DIGCTL_3_6_AN_INGORELINK_CNT2_MASK                  0x00ff
#define OVER1G_DIGCTL_3_6_AN_INGORELINK_CNT2_ALIGN                 0
#define OVER1G_DIGCTL_3_6_AN_INGORELINK_CNT2_BITS                  8
#define OVER1G_DIGCTL_3_6_AN_INGORELINK_CNT2_SHIFT                 0


/****************************************************************************
 * Over1G :: TPOUT_1
 ***************************************************************************/
/* Over1G :: TPOUT_1 :: tpout1 [15:00] */
#define OVER1G_TPOUT_1_TPOUT1_MASK                                 0xffff
#define OVER1G_TPOUT_1_TPOUT1_ALIGN                                0
#define OVER1G_TPOUT_1_TPOUT1_BITS                                 16
#define OVER1G_TPOUT_1_TPOUT1_SHIFT                                0


/****************************************************************************
 * Over1G :: TPOUT_2
 ***************************************************************************/
/* Over1G :: TPOUT_2 :: tpout2 [15:00] */
#define OVER1G_TPOUT_2_TPOUT2_MASK                                 0xffff
#define OVER1G_TPOUT_2_TPOUT2_ALIGN                                0
#define OVER1G_TPOUT_2_TPOUT2_BITS                                 16
#define OVER1G_TPOUT_2_TPOUT2_SHIFT                                0


/****************************************************************************
 * Over1G :: UP1
 ***************************************************************************/
/* Over1G :: UP1 :: reserved0 [15:11] */
#define OVER1G_UP1_RESERVED0_MASK                                  0xf800
#define OVER1G_UP1_RESERVED0_ALIGN                                 0
#define OVER1G_UP1_RESERVED0_BITS                                  5
#define OVER1G_UP1_RESERVED0_SHIFT                                 11

/* Over1G :: UP1 :: dataRate_rsvd [10:10] */
#define OVER1G_UP1_DATARATE_RSVD_MASK                              0x0400
#define OVER1G_UP1_DATARATE_RSVD_ALIGN                             0
#define OVER1G_UP1_DATARATE_RSVD_BITS                              1
#define OVER1G_UP1_DATARATE_RSVD_SHIFT                             10

/* Over1G :: UP1 :: dataRate_16GX4 [09:09] */
#define OVER1G_UP1_DATARATE_16GX4_MASK                             0x0200
#define OVER1G_UP1_DATARATE_16GX4_ALIGN                            0
#define OVER1G_UP1_DATARATE_16GX4_BITS                             1
#define OVER1G_UP1_DATARATE_16GX4_SHIFT                            9

/* Over1G :: UP1 :: dataRate_15GX4 [08:08] */
#define OVER1G_UP1_DATARATE_15GX4_MASK                             0x0100
#define OVER1G_UP1_DATARATE_15GX4_ALIGN                            0
#define OVER1G_UP1_DATARATE_15GX4_BITS                             1
#define OVER1G_UP1_DATARATE_15GX4_SHIFT                            8

/* Over1G :: UP1 :: dataRate_13GX4 [07:07] */
#define OVER1G_UP1_DATARATE_13GX4_MASK                             0x0080
#define OVER1G_UP1_DATARATE_13GX4_ALIGN                            0
#define OVER1G_UP1_DATARATE_13GX4_BITS                             1
#define OVER1G_UP1_DATARATE_13GX4_SHIFT                            7

/* Over1G :: UP1 :: dataRate_12p5GX4 [06:06] */
#define OVER1G_UP1_DATARATE_12P5GX4_MASK                           0x0040
#define OVER1G_UP1_DATARATE_12P5GX4_ALIGN                          0
#define OVER1G_UP1_DATARATE_12P5GX4_BITS                           1
#define OVER1G_UP1_DATARATE_12P5GX4_SHIFT                          6

/* Over1G :: UP1 :: dataRate_12GX4 [05:05] */
#define OVER1G_UP1_DATARATE_12GX4_MASK                             0x0020
#define OVER1G_UP1_DATARATE_12GX4_ALIGN                            0
#define OVER1G_UP1_DATARATE_12GX4_BITS                             1
#define OVER1G_UP1_DATARATE_12GX4_SHIFT                            5

/* Over1G :: UP1 :: dataRate_10GCX4 [04:04] */
#define OVER1G_UP1_DATARATE_10GCX4_MASK                            0x0010
#define OVER1G_UP1_DATARATE_10GCX4_ALIGN                           0
#define OVER1G_UP1_DATARATE_10GCX4_BITS                            1
#define OVER1G_UP1_DATARATE_10GCX4_SHIFT                           4

/* Over1G :: UP1 :: dataRate_10GX4 [03:03] */
#define OVER1G_UP1_DATARATE_10GX4_MASK                             0x0008
#define OVER1G_UP1_DATARATE_10GX4_ALIGN                            0
#define OVER1G_UP1_DATARATE_10GX4_BITS                             1
#define OVER1G_UP1_DATARATE_10GX4_SHIFT                            3

/* Over1G :: UP1 :: dataRate_6GX4 [02:02] */
#define OVER1G_UP1_DATARATE_6GX4_MASK                              0x0004
#define OVER1G_UP1_DATARATE_6GX4_ALIGN                             0
#define OVER1G_UP1_DATARATE_6GX4_BITS                              1
#define OVER1G_UP1_DATARATE_6GX4_SHIFT                             2

/* Over1G :: UP1 :: dataRate_5GX4 [01:01] */
#define OVER1G_UP1_DATARATE_5GX4_MASK                              0x0002
#define OVER1G_UP1_DATARATE_5GX4_ALIGN                             0
#define OVER1G_UP1_DATARATE_5GX4_BITS                              1
#define OVER1G_UP1_DATARATE_5GX4_SHIFT                             1

/* Over1G :: UP1 :: dataRate_2p5GX1 [00:00] */
#define OVER1G_UP1_DATARATE_2P5GX1_MASK                            0x0001
#define OVER1G_UP1_DATARATE_2P5GX1_ALIGN                           0
#define OVER1G_UP1_DATARATE_2P5GX1_BITS                            1
#define OVER1G_UP1_DATARATE_2P5GX1_SHIFT                           0


/****************************************************************************
 * Over1G :: UP2
 ***************************************************************************/
/* Over1G :: UP2 :: reserved0 [15:11] */
#define OVER1G_UP2_RESERVED0_MASK                                  0xf800
#define OVER1G_UP2_RESERVED0_ALIGN                                 0
#define OVER1G_UP2_RESERVED0_BITS                                  5
#define OVER1G_UP2_RESERVED0_SHIFT                                 11

/* Over1G :: UP2 :: valid [10:10] */
#define OVER1G_UP2_VALID_MASK                                      0x0400
#define OVER1G_UP2_VALID_ALIGN                                     0
#define OVER1G_UP2_VALID_BITS                                      1
#define OVER1G_UP2_VALID_SHIFT                                     10

/* Over1G :: UP2 :: preemphasis [09:06] */
#define OVER1G_UP2_PREEMPHASIS_MASK                                0x03c0
#define OVER1G_UP2_PREEMPHASIS_ALIGN                               0
#define OVER1G_UP2_PREEMPHASIS_BITS                                4
#define OVER1G_UP2_PREEMPHASIS_SHIFT                               6

/* Over1G :: UP2 :: idriver [05:03] */
#define OVER1G_UP2_IDRIVER_MASK                                    0x0038
#define OVER1G_UP2_IDRIVER_ALIGN                                   0
#define OVER1G_UP2_IDRIVER_BITS                                    3
#define OVER1G_UP2_IDRIVER_SHIFT                                   3

/* Over1G :: UP2 :: ipredriver [02:00] */
#define OVER1G_UP2_IPREDRIVER_MASK                                 0x0007
#define OVER1G_UP2_IPREDRIVER_ALIGN                                0
#define OVER1G_UP2_IPREDRIVER_BITS                                 3
#define OVER1G_UP2_IPREDRIVER_SHIFT                                0


/****************************************************************************
 * Over1G :: UP3
 ***************************************************************************/
/* Over1G :: UP3 :: reserved0 [15:11] */
#define OVER1G_UP3_RESERVED0_MASK                                  0xf800
#define OVER1G_UP3_RESERVED0_ALIGN                                 0
#define OVER1G_UP3_RESERVED0_BITS                                  5
#define OVER1G_UP3_RESERVED0_SHIFT                                 11

/* Over1G :: UP3 :: last [10:10] */
#define OVER1G_UP3_LAST_MASK                                       0x0400
#define OVER1G_UP3_LAST_ALIGN                                      0
#define OVER1G_UP3_LAST_BITS                                       1
#define OVER1G_UP3_LAST_SHIFT                                      10

/* Over1G :: UP3 :: reserved1 [09:02] */
#define OVER1G_UP3_RESERVED1_MASK                                  0x03fc
#define OVER1G_UP3_RESERVED1_ALIGN                                 0
#define OVER1G_UP3_RESERVED1_BITS                                  8
#define OVER1G_UP3_RESERVED1_SHIFT                                 2

/* Over1G :: UP3 :: scramble_8B10B [01:01] */
#define OVER1G_UP3_SCRAMBLE_8B10B_MASK                             0x0002
#define OVER1G_UP3_SCRAMBLE_8B10B_ALIGN                            0
#define OVER1G_UP3_SCRAMBLE_8B10B_BITS                             1
#define OVER1G_UP3_SCRAMBLE_8B10B_SHIFT                            1

/* Over1G :: UP3 :: HiGig2 [00:00] */
#define OVER1G_UP3_HIGIG2_MASK                                     0x0001
#define OVER1G_UP3_HIGIG2_ALIGN                                    0
#define OVER1G_UP3_HIGIG2_BITS                                     1
#define OVER1G_UP3_HIGIG2_SHIFT                                    0


/****************************************************************************
 * Over1G :: LP_UP1
 ***************************************************************************/
/* Over1G :: LP_UP1 :: reserved0 [15:11] */
#define OVER1G_LP_UP1_RESERVED0_MASK                               0xf800
#define OVER1G_LP_UP1_RESERVED0_ALIGN                              0
#define OVER1G_LP_UP1_RESERVED0_BITS                               5
#define OVER1G_LP_UP1_RESERVED0_SHIFT                              11

/* Over1G :: LP_UP1 :: dataRate_rsvd [10:10] */
#define OVER1G_LP_UP1_DATARATE_RSVD_MASK                           0x0400
#define OVER1G_LP_UP1_DATARATE_RSVD_ALIGN                          0
#define OVER1G_LP_UP1_DATARATE_RSVD_BITS                           1
#define OVER1G_LP_UP1_DATARATE_RSVD_SHIFT                          10

/* Over1G :: LP_UP1 :: dataRate_16GX4 [09:09] */
#define OVER1G_LP_UP1_DATARATE_16GX4_MASK                          0x0200
#define OVER1G_LP_UP1_DATARATE_16GX4_ALIGN                         0
#define OVER1G_LP_UP1_DATARATE_16GX4_BITS                          1
#define OVER1G_LP_UP1_DATARATE_16GX4_SHIFT                         9

/* Over1G :: LP_UP1 :: dataRate_15GX4 [08:08] */
#define OVER1G_LP_UP1_DATARATE_15GX4_MASK                          0x0100
#define OVER1G_LP_UP1_DATARATE_15GX4_ALIGN                         0
#define OVER1G_LP_UP1_DATARATE_15GX4_BITS                          1
#define OVER1G_LP_UP1_DATARATE_15GX4_SHIFT                         8

/* Over1G :: LP_UP1 :: dataRate_13GX4 [07:07] */
#define OVER1G_LP_UP1_DATARATE_13GX4_MASK                          0x0080
#define OVER1G_LP_UP1_DATARATE_13GX4_ALIGN                         0
#define OVER1G_LP_UP1_DATARATE_13GX4_BITS                          1
#define OVER1G_LP_UP1_DATARATE_13GX4_SHIFT                         7

/* Over1G :: LP_UP1 :: dataRate_12p5GX4 [06:06] */
#define OVER1G_LP_UP1_DATARATE_12P5GX4_MASK                        0x0040
#define OVER1G_LP_UP1_DATARATE_12P5GX4_ALIGN                       0
#define OVER1G_LP_UP1_DATARATE_12P5GX4_BITS                        1
#define OVER1G_LP_UP1_DATARATE_12P5GX4_SHIFT                       6

/* Over1G :: LP_UP1 :: dataRate_12GX4 [05:05] */
#define OVER1G_LP_UP1_DATARATE_12GX4_MASK                          0x0020
#define OVER1G_LP_UP1_DATARATE_12GX4_ALIGN                         0
#define OVER1G_LP_UP1_DATARATE_12GX4_BITS                          1
#define OVER1G_LP_UP1_DATARATE_12GX4_SHIFT                         5

/* Over1G :: LP_UP1 :: dataRate_10GCX4 [04:04] */
#define OVER1G_LP_UP1_DATARATE_10GCX4_MASK                         0x0010
#define OVER1G_LP_UP1_DATARATE_10GCX4_ALIGN                        0
#define OVER1G_LP_UP1_DATARATE_10GCX4_BITS                         1
#define OVER1G_LP_UP1_DATARATE_10GCX4_SHIFT                        4

/* Over1G :: LP_UP1 :: dataRate_10GX4 [03:03] */
#define OVER1G_LP_UP1_DATARATE_10GX4_MASK                          0x0008
#define OVER1G_LP_UP1_DATARATE_10GX4_ALIGN                         0
#define OVER1G_LP_UP1_DATARATE_10GX4_BITS                          1
#define OVER1G_LP_UP1_DATARATE_10GX4_SHIFT                         3

/* Over1G :: LP_UP1 :: dataRate_6GX4 [02:02] */
#define OVER1G_LP_UP1_DATARATE_6GX4_MASK                           0x0004
#define OVER1G_LP_UP1_DATARATE_6GX4_ALIGN                          0
#define OVER1G_LP_UP1_DATARATE_6GX4_BITS                           1
#define OVER1G_LP_UP1_DATARATE_6GX4_SHIFT                          2

/* Over1G :: LP_UP1 :: dataRate_5GX4 [01:01] */
#define OVER1G_LP_UP1_DATARATE_5GX4_MASK                           0x0002
#define OVER1G_LP_UP1_DATARATE_5GX4_ALIGN                          0
#define OVER1G_LP_UP1_DATARATE_5GX4_BITS                           1
#define OVER1G_LP_UP1_DATARATE_5GX4_SHIFT                          1

/* Over1G :: LP_UP1 :: dataRate_2p5GX1 [00:00] */
#define OVER1G_LP_UP1_DATARATE_2P5GX1_MASK                         0x0001
#define OVER1G_LP_UP1_DATARATE_2P5GX1_ALIGN                        0
#define OVER1G_LP_UP1_DATARATE_2P5GX1_BITS                         1
#define OVER1G_LP_UP1_DATARATE_2P5GX1_SHIFT                        0


/****************************************************************************
 * Over1G :: LP_UP2
 ***************************************************************************/
/* Over1G :: LP_UP2 :: reserved0 [15:11] */
#define OVER1G_LP_UP2_RESERVED0_MASK                               0xf800
#define OVER1G_LP_UP2_RESERVED0_ALIGN                              0
#define OVER1G_LP_UP2_RESERVED0_BITS                               5
#define OVER1G_LP_UP2_RESERVED0_SHIFT                              11

/* Over1G :: LP_UP2 :: valid [10:10] */
#define OVER1G_LP_UP2_VALID_MASK                                   0x0400
#define OVER1G_LP_UP2_VALID_ALIGN                                  0
#define OVER1G_LP_UP2_VALID_BITS                                   1
#define OVER1G_LP_UP2_VALID_SHIFT                                  10

/* Over1G :: LP_UP2 :: preemphasis [09:06] */
#define OVER1G_LP_UP2_PREEMPHASIS_MASK                             0x03c0
#define OVER1G_LP_UP2_PREEMPHASIS_ALIGN                            0
#define OVER1G_LP_UP2_PREEMPHASIS_BITS                             4
#define OVER1G_LP_UP2_PREEMPHASIS_SHIFT                            6

/* Over1G :: LP_UP2 :: idriver [05:03] */
#define OVER1G_LP_UP2_IDRIVER_MASK                                 0x0038
#define OVER1G_LP_UP2_IDRIVER_ALIGN                                0
#define OVER1G_LP_UP2_IDRIVER_BITS                                 3
#define OVER1G_LP_UP2_IDRIVER_SHIFT                                3

/* Over1G :: LP_UP2 :: ipredriver [02:00] */
#define OVER1G_LP_UP2_IPREDRIVER_MASK                              0x0007
#define OVER1G_LP_UP2_IPREDRIVER_ALIGN                             0
#define OVER1G_LP_UP2_IPREDRIVER_BITS                              3
#define OVER1G_LP_UP2_IPREDRIVER_SHIFT                             0


/****************************************************************************
 * Over1G :: LP_UP3
 ***************************************************************************/
/* Over1G :: LP_UP3 :: reserved0 [15:11] */
#define OVER1G_LP_UP3_RESERVED0_MASK                               0xf800
#define OVER1G_LP_UP3_RESERVED0_ALIGN                              0
#define OVER1G_LP_UP3_RESERVED0_BITS                               5
#define OVER1G_LP_UP3_RESERVED0_SHIFT                              11

/* Over1G :: LP_UP3 :: last [10:10] */
#define OVER1G_LP_UP3_LAST_MASK                                    0x0400
#define OVER1G_LP_UP3_LAST_ALIGN                                   0
#define OVER1G_LP_UP3_LAST_BITS                                    1
#define OVER1G_LP_UP3_LAST_SHIFT                                   10

/* Over1G :: LP_UP3 :: reserved1 [09:02] */
#define OVER1G_LP_UP3_RESERVED1_MASK                               0x03fc
#define OVER1G_LP_UP3_RESERVED1_ALIGN                              0
#define OVER1G_LP_UP3_RESERVED1_BITS                               8
#define OVER1G_LP_UP3_RESERVED1_SHIFT                              2

/* Over1G :: LP_UP3 :: scramble_8B10B [01:01] */
#define OVER1G_LP_UP3_SCRAMBLE_8B10B_MASK                          0x0002
#define OVER1G_LP_UP3_SCRAMBLE_8B10B_ALIGN                         0
#define OVER1G_LP_UP3_SCRAMBLE_8B10B_BITS                          1
#define OVER1G_LP_UP3_SCRAMBLE_8B10B_SHIFT                         1

/* Over1G :: LP_UP3 :: HiGig2 [00:00] */
#define OVER1G_LP_UP3_HIGIG2_MASK                                  0x0001
#define OVER1G_LP_UP3_HIGIG2_ALIGN                                 0
#define OVER1G_LP_UP3_HIGIG2_BITS                                  1
#define OVER1G_LP_UP3_HIGIG2_SHIFT                                 0


/****************************************************************************
 * XGXS16G_USER_RemotePhy
 ***************************************************************************/
/****************************************************************************
 * RemotePhy :: MiscRxStatus
 ***************************************************************************/
/* union - case statusSelect0 [15:00] */
/* RemotePhy :: MiscRxStatus :: capture_NP_lh [15:15] */
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_MASK    0x8000
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_ALIGN   0
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_BITS    1
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_SHIFT   15

/* RemotePhy :: MiscRxStatus :: teton_brk_link_lh [14:14] */
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_MASK 0x4000
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_ALIGN 0
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_BITS 1
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_SHIFT 14

/* RemotePhy :: MiscRxStatus :: UP3_lh [13:13] */
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_UP3_LH_MASK           0x2000
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_UP3_LH_ALIGN          0
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_UP3_LH_BITS           1
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_UP3_LH_SHIFT          13

/* RemotePhy :: MiscRxStatus :: MP5_lh [12:12] */
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MP5_LH_MASK           0x1000
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MP5_LH_ALIGN          0
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MP5_LH_BITS           1
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MP5_LH_SHIFT          12

/* RemotePhy :: MiscRxStatus :: nonMatchingOUI_lh [11:11] */
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_MASK 0x0800
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_ALIGN 0
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_BITS 1
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_SHIFT 11

/* RemotePhy :: MiscRxStatus :: matchingOUI_msb_lh [10:10] */
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_MASK 0x0400
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_ALIGN 0
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_BITS 1
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_SHIFT 10

/* RemotePhy :: MiscRxStatus :: matchingOUI_lsb_lh [09:09] */
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_MASK 0x0200
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_ALIGN 0
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_BITS 1
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_SHIFT 9

/* RemotePhy :: MiscRxStatus :: invalidSeq_lh [08:08] */
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_MASK    0x0100
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_ALIGN   0
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_BITS    1
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_SHIFT   8

/* RemotePhy :: MiscRxStatus :: nullMP_lh [07:07] */
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_MASK        0x0080
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_ALIGN       0
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_BITS        1
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_SHIFT       7

/* RemotePhy :: MiscRxStatus :: remotePhyMP_lh [06:06] */
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_MASK   0x0040
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_ALIGN  0
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_BITS   1
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_SHIFT  6

/* RemotePhy :: MiscRxStatus :: nonMatchingMP_lh [05:05] */
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_MASK 0x0020
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_ALIGN 0
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_BITS 1
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_SHIFT 5

/* RemotePhy :: MiscRxStatus :: over1gMP_lh [04:04] */
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_MASK      0x0010
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_ALIGN     0
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_BITS      1
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_SHIFT     4

/* RemotePhy :: MiscRxStatus :: rx_config_is_0_lh [03:03] */
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_MASK 0x0008
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_ALIGN 0
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_BITS 1
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_SHIFT 3

/* RemotePhy :: MiscRxStatus :: np_toggle_err_lh [02:02] */
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_MASK 0x0004
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_ALIGN 0
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_BITS 1
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_SHIFT 2

/* RemotePhy :: MiscRxStatus :: mr_np_lh [01:01] */
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_MASK         0x0002
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_ALIGN        0
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_BITS         1
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_SHIFT        1

/* RemotePhy :: MiscRxStatus :: mr_bp_lh [00:00] */
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_MASK         0x0001
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_ALIGN        0
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_BITS         1
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_SHIFT        0


/* union - case statusSelect1 [15:00] */
/* RemotePhy :: MiscRxStatus :: reserved0 [15:04] */
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT1_RESERVED0_MASK        0xfff0
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT1_RESERVED0_ALIGN       0
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT1_RESERVED0_BITS        12
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT1_RESERVED0_SHIFT       4

/* RemotePhy :: MiscRxStatus :: np_count [03:00] */
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_MASK         0x000f
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_ALIGN        0
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_BITS         4
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_SHIFT        0


/* union - case statusSelect2 [15:00] */
/* RemotePhy :: MiscRxStatus :: reserved0 [15:06] */
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_RESERVED0_MASK        0xffc0
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_RESERVED0_ALIGN       0
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_RESERVED0_BITS        10
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_RESERVED0_SHIFT       6

/* RemotePhy :: MiscRxStatus :: remote_phy_enable [05:05] */
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_MASK 0x0020
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_ALIGN 0
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_BITS 1
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_SHIFT 5

/* RemotePhy :: MiscRxStatus :: det_teton_mode [04:04] */
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_MASK   0x0010
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_ALIGN  0
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_BITS   1
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_SHIFT  4

/* RemotePhy :: MiscRxStatus :: cu_linkdown [03:03] */
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_MASK      0x0008
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_ALIGN     0
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_BITS      1
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_SHIFT     3

/* RemotePhy :: MiscRxStatus :: cu_resolution_error [02:02] */
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_MASK 0x0004
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_ALIGN 0
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_BITS 1
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_SHIFT 2

/* RemotePhy :: MiscRxStatus :: remotePhy_autosel [01:01] */
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_MASK 0x0002
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_ALIGN 0
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_BITS 1
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_SHIFT 1

/* RemotePhy :: MiscRxStatus :: rx_config_isNot_0_lh [00:00] */
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_MASK 0x0001
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_ALIGN 0
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_BITS 1
#define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_SHIFT 0



/****************************************************************************
 * RemotePhy :: lp_basePage
 ***************************************************************************/
/* RemotePhy :: lp_basePage :: lp_basePage [15:00] */
#define REMOTEPHY_LP_BASEPAGE_LP_BASEPAGE_MASK                     0xffff
#define REMOTEPHY_LP_BASEPAGE_LP_BASEPAGE_ALIGN                    0
#define REMOTEPHY_LP_BASEPAGE_LP_BASEPAGE_BITS                     16
#define REMOTEPHY_LP_BASEPAGE_LP_BASEPAGE_SHIFT                    0


/****************************************************************************
 * RemotePhy :: lp_nextPage_0
 ***************************************************************************/
/* RemotePhy :: lp_nextPage_0 :: lp_nextPage_0 [15:00] */
#define REMOTEPHY_LP_NEXTPAGE_0_LP_NEXTPAGE_0_MASK                 0xffff
#define REMOTEPHY_LP_NEXTPAGE_0_LP_NEXTPAGE_0_ALIGN                0
#define REMOTEPHY_LP_NEXTPAGE_0_LP_NEXTPAGE_0_BITS                 16
#define REMOTEPHY_LP_NEXTPAGE_0_LP_NEXTPAGE_0_SHIFT                0


/****************************************************************************
 * RemotePhy :: lp_nextPage_1
 ***************************************************************************/
/* RemotePhy :: lp_nextPage_1 :: lp_nextPage_1 [15:00] */
#define REMOTEPHY_LP_NEXTPAGE_1_LP_NEXTPAGE_1_MASK                 0xffff
#define REMOTEPHY_LP_NEXTPAGE_1_LP_NEXTPAGE_1_ALIGN                0
#define REMOTEPHY_LP_NEXTPAGE_1_LP_NEXTPAGE_1_BITS                 16
#define REMOTEPHY_LP_NEXTPAGE_1_LP_NEXTPAGE_1_SHIFT                0


/****************************************************************************
 * RemotePhy :: lp_nextPage_2
 ***************************************************************************/
/* RemotePhy :: lp_nextPage_2 :: lp_nextPage_2 [15:00] */
#define REMOTEPHY_LP_NEXTPAGE_2_LP_NEXTPAGE_2_MASK                 0xffff
#define REMOTEPHY_LP_NEXTPAGE_2_LP_NEXTPAGE_2_ALIGN                0
#define REMOTEPHY_LP_NEXTPAGE_2_LP_NEXTPAGE_2_BITS                 16
#define REMOTEPHY_LP_NEXTPAGE_2_LP_NEXTPAGE_2_SHIFT                0


/****************************************************************************
 * RemotePhy :: lp_nextPage_3
 ***************************************************************************/
/* RemotePhy :: lp_nextPage_3 :: lp_nextPage_3 [15:00] */
#define REMOTEPHY_LP_NEXTPAGE_3_LP_NEXTPAGE_3_MASK                 0xffff
#define REMOTEPHY_LP_NEXTPAGE_3_LP_NEXTPAGE_3_ALIGN                0
#define REMOTEPHY_LP_NEXTPAGE_3_LP_NEXTPAGE_3_BITS                 16
#define REMOTEPHY_LP_NEXTPAGE_3_LP_NEXTPAGE_3_SHIFT                0


/****************************************************************************
 * RemotePhy :: lp_nextPage_4
 ***************************************************************************/
/* RemotePhy :: lp_nextPage_4 :: lp_nextPage_4 [15:00] */
#define REMOTEPHY_LP_NEXTPAGE_4_LP_NEXTPAGE_4_MASK                 0xffff
#define REMOTEPHY_LP_NEXTPAGE_4_LP_NEXTPAGE_4_ALIGN                0
#define REMOTEPHY_LP_NEXTPAGE_4_LP_NEXTPAGE_4_BITS                 16
#define REMOTEPHY_LP_NEXTPAGE_4_LP_NEXTPAGE_4_SHIFT                0


/****************************************************************************
 * RemotePhy :: rp_nextPage_0
 ***************************************************************************/
/* RemotePhy :: rp_nextPage_0 :: reserved0 [15:15] */
#define REMOTEPHY_RP_NEXTPAGE_0_RESERVED0_MASK                     0x8000
#define REMOTEPHY_RP_NEXTPAGE_0_RESERVED0_ALIGN                    0
#define REMOTEPHY_RP_NEXTPAGE_0_RESERVED0_BITS                     1
#define REMOTEPHY_RP_NEXTPAGE_0_RESERVED0_SHIFT                    15

/* RemotePhy :: rp_nextPage_0 :: extra_page_disable [14:14] */
#define REMOTEPHY_RP_NEXTPAGE_0_EXTRA_PAGE_DISABLE_MASK            0x4000
#define REMOTEPHY_RP_NEXTPAGE_0_EXTRA_PAGE_DISABLE_ALIGN           0
#define REMOTEPHY_RP_NEXTPAGE_0_EXTRA_PAGE_DISABLE_BITS            1
#define REMOTEPHY_RP_NEXTPAGE_0_EXTRA_PAGE_DISABLE_SHIFT           14

/* RemotePhy :: rp_nextPage_0 :: null_page_enable [13:13] */
#define REMOTEPHY_RP_NEXTPAGE_0_NULL_PAGE_ENABLE_MASK              0x2000
#define REMOTEPHY_RP_NEXTPAGE_0_NULL_PAGE_ENABLE_ALIGN             0
#define REMOTEPHY_RP_NEXTPAGE_0_NULL_PAGE_ENABLE_BITS              1
#define REMOTEPHY_RP_NEXTPAGE_0_NULL_PAGE_ENABLE_SHIFT             13

/* RemotePhy :: rp_nextPage_0 :: over_1g_disable [12:12] */
#define REMOTEPHY_RP_NEXTPAGE_0_OVER_1G_DISABLE_MASK               0x1000
#define REMOTEPHY_RP_NEXTPAGE_0_OVER_1G_DISABLE_ALIGN              0
#define REMOTEPHY_RP_NEXTPAGE_0_OVER_1G_DISABLE_BITS               1
#define REMOTEPHY_RP_NEXTPAGE_0_OVER_1G_DISABLE_SHIFT              12

/* RemotePhy :: rp_nextPage_0 :: remote_phy_enable [11:11] */
#define REMOTEPHY_RP_NEXTPAGE_0_REMOTE_PHY_ENABLE_MASK             0x0800
#define REMOTEPHY_RP_NEXTPAGE_0_REMOTE_PHY_ENABLE_ALIGN            0
#define REMOTEPHY_RP_NEXTPAGE_0_REMOTE_PHY_ENABLE_BITS             1
#define REMOTEPHY_RP_NEXTPAGE_0_REMOTE_PHY_ENABLE_SHIFT            11

/* RemotePhy :: rp_nextPage_0 :: rp_nextPage_0 [10:00] */
#define REMOTEPHY_RP_NEXTPAGE_0_RP_NEXTPAGE_0_MASK                 0x07ff
#define REMOTEPHY_RP_NEXTPAGE_0_RP_NEXTPAGE_0_ALIGN                0
#define REMOTEPHY_RP_NEXTPAGE_0_RP_NEXTPAGE_0_BITS                 11
#define REMOTEPHY_RP_NEXTPAGE_0_RP_NEXTPAGE_0_SHIFT                0


/****************************************************************************
 * RemotePhy :: rp_nextPage_1
 ***************************************************************************/
/* RemotePhy :: rp_nextPage_1 :: reserved0 [15:15] */
#define REMOTEPHY_RP_NEXTPAGE_1_RESERVED0_MASK                     0x8000
#define REMOTEPHY_RP_NEXTPAGE_1_RESERVED0_ALIGN                    0
#define REMOTEPHY_RP_NEXTPAGE_1_RESERVED0_BITS                     1
#define REMOTEPHY_RP_NEXTPAGE_1_RESERVED0_SHIFT                    15

/* RemotePhy :: rp_nextPage_1 :: remotePhy_linkDown_rstrt_disable [14:14] */
#define REMOTEPHY_RP_NEXTPAGE_1_REMOTEPHY_LINKDOWN_RSTRT_DISABLE_MASK 0x4000
#define REMOTEPHY_RP_NEXTPAGE_1_REMOTEPHY_LINKDOWN_RSTRT_DISABLE_ALIGN 0
#define REMOTEPHY_RP_NEXTPAGE_1_REMOTEPHY_LINKDOWN_RSTRT_DISABLE_BITS 1
#define REMOTEPHY_RP_NEXTPAGE_1_REMOTEPHY_LINKDOWN_RSTRT_DISABLE_SHIFT 14

/* RemotePhy :: rp_nextPage_1 :: remotePhy_rsltn_err_rstrt_disable [13:13] */
#define REMOTEPHY_RP_NEXTPAGE_1_REMOTEPHY_RSLTN_ERR_RSTRT_DISABLE_MASK 0x2000
#define REMOTEPHY_RP_NEXTPAGE_1_REMOTEPHY_RSLTN_ERR_RSTRT_DISABLE_ALIGN 0
#define REMOTEPHY_RP_NEXTPAGE_1_REMOTEPHY_RSLTN_ERR_RSTRT_DISABLE_BITS 1
#define REMOTEPHY_RP_NEXTPAGE_1_REMOTEPHY_RSLTN_ERR_RSTRT_DISABLE_SHIFT 13

/* RemotePhy :: rp_nextPage_1 :: remotePhy_resolution_disable [12:12] */
#define REMOTEPHY_RP_NEXTPAGE_1_REMOTEPHY_RESOLUTION_DISABLE_MASK  0x1000
#define REMOTEPHY_RP_NEXTPAGE_1_REMOTEPHY_RESOLUTION_DISABLE_ALIGN 0
#define REMOTEPHY_RP_NEXTPAGE_1_REMOTEPHY_RESOLUTION_DISABLE_BITS  1
#define REMOTEPHY_RP_NEXTPAGE_1_REMOTEPHY_RESOLUTION_DISABLE_SHIFT 12

/* RemotePhy :: rp_nextPage_1 :: remotePhy_decode_enable [11:11] */
#define REMOTEPHY_RP_NEXTPAGE_1_REMOTEPHY_DECODE_ENABLE_MASK       0x0800
#define REMOTEPHY_RP_NEXTPAGE_1_REMOTEPHY_DECODE_ENABLE_ALIGN      0
#define REMOTEPHY_RP_NEXTPAGE_1_REMOTEPHY_DECODE_ENABLE_BITS       1
#define REMOTEPHY_RP_NEXTPAGE_1_REMOTEPHY_DECODE_ENABLE_SHIFT      11

/* RemotePhy :: rp_nextPage_1 :: rp_nextPage_1 [10:00] */
#define REMOTEPHY_RP_NEXTPAGE_1_RP_NEXTPAGE_1_MASK                 0x07ff
#define REMOTEPHY_RP_NEXTPAGE_1_RP_NEXTPAGE_1_ALIGN                0
#define REMOTEPHY_RP_NEXTPAGE_1_RP_NEXTPAGE_1_BITS                 11
#define REMOTEPHY_RP_NEXTPAGE_1_RP_NEXTPAGE_1_SHIFT                0


/****************************************************************************
 * RemotePhy :: rp_nextPage_2
 ***************************************************************************/
/* RemotePhy :: rp_nextPage_2 :: reserved0 [15:12] */
#define REMOTEPHY_RP_NEXTPAGE_2_RESERVED0_MASK                     0xf000
#define REMOTEPHY_RP_NEXTPAGE_2_RESERVED0_ALIGN                    0
#define REMOTEPHY_RP_NEXTPAGE_2_RESERVED0_BITS                     4
#define REMOTEPHY_RP_NEXTPAGE_2_RESERVED0_SHIFT                    12

/* RemotePhy :: rp_nextPage_2 :: remPhy_NP_clr_disable [11:11] */
#define REMOTEPHY_RP_NEXTPAGE_2_REMPHY_NP_CLR_DISABLE_MASK         0x0800
#define REMOTEPHY_RP_NEXTPAGE_2_REMPHY_NP_CLR_DISABLE_ALIGN        0
#define REMOTEPHY_RP_NEXTPAGE_2_REMPHY_NP_CLR_DISABLE_BITS         1
#define REMOTEPHY_RP_NEXTPAGE_2_REMPHY_NP_CLR_DISABLE_SHIFT        11

/* RemotePhy :: rp_nextPage_2 :: rp_nextPage_2 [10:00] */
#define REMOTEPHY_RP_NEXTPAGE_2_RP_NEXTPAGE_2_MASK                 0x07ff
#define REMOTEPHY_RP_NEXTPAGE_2_RP_NEXTPAGE_2_ALIGN                0
#define REMOTEPHY_RP_NEXTPAGE_2_RP_NEXTPAGE_2_BITS                 11
#define REMOTEPHY_RP_NEXTPAGE_2_RP_NEXTPAGE_2_SHIFT                0


/****************************************************************************
 * RemotePhy :: rp_nextPage_3
 ***************************************************************************/
/* RemotePhy :: rp_nextPage_3 :: reserved0 [15:11] */
#define REMOTEPHY_RP_NEXTPAGE_3_RESERVED0_MASK                     0xf800
#define REMOTEPHY_RP_NEXTPAGE_3_RESERVED0_ALIGN                    0
#define REMOTEPHY_RP_NEXTPAGE_3_RESERVED0_BITS                     5
#define REMOTEPHY_RP_NEXTPAGE_3_RESERVED0_SHIFT                    11

/* RemotePhy :: rp_nextPage_3 :: rp_nextPage_3 [10:00] */
#define REMOTEPHY_RP_NEXTPAGE_3_RP_NEXTPAGE_3_MASK                 0x07ff
#define REMOTEPHY_RP_NEXTPAGE_3_RP_NEXTPAGE_3_ALIGN                0
#define REMOTEPHY_RP_NEXTPAGE_3_RP_NEXTPAGE_3_BITS                 11
#define REMOTEPHY_RP_NEXTPAGE_3_RP_NEXTPAGE_3_SHIFT                0


/****************************************************************************
 * RemotePhy :: rp_nextPage_4
 ***************************************************************************/
/* RemotePhy :: rp_nextPage_4 :: reserved0 [15:11] */
#define REMOTEPHY_RP_NEXTPAGE_4_RESERVED0_MASK                     0xf800
#define REMOTEPHY_RP_NEXTPAGE_4_RESERVED0_ALIGN                    0
#define REMOTEPHY_RP_NEXTPAGE_4_RESERVED0_BITS                     5
#define REMOTEPHY_RP_NEXTPAGE_4_RESERVED0_SHIFT                    11

/* RemotePhy :: rp_nextPage_4 :: rp_nextPage_4 [10:00] */
#define REMOTEPHY_RP_NEXTPAGE_4_RP_NEXTPAGE_4_MASK                 0x07ff
#define REMOTEPHY_RP_NEXTPAGE_4_RP_NEXTPAGE_4_ALIGN                0
#define REMOTEPHY_RP_NEXTPAGE_4_RP_NEXTPAGE_4_BITS                 11
#define REMOTEPHY_RP_NEXTPAGE_4_RP_NEXTPAGE_4_SHIFT                0


/****************************************************************************
 * RemotePhy :: Misc3
 ***************************************************************************/
/* RemotePhy :: Misc3 :: reserved0 [15:02] */
#define REMOTEPHY_MISC3_RESERVED0_MASK                             0xfffc
#define REMOTEPHY_MISC3_RESERVED0_ALIGN                            0
#define REMOTEPHY_MISC3_RESERVED0_BITS                             14
#define REMOTEPHY_MISC3_RESERVED0_SHIFT                            2

/* RemotePhy :: Misc3 :: rxSigdetPwrdn_override_val [01:01] */
#define REMOTEPHY_MISC3_RXSIGDETPWRDN_OVERRIDE_VAL_MASK            0x0002
#define REMOTEPHY_MISC3_RXSIGDETPWRDN_OVERRIDE_VAL_ALIGN           0
#define REMOTEPHY_MISC3_RXSIGDETPWRDN_OVERRIDE_VAL_BITS            1
#define REMOTEPHY_MISC3_RXSIGDETPWRDN_OVERRIDE_VAL_SHIFT           1

/* RemotePhy :: Misc3 :: rxSigdetPwrdn_override [00:00] */
#define REMOTEPHY_MISC3_RXSIGDETPWRDN_OVERRIDE_MASK                0x0001
#define REMOTEPHY_MISC3_RXSIGDETPWRDN_OVERRIDE_ALIGN               0
#define REMOTEPHY_MISC3_RXSIGDETPWRDN_OVERRIDE_BITS                1
#define REMOTEPHY_MISC3_RXSIGDETPWRDN_OVERRIDE_SHIFT               0


/****************************************************************************
 * XGXS16G_USER_BAM_NextPage
 ***************************************************************************/
/****************************************************************************
 * BAM_NextPage :: mp5_NextPageCtrl
 ***************************************************************************/
/* BAM_NextPage :: mp5_NextPageCtrl :: reserved0 [15:04] */
#define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_RESERVED0_MASK               0xfff0
#define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_RESERVED0_ALIGN              0
#define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_RESERVED0_BITS               12
#define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_RESERVED0_SHIFT              4

/* BAM_NextPage :: mp5_NextPageCtrl :: np_sw_overRide_en [03:03] */
#define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_NP_SW_OVERRIDE_EN_MASK       0x0008
#define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_NP_SW_OVERRIDE_EN_ALIGN      0
#define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_NP_SW_OVERRIDE_EN_BITS       1
#define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_NP_SW_OVERRIDE_EN_SHIFT      3

/* BAM_NextPage :: mp5_NextPageCtrl :: teton_mode_up3_en [02:02] */
#define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_TETON_MODE_UP3_EN_MASK       0x0004
#define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_TETON_MODE_UP3_EN_ALIGN      0
#define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_TETON_MODE_UP3_EN_BITS       1
#define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_TETON_MODE_UP3_EN_SHIFT      2

/* BAM_NextPage :: mp5_NextPageCtrl :: teton_mode [01:01] */
#define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_TETON_MODE_MASK              0x0002
#define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_TETON_MODE_ALIGN             0
#define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_TETON_MODE_BITS              1
#define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_TETON_MODE_SHIFT             1

/* BAM_NextPage :: mp5_NextPageCtrl :: bam_mode [00:00] */
#define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_BAM_MODE_MASK                0x0001
#define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_BAM_MODE_ALIGN               0
#define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_BAM_MODE_BITS                1
#define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_BAM_MODE_SHIFT               0


/****************************************************************************
 * BAM_NextPage :: link_timer_offset1
 ***************************************************************************/
/* BAM_NextPage :: link_timer_offset1 :: sgmii_offset [15:08] */
#define BAM_NEXTPAGE_LINK_TIMER_OFFSET1_SGMII_OFFSET_MASK          0xff00
#define BAM_NEXTPAGE_LINK_TIMER_OFFSET1_SGMII_OFFSET_ALIGN         0
#define BAM_NEXTPAGE_LINK_TIMER_OFFSET1_SGMII_OFFSET_BITS          8
#define BAM_NEXTPAGE_LINK_TIMER_OFFSET1_SGMII_OFFSET_SHIFT         8

/* BAM_NextPage :: link_timer_offset1 :: max_offset [07:00] */
#define BAM_NEXTPAGE_LINK_TIMER_OFFSET1_MAX_OFFSET_MASK            0x00ff
#define BAM_NEXTPAGE_LINK_TIMER_OFFSET1_MAX_OFFSET_ALIGN           0
#define BAM_NEXTPAGE_LINK_TIMER_OFFSET1_MAX_OFFSET_BITS            8
#define BAM_NEXTPAGE_LINK_TIMER_OFFSET1_MAX_OFFSET_SHIFT           0


/****************************************************************************
 * BAM_NextPage :: link_timer_offset2
 ***************************************************************************/
/* BAM_NextPage :: link_timer_offset2 :: link_up_offset [15:08] */
#define BAM_NEXTPAGE_LINK_TIMER_OFFSET2_LINK_UP_OFFSET_MASK        0xff00
#define BAM_NEXTPAGE_LINK_TIMER_OFFSET2_LINK_UP_OFFSET_ALIGN       0
#define BAM_NEXTPAGE_LINK_TIMER_OFFSET2_LINK_UP_OFFSET_BITS        8
#define BAM_NEXTPAGE_LINK_TIMER_OFFSET2_LINK_UP_OFFSET_SHIFT       8

/* BAM_NextPage :: link_timer_offset2 :: link_down_offset [07:00] */
#define BAM_NEXTPAGE_LINK_TIMER_OFFSET2_LINK_DOWN_OFFSET_MASK      0x00ff
#define BAM_NEXTPAGE_LINK_TIMER_OFFSET2_LINK_DOWN_OFFSET_ALIGN     0
#define BAM_NEXTPAGE_LINK_TIMER_OFFSET2_LINK_DOWN_OFFSET_BITS      8
#define BAM_NEXTPAGE_LINK_TIMER_OFFSET2_LINK_DOWN_OFFSET_SHIFT     0


/****************************************************************************
 * BAM_NextPage :: link_timer_offset3
 ***************************************************************************/
/* BAM_NextPage :: link_timer_offset3 :: break_link_offset [15:08] */
#define BAM_NEXTPAGE_LINK_TIMER_OFFSET3_BREAK_LINK_OFFSET_MASK     0xff00
#define BAM_NEXTPAGE_LINK_TIMER_OFFSET3_BREAK_LINK_OFFSET_ALIGN    0
#define BAM_NEXTPAGE_LINK_TIMER_OFFSET3_BREAK_LINK_OFFSET_BITS     8
#define BAM_NEXTPAGE_LINK_TIMER_OFFSET3_BREAK_LINK_OFFSET_SHIFT    8

/* BAM_NextPage :: link_timer_offset3 :: np_link_offset [07:00] */
#define BAM_NEXTPAGE_LINK_TIMER_OFFSET3_NP_LINK_OFFSET_MASK        0x00ff
#define BAM_NEXTPAGE_LINK_TIMER_OFFSET3_NP_LINK_OFFSET_ALIGN       0
#define BAM_NEXTPAGE_LINK_TIMER_OFFSET3_NP_LINK_OFFSET_BITS        8
#define BAM_NEXTPAGE_LINK_TIMER_OFFSET3_NP_LINK_OFFSET_SHIFT       0


/****************************************************************************
 * BAM_NextPage :: oui_msb_field
 ***************************************************************************/
/* BAM_NextPage :: oui_msb_field :: reserved0 [15:11] */
#define BAM_NEXTPAGE_OUI_MSB_FIELD_RESERVED0_MASK                  0xf800
#define BAM_NEXTPAGE_OUI_MSB_FIELD_RESERVED0_ALIGN                 0
#define BAM_NEXTPAGE_OUI_MSB_FIELD_RESERVED0_BITS                  5
#define BAM_NEXTPAGE_OUI_MSB_FIELD_RESERVED0_SHIFT                 11

/* BAM_NextPage :: oui_msb_field :: oui_msb_field [10:00] */
#define BAM_NEXTPAGE_OUI_MSB_FIELD_OUI_MSB_FIELD_MASK              0x07ff
#define BAM_NEXTPAGE_OUI_MSB_FIELD_OUI_MSB_FIELD_ALIGN             0
#define BAM_NEXTPAGE_OUI_MSB_FIELD_OUI_MSB_FIELD_BITS              11
#define BAM_NEXTPAGE_OUI_MSB_FIELD_OUI_MSB_FIELD_SHIFT             0


/****************************************************************************
 * BAM_NextPage :: oui_lsb_field
 ***************************************************************************/
/* BAM_NextPage :: oui_lsb_field :: reserved0 [15:11] */
#define BAM_NEXTPAGE_OUI_LSB_FIELD_RESERVED0_MASK                  0xf800
#define BAM_NEXTPAGE_OUI_LSB_FIELD_RESERVED0_ALIGN                 0
#define BAM_NEXTPAGE_OUI_LSB_FIELD_RESERVED0_BITS                  5
#define BAM_NEXTPAGE_OUI_LSB_FIELD_RESERVED0_SHIFT                 11

/* BAM_NextPage :: oui_lsb_field :: oui_lsb_field [10:00] */
#define BAM_NEXTPAGE_OUI_LSB_FIELD_OUI_LSB_FIELD_MASK              0x07ff
#define BAM_NEXTPAGE_OUI_LSB_FIELD_OUI_LSB_FIELD_ALIGN             0
#define BAM_NEXTPAGE_OUI_LSB_FIELD_OUI_LSB_FIELD_BITS              11
#define BAM_NEXTPAGE_OUI_LSB_FIELD_OUI_LSB_FIELD_SHIFT             0


/****************************************************************************
 * BAM_NextPage :: bam_field
 ***************************************************************************/
/* BAM_NextPage :: bam_field :: reserved0 [15:11] */
#define BAM_NEXTPAGE_BAM_FIELD_RESERVED0_MASK                      0xf800
#define BAM_NEXTPAGE_BAM_FIELD_RESERVED0_ALIGN                     0
#define BAM_NEXTPAGE_BAM_FIELD_RESERVED0_BITS                      5
#define BAM_NEXTPAGE_BAM_FIELD_RESERVED0_SHIFT                     11

/* BAM_NextPage :: bam_field :: oui_1_0 [10:09] */
#define BAM_NEXTPAGE_BAM_FIELD_OUI_1_0_MASK                        0x0600
#define BAM_NEXTPAGE_BAM_FIELD_OUI_1_0_ALIGN                       0
#define BAM_NEXTPAGE_BAM_FIELD_OUI_1_0_BITS                        2
#define BAM_NEXTPAGE_BAM_FIELD_OUI_1_0_SHIFT                       9

/* BAM_NextPage :: bam_field :: bam_field [08:00] */
#define BAM_NEXTPAGE_BAM_FIELD_BAM_FIELD_MASK                      0x01ff
#define BAM_NEXTPAGE_BAM_FIELD_BAM_FIELD_ALIGN                     0
#define BAM_NEXTPAGE_BAM_FIELD_BAM_FIELD_BITS                      9
#define BAM_NEXTPAGE_BAM_FIELD_BAM_FIELD_SHIFT                     0


/****************************************************************************
 * BAM_NextPage :: ud_field
 ***************************************************************************/
/* BAM_NextPage :: ud_field :: reserved0 [15:11] */
#define BAM_NEXTPAGE_UD_FIELD_RESERVED0_MASK                       0xf800
#define BAM_NEXTPAGE_UD_FIELD_RESERVED0_ALIGN                      0
#define BAM_NEXTPAGE_UD_FIELD_RESERVED0_BITS                       5
#define BAM_NEXTPAGE_UD_FIELD_RESERVED0_SHIFT                      11

/* BAM_NextPage :: ud_field :: ud_reserved [10:06] */
#define BAM_NEXTPAGE_UD_FIELD_UD_RESERVED_MASK                     0x07c0
#define BAM_NEXTPAGE_UD_FIELD_UD_RESERVED_ALIGN                    0
#define BAM_NEXTPAGE_UD_FIELD_UD_RESERVED_BITS                     5
#define BAM_NEXTPAGE_UD_FIELD_UD_RESERVED_SHIFT                    6

/* BAM_NextPage :: ud_field :: remote_BN_page [05:05] */
#define BAM_NEXTPAGE_UD_FIELD_REMOTE_BN_PAGE_MASK                  0x0020
#define BAM_NEXTPAGE_UD_FIELD_REMOTE_BN_PAGE_ALIGN                 0
#define BAM_NEXTPAGE_UD_FIELD_REMOTE_BN_PAGE_BITS                  1
#define BAM_NEXTPAGE_UD_FIELD_REMOTE_BN_PAGE_SHIFT                 5

/* BAM_NextPage :: ud_field :: inband_MDIO [04:04] */
#define BAM_NEXTPAGE_UD_FIELD_INBAND_MDIO_MASK                     0x0010
#define BAM_NEXTPAGE_UD_FIELD_INBAND_MDIO_ALIGN                    0
#define BAM_NEXTPAGE_UD_FIELD_INBAND_MDIO_BITS                     1
#define BAM_NEXTPAGE_UD_FIELD_INBAND_MDIO_SHIFT                    4

/* BAM_NextPage :: ud_field :: autoneg_MDIO [03:03] */
#define BAM_NEXTPAGE_UD_FIELD_AUTONEG_MDIO_MASK                    0x0008
#define BAM_NEXTPAGE_UD_FIELD_AUTONEG_MDIO_ALIGN                   0
#define BAM_NEXTPAGE_UD_FIELD_AUTONEG_MDIO_BITS                    1
#define BAM_NEXTPAGE_UD_FIELD_AUTONEG_MDIO_SHIFT                   3

/* BAM_NextPage :: ud_field :: remote_serdes_phy [02:02] */
#define BAM_NEXTPAGE_UD_FIELD_REMOTE_SERDES_PHY_MASK               0x0004
#define BAM_NEXTPAGE_UD_FIELD_REMOTE_SERDES_PHY_ALIGN              0
#define BAM_NEXTPAGE_UD_FIELD_REMOTE_SERDES_PHY_BITS               1
#define BAM_NEXTPAGE_UD_FIELD_REMOTE_SERDES_PHY_SHIFT              2

/* BAM_NextPage :: ud_field :: remote_cu_phy [01:01] */
#define BAM_NEXTPAGE_UD_FIELD_REMOTE_CU_PHY_MASK                   0x0002
#define BAM_NEXTPAGE_UD_FIELD_REMOTE_CU_PHY_ALIGN                  0
#define BAM_NEXTPAGE_UD_FIELD_REMOTE_CU_PHY_BITS                   1
#define BAM_NEXTPAGE_UD_FIELD_REMOTE_CU_PHY_SHIFT                  1

/* BAM_NextPage :: ud_field :: over1g [00:00] */
#define BAM_NEXTPAGE_UD_FIELD_OVER1G_MASK                          0x0001
#define BAM_NEXTPAGE_UD_FIELD_OVER1G_ALIGN                         0
#define BAM_NEXTPAGE_UD_FIELD_OVER1G_BITS                          1
#define BAM_NEXTPAGE_UD_FIELD_OVER1G_SHIFT                         0


/****************************************************************************
 * BAM_NextPage :: lp_oui_msb_field
 ***************************************************************************/
/* BAM_NextPage :: lp_oui_msb_field :: reserved0 [15:11] */
#define BAM_NEXTPAGE_LP_OUI_MSB_FIELD_RESERVED0_MASK               0xf800
#define BAM_NEXTPAGE_LP_OUI_MSB_FIELD_RESERVED0_ALIGN              0
#define BAM_NEXTPAGE_LP_OUI_MSB_FIELD_RESERVED0_BITS               5
#define BAM_NEXTPAGE_LP_OUI_MSB_FIELD_RESERVED0_SHIFT              11

/* BAM_NextPage :: lp_oui_msb_field :: oui_msb_field [10:00] */
#define BAM_NEXTPAGE_LP_OUI_MSB_FIELD_OUI_MSB_FIELD_MASK           0x07ff
#define BAM_NEXTPAGE_LP_OUI_MSB_FIELD_OUI_MSB_FIELD_ALIGN          0
#define BAM_NEXTPAGE_LP_OUI_MSB_FIELD_OUI_MSB_FIELD_BITS           11
#define BAM_NEXTPAGE_LP_OUI_MSB_FIELD_OUI_MSB_FIELD_SHIFT          0


/****************************************************************************
 * BAM_NextPage :: lp_oui_lsb_field
 ***************************************************************************/
/* BAM_NextPage :: lp_oui_lsb_field :: reserved0 [15:11] */
#define BAM_NEXTPAGE_LP_OUI_LSB_FIELD_RESERVED0_MASK               0xf800
#define BAM_NEXTPAGE_LP_OUI_LSB_FIELD_RESERVED0_ALIGN              0
#define BAM_NEXTPAGE_LP_OUI_LSB_FIELD_RESERVED0_BITS               5
#define BAM_NEXTPAGE_LP_OUI_LSB_FIELD_RESERVED0_SHIFT              11

/* BAM_NextPage :: lp_oui_lsb_field :: oui_lsb_field [10:00] */
#define BAM_NEXTPAGE_LP_OUI_LSB_FIELD_OUI_LSB_FIELD_MASK           0x07ff
#define BAM_NEXTPAGE_LP_OUI_LSB_FIELD_OUI_LSB_FIELD_ALIGN          0
#define BAM_NEXTPAGE_LP_OUI_LSB_FIELD_OUI_LSB_FIELD_BITS           11
#define BAM_NEXTPAGE_LP_OUI_LSB_FIELD_OUI_LSB_FIELD_SHIFT          0


/****************************************************************************
 * BAM_NextPage :: lp_bam_field
 ***************************************************************************/
/* BAM_NextPage :: lp_bam_field :: reserved0 [15:11] */
#define BAM_NEXTPAGE_LP_BAM_FIELD_RESERVED0_MASK                   0xf800
#define BAM_NEXTPAGE_LP_BAM_FIELD_RESERVED0_ALIGN                  0
#define BAM_NEXTPAGE_LP_BAM_FIELD_RESERVED0_BITS                   5
#define BAM_NEXTPAGE_LP_BAM_FIELD_RESERVED0_SHIFT                  11

/* BAM_NextPage :: lp_bam_field :: oui_1_0 [10:09] */
#define BAM_NEXTPAGE_LP_BAM_FIELD_OUI_1_0_MASK                     0x0600
#define BAM_NEXTPAGE_LP_BAM_FIELD_OUI_1_0_ALIGN                    0
#define BAM_NEXTPAGE_LP_BAM_FIELD_OUI_1_0_BITS                     2
#define BAM_NEXTPAGE_LP_BAM_FIELD_OUI_1_0_SHIFT                    9

/* BAM_NextPage :: lp_bam_field :: bam_field [08:00] */
#define BAM_NEXTPAGE_LP_BAM_FIELD_BAM_FIELD_MASK                   0x01ff
#define BAM_NEXTPAGE_LP_BAM_FIELD_BAM_FIELD_ALIGN                  0
#define BAM_NEXTPAGE_LP_BAM_FIELD_BAM_FIELD_BITS                   9
#define BAM_NEXTPAGE_LP_BAM_FIELD_BAM_FIELD_SHIFT                  0


/****************************************************************************
 * BAM_NextPage :: lp_ud_field
 ***************************************************************************/
/* BAM_NextPage :: lp_ud_field :: reserved0 [15:11] */
#define BAM_NEXTPAGE_LP_UD_FIELD_RESERVED0_MASK                    0xf800
#define BAM_NEXTPAGE_LP_UD_FIELD_RESERVED0_ALIGN                   0
#define BAM_NEXTPAGE_LP_UD_FIELD_RESERVED0_BITS                    5
#define BAM_NEXTPAGE_LP_UD_FIELD_RESERVED0_SHIFT                   11

/* BAM_NextPage :: lp_ud_field :: ud_reserved [10:06] */
#define BAM_NEXTPAGE_LP_UD_FIELD_UD_RESERVED_MASK                  0x07c0
#define BAM_NEXTPAGE_LP_UD_FIELD_UD_RESERVED_ALIGN                 0
#define BAM_NEXTPAGE_LP_UD_FIELD_UD_RESERVED_BITS                  5
#define BAM_NEXTPAGE_LP_UD_FIELD_UD_RESERVED_SHIFT                 6

/* BAM_NextPage :: lp_ud_field :: remote_BN_page [05:05] */
#define BAM_NEXTPAGE_LP_UD_FIELD_REMOTE_BN_PAGE_MASK               0x0020
#define BAM_NEXTPAGE_LP_UD_FIELD_REMOTE_BN_PAGE_ALIGN              0
#define BAM_NEXTPAGE_LP_UD_FIELD_REMOTE_BN_PAGE_BITS               1
#define BAM_NEXTPAGE_LP_UD_FIELD_REMOTE_BN_PAGE_SHIFT              5

/* BAM_NextPage :: lp_ud_field :: inband_MDIO [04:04] */
#define BAM_NEXTPAGE_LP_UD_FIELD_INBAND_MDIO_MASK                  0x0010
#define BAM_NEXTPAGE_LP_UD_FIELD_INBAND_MDIO_ALIGN                 0
#define BAM_NEXTPAGE_LP_UD_FIELD_INBAND_MDIO_BITS                  1
#define BAM_NEXTPAGE_LP_UD_FIELD_INBAND_MDIO_SHIFT                 4

/* BAM_NextPage :: lp_ud_field :: autoneg_MDIO [03:03] */
#define BAM_NEXTPAGE_LP_UD_FIELD_AUTONEG_MDIO_MASK                 0x0008
#define BAM_NEXTPAGE_LP_UD_FIELD_AUTONEG_MDIO_ALIGN                0
#define BAM_NEXTPAGE_LP_UD_FIELD_AUTONEG_MDIO_BITS                 1
#define BAM_NEXTPAGE_LP_UD_FIELD_AUTONEG_MDIO_SHIFT                3

/* BAM_NextPage :: lp_ud_field :: remote_serdes_phy [02:02] */
#define BAM_NEXTPAGE_LP_UD_FIELD_REMOTE_SERDES_PHY_MASK            0x0004
#define BAM_NEXTPAGE_LP_UD_FIELD_REMOTE_SERDES_PHY_ALIGN           0
#define BAM_NEXTPAGE_LP_UD_FIELD_REMOTE_SERDES_PHY_BITS            1
#define BAM_NEXTPAGE_LP_UD_FIELD_REMOTE_SERDES_PHY_SHIFT           2

/* BAM_NextPage :: lp_ud_field :: remote_cu_phy [01:01] */
#define BAM_NEXTPAGE_LP_UD_FIELD_REMOTE_CU_PHY_MASK                0x0002
#define BAM_NEXTPAGE_LP_UD_FIELD_REMOTE_CU_PHY_ALIGN               0
#define BAM_NEXTPAGE_LP_UD_FIELD_REMOTE_CU_PHY_BITS                1
#define BAM_NEXTPAGE_LP_UD_FIELD_REMOTE_CU_PHY_SHIFT               1

/* BAM_NextPage :: lp_ud_field :: over1g [00:00] */
#define BAM_NEXTPAGE_LP_UD_FIELD_OVER1G_MASK                       0x0001
#define BAM_NEXTPAGE_LP_UD_FIELD_OVER1G_ALIGN                      0
#define BAM_NEXTPAGE_LP_UD_FIELD_OVER1G_BITS                       1
#define BAM_NEXTPAGE_LP_UD_FIELD_OVER1G_SHIFT                      0


/****************************************************************************
 * XGXS16G_USER_CL73_UserB0
 ***************************************************************************/
/****************************************************************************
 * CL73_UserB0 :: CL73_UCtrl1
 ***************************************************************************/
/* CL73_UserB0 :: CL73_UCtrl1 :: reserved0 [15:13] */
#define CL73_USERB0_CL73_UCTRL1_RESERVED0_MASK                     0xe000
#define CL73_USERB0_CL73_UCTRL1_RESERVED0_ALIGN                    0
#define CL73_USERB0_CL73_UCTRL1_RESERVED0_BITS                     3
#define CL73_USERB0_CL73_UCTRL1_RESERVED0_SHIFT                    13

/* CL73_UserB0 :: CL73_UCtrl1 :: cl73_lossOfSyncFail_en [12:12] */
#define CL73_USERB0_CL73_UCTRL1_CL73_LOSSOFSYNCFAIL_EN_MASK        0x1000
#define CL73_USERB0_CL73_UCTRL1_CL73_LOSSOFSYNCFAIL_EN_ALIGN       0
#define CL73_USERB0_CL73_UCTRL1_CL73_LOSSOFSYNCFAIL_EN_BITS        1
#define CL73_USERB0_CL73_UCTRL1_CL73_LOSSOFSYNCFAIL_EN_SHIFT       12

/* CL73_UserB0 :: CL73_UCtrl1 :: cl73_parDet_dis [11:11] */
#define CL73_USERB0_CL73_UCTRL1_CL73_PARDET_DIS_MASK               0x0800
#define CL73_USERB0_CL73_UCTRL1_CL73_PARDET_DIS_ALIGN              0
#define CL73_USERB0_CL73_UCTRL1_CL73_PARDET_DIS_BITS               1
#define CL73_USERB0_CL73_UCTRL1_CL73_PARDET_DIS_SHIFT              11

/* CL73_UserB0 :: CL73_UCtrl1 :: cl73_allowCl37AN [10:10] */
#define CL73_USERB0_CL73_UCTRL1_CL73_ALLOWCL37AN_MASK              0x0400
#define CL73_USERB0_CL73_UCTRL1_CL73_ALLOWCL37AN_ALIGN             0
#define CL73_USERB0_CL73_UCTRL1_CL73_ALLOWCL37AN_BITS              1
#define CL73_USERB0_CL73_UCTRL1_CL73_ALLOWCL37AN_SHIFT             10

/* CL73_UserB0 :: CL73_UCtrl1 :: longParDetTimer_dis [09:09] */
#define CL73_USERB0_CL73_UCTRL1_LONGPARDETTIMER_DIS_MASK           0x0200
#define CL73_USERB0_CL73_UCTRL1_LONGPARDETTIMER_DIS_ALIGN          0
#define CL73_USERB0_CL73_UCTRL1_LONGPARDETTIMER_DIS_BITS           1
#define CL73_USERB0_CL73_UCTRL1_LONGPARDETTIMER_DIS_SHIFT          9

/* CL73_UserB0 :: CL73_UCtrl1 :: linkFailTimer_dis [08:08] */
#define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMER_DIS_MASK             0x0100
#define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMER_DIS_ALIGN            0
#define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMER_DIS_BITS             1
#define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMER_DIS_SHIFT            8

/* CL73_UserB0 :: CL73_UCtrl1 :: linkFailTimerQual_en [07:07] */
#define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMERQUAL_EN_MASK          0x0080
#define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMERQUAL_EN_ALIGN         0
#define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMERQUAL_EN_BITS          1
#define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMERQUAL_EN_SHIFT         7

/* CL73_UserB0 :: CL73_UCtrl1 :: cl73_nonce_match_over [06:06] */
#define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_OVER_MASK         0x0040
#define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_OVER_ALIGN        0
#define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_OVER_BITS         1
#define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_OVER_SHIFT        6

/* CL73_UserB0 :: CL73_UCtrl1 :: cl73_nonce_match_val [05:05] */
#define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_VAL_MASK          0x0020
#define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_VAL_ALIGN         0
#define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_VAL_BITS          1
#define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_VAL_SHIFT         5

/* CL73_UserB0 :: CL73_UCtrl1 :: couple_w_cl73_restart_wo_link_fail [04:04] */
#define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_WO_LINK_FAIL_MASK 0x0010
#define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_WO_LINK_FAIL_ALIGN 0
#define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_WO_LINK_FAIL_BITS 1
#define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_WO_LINK_FAIL_SHIFT 4

/* CL73_UserB0 :: CL73_UCtrl1 :: couple_w_cl73_restart [03:03] */
#define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_MASK         0x0008
#define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_ALIGN        0
#define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_BITS         1
#define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_SHIFT        3

/* CL73_UserB0 :: CL73_UCtrl1 :: couple_w_cl37_restart [02:02] */
#define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL37_RESTART_MASK         0x0004
#define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL37_RESTART_ALIGN        0
#define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL37_RESTART_BITS         1
#define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL37_RESTART_SHIFT        2

/* CL73_UserB0 :: CL73_UCtrl1 :: CL73_Ustat1_muxsel [01:01] */
#define CL73_USERB0_CL73_UCTRL1_CL73_USTAT1_MUXSEL_MASK            0x0002
#define CL73_USERB0_CL73_UCTRL1_CL73_USTAT1_MUXSEL_ALIGN           0
#define CL73_USERB0_CL73_UCTRL1_CL73_USTAT1_MUXSEL_BITS            1
#define CL73_USERB0_CL73_UCTRL1_CL73_USTAT1_MUXSEL_SHIFT           1

/* CL73_UserB0 :: CL73_UCtrl1 :: force_cl73_tx_omux_en [00:00] */
#define CL73_USERB0_CL73_UCTRL1_FORCE_CL73_TX_OMUX_EN_MASK         0x0001
#define CL73_USERB0_CL73_UCTRL1_FORCE_CL73_TX_OMUX_EN_ALIGN        0
#define CL73_USERB0_CL73_UCTRL1_FORCE_CL73_TX_OMUX_EN_BITS         1
#define CL73_USERB0_CL73_UCTRL1_FORCE_CL73_TX_OMUX_EN_SHIFT        0


/****************************************************************************
 * CL73_UserB0 :: CL73_Ustat1
 ***************************************************************************/
/* CL73_UserB0 :: CL73_Ustat1 :: reserved0 [15:10] */
#define CL73_USERB0_CL73_USTAT1_RESERVED0_MASK                     0xfc00
#define CL73_USERB0_CL73_USTAT1_RESERVED0_ALIGN                    0
#define CL73_USERB0_CL73_USTAT1_RESERVED0_BITS                     6
#define CL73_USERB0_CL73_USTAT1_RESERVED0_SHIFT                    10

/* CL73_UserB0 :: CL73_Ustat1 :: arb_fsm [09:00] */
#define CL73_USERB0_CL73_USTAT1_ARB_FSM_MASK                       0x03ff
#define CL73_USERB0_CL73_USTAT1_ARB_FSM_ALIGN                      0
#define CL73_USERB0_CL73_USTAT1_ARB_FSM_BITS                       10
#define CL73_USERB0_CL73_USTAT1_ARB_FSM_SHIFT                      0


/****************************************************************************
 * CL73_UserB0 :: CL73_BAMCtrl1
 ***************************************************************************/
/* CL73_UserB0 :: CL73_BAMCtrl1 :: CL73_bamEn [15:15] */
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMEN_MASK                  0x8000
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMEN_ALIGN                 0
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMEN_BITS                  1
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMEN_SHIFT                 15

/* CL73_UserB0 :: CL73_BAMCtrl1 :: CL73_bam_station_mngr_en [14:14] */
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_STATION_MNGR_EN_MASK    0x4000
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_STATION_MNGR_EN_ALIGN   0
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_STATION_MNGR_EN_BITS    1
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_STATION_MNGR_EN_SHIFT   14

/* CL73_UserB0 :: CL73_BAMCtrl1 :: CL73_bamNP_after_bp_en [13:13] */
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMNP_AFTER_BP_EN_MASK      0x2000
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMNP_AFTER_BP_EN_ALIGN     0
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMNP_AFTER_BP_EN_BITS      1
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMNP_AFTER_BP_EN_SHIFT     13

/* CL73_UserB0 :: CL73_BAMCtrl1 :: CL73_bam_test_MP5_halt_en [12:12] */
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_EN_MASK   0x1000
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_EN_ALIGN  0
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_EN_BITS   1
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_EN_SHIFT  12

/* CL73_UserB0 :: CL73_BAMCtrl1 :: CL73_bam_test_MP5_halt_step [11:11] */
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_STEP_MASK 0x0800
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_STEP_ALIGN 0
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_STEP_BITS 1
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_STEP_SHIFT 11

/* CL73_UserB0 :: CL73_BAMCtrl1 :: reserved0 [10:10] */
#define CL73_USERB0_CL73_BAMCTRL1_RESERVED0_MASK                   0x0400
#define CL73_USERB0_CL73_BAMCTRL1_RESERVED0_ALIGN                  0
#define CL73_USERB0_CL73_BAMCTRL1_RESERVED0_BITS                   1
#define CL73_USERB0_CL73_BAMCTRL1_RESERVED0_SHIFT                  10

/* CL73_UserB0 :: CL73_BAMCtrl1 :: UD_code_field [09:00] */
#define CL73_USERB0_CL73_BAMCTRL1_UD_CODE_FIELD_MASK               0x03ff
#define CL73_USERB0_CL73_BAMCTRL1_UD_CODE_FIELD_ALIGN              0
#define CL73_USERB0_CL73_BAMCTRL1_UD_CODE_FIELD_BITS               10
#define CL73_USERB0_CL73_BAMCTRL1_UD_CODE_FIELD_SHIFT              0


/****************************************************************************
 * CL73_UserB0 :: CL73_BAMCtrl2
 ***************************************************************************/
/* CL73_UserB0 :: CL73_BAMCtrl2 :: UD_code_field [15:00] */
#define CL73_USERB0_CL73_BAMCTRL2_UD_CODE_FIELD_MASK               0xffff
#define CL73_USERB0_CL73_BAMCTRL2_UD_CODE_FIELD_ALIGN              0
#define CL73_USERB0_CL73_BAMCTRL2_UD_CODE_FIELD_BITS               16
#define CL73_USERB0_CL73_BAMCTRL2_UD_CODE_FIELD_SHIFT              0


/****************************************************************************
 * CL73_UserB0 :: CL73_BAMCtrl3
 ***************************************************************************/
/* CL73_UserB0 :: CL73_BAMCtrl3 :: UD_code_field [15:00] */
#define CL73_USERB0_CL73_BAMCTRL3_UD_CODE_FIELD_MASK               0xffff
#define CL73_USERB0_CL73_BAMCTRL3_UD_CODE_FIELD_ALIGN              0
#define CL73_USERB0_CL73_BAMCTRL3_UD_CODE_FIELD_BITS               16
#define CL73_USERB0_CL73_BAMCTRL3_UD_CODE_FIELD_SHIFT              0


/****************************************************************************
 * CL73_UserB0 :: CL73_BAMStat1
 ***************************************************************************/
/* CL73_UserB0 :: CL73_BAMStat1 :: reserved0 [15:10] */
#define CL73_USERB0_CL73_BAMSTAT1_RESERVED0_MASK                   0xfc00
#define CL73_USERB0_CL73_BAMSTAT1_RESERVED0_ALIGN                  0
#define CL73_USERB0_CL73_BAMSTAT1_RESERVED0_BITS                   6
#define CL73_USERB0_CL73_BAMSTAT1_RESERVED0_SHIFT                  10

/* CL73_UserB0 :: CL73_BAMStat1 :: LP_UD_code_field [09:00] */
#define CL73_USERB0_CL73_BAMSTAT1_LP_UD_CODE_FIELD_MASK            0x03ff
#define CL73_USERB0_CL73_BAMSTAT1_LP_UD_CODE_FIELD_ALIGN           0
#define CL73_USERB0_CL73_BAMSTAT1_LP_UD_CODE_FIELD_BITS            10
#define CL73_USERB0_CL73_BAMSTAT1_LP_UD_CODE_FIELD_SHIFT           0


/****************************************************************************
 * CL73_UserB0 :: CL73_BAMStat2
 ***************************************************************************/
/* CL73_UserB0 :: CL73_BAMStat2 :: LP_UD_code_field [15:00] */
#define CL73_USERB0_CL73_BAMSTAT2_LP_UD_CODE_FIELD_MASK            0xffff
#define CL73_USERB0_CL73_BAMSTAT2_LP_UD_CODE_FIELD_ALIGN           0
#define CL73_USERB0_CL73_BAMSTAT2_LP_UD_CODE_FIELD_BITS            16
#define CL73_USERB0_CL73_BAMSTAT2_LP_UD_CODE_FIELD_SHIFT           0


/****************************************************************************
 * CL73_UserB0 :: CL73_BAMStat3
 ***************************************************************************/
/* CL73_UserB0 :: CL73_BAMStat3 :: LP_UD_code_field [15:00] */
#define CL73_USERB0_CL73_BAMSTAT3_LP_UD_CODE_FIELD_MASK            0xffff
#define CL73_USERB0_CL73_BAMSTAT3_LP_UD_CODE_FIELD_ALIGN           0
#define CL73_USERB0_CL73_BAMSTAT3_LP_UD_CODE_FIELD_BITS            16
#define CL73_USERB0_CL73_BAMSTAT3_LP_UD_CODE_FIELD_SHIFT           0

/****************************************************************************
 * FX100 :: Control1
 ***************************************************************************/
/* FX100 :: Control1 :: data_sampler_en [15:15] */
#define FX100_CONTROL1_DATA_SAMPLER_EN_MASK                        0x8000
#define FX100_CONTROL1_DATA_SAMPLER_EN_ALIGN                       0
#define FX100_CONTROL1_DATA_SAMPLER_EN_BITS                        1
#define FX100_CONTROL1_DATA_SAMPLER_EN_SHIFT                       15

/* FX100 :: Control1 :: fiber_autopwrdwn_wakeup [14:14] */
#define FX100_CONTROL1_FIBER_AUTOPWRDWN_WAKEUP_MASK                0x4000
#define FX100_CONTROL1_FIBER_AUTOPWRDWN_WAKEUP_ALIGN               0
#define FX100_CONTROL1_FIBER_AUTOPWRDWN_WAKEUP_BITS                1
#define FX100_CONTROL1_FIBER_AUTOPWRDWN_WAKEUP_SHIFT               14

/* FX100 :: Control1 :: fiber_autopwrdwn_sleep [13:13] */
#define FX100_CONTROL1_FIBER_AUTOPWRDWN_SLEEP_MASK                 0x2000
#define FX100_CONTROL1_FIBER_AUTOPWRDWN_SLEEP_ALIGN                0
#define FX100_CONTROL1_FIBER_AUTOPWRDWN_SLEEP_BITS                 1
#define FX100_CONTROL1_FIBER_AUTOPWRDWN_SLEEP_SHIFT                13

/* FX100 :: Control1 :: fiberautopwrdwn_en [12:12] */
#define FX100_CONTROL1_FIBERAUTOPWRDWN_EN_MASK                     0x1000
#define FX100_CONTROL1_FIBERAUTOPWRDWN_EN_ALIGN                    0
#define FX100_CONTROL1_FIBERAUTOPWRDWN_EN_BITS                     1
#define FX100_CONTROL1_FIBERAUTOPWRDWN_EN_SHIFT                    12

/* FX100 :: Control1 :: fiber_autopwrdwn_dis [11:11] */
#define FX100_CONTROL1_FIBER_AUTOPWRDWN_DIS_MASK                   0x0800
#define FX100_CONTROL1_FIBER_AUTOPWRDWN_DIS_ALIGN                  0
#define FX100_CONTROL1_FIBER_AUTOPWRDWN_DIS_BITS                   1
#define FX100_CONTROL1_FIBER_AUTOPWRDWN_DIS_SHIFT                  11

/* FX100 :: Control1 :: autodet_timer_sel [10:10] */
#define FX100_CONTROL1_AUTODET_TIMER_SEL_MASK                      0x0400
#define FX100_CONTROL1_AUTODET_TIMER_SEL_ALIGN                     0
#define FX100_CONTROL1_AUTODET_TIMER_SEL_BITS                      1
#define FX100_CONTROL1_AUTODET_TIMER_SEL_SHIFT                     10

/* FX100 :: Control1 :: rxdata_sel [09:06] */
#define FX100_CONTROL1_RXDATA_SEL_MASK                             0x03c0
#define FX100_CONTROL1_RXDATA_SEL_ALIGN                            0
#define FX100_CONTROL1_RXDATA_SEL_BITS                             4
#define FX100_CONTROL1_RXDATA_SEL_SHIFT                            6

/* FX100 :: Control1 :: disable_rx_qual [05:05] */
#define FX100_CONTROL1_DISABLE_RX_QUAL_MASK                        0x0020
#define FX100_CONTROL1_DISABLE_RX_QUAL_ALIGN                       0
#define FX100_CONTROL1_DISABLE_RX_QUAL_BITS                        1
#define FX100_CONTROL1_DISABLE_RX_QUAL_SHIFT                       5

/* FX100 :: Control1 :: force_rx_qual [04:04] */
#define FX100_CONTROL1_FORCE_RX_QUAL_MASK                          0x0010
#define FX100_CONTROL1_FORCE_RX_QUAL_ALIGN                         0
#define FX100_CONTROL1_FORCE_RX_QUAL_BITS                          1
#define FX100_CONTROL1_FORCE_RX_QUAL_SHIFT                         4

/* FX100 :: Control1 :: far_end_fault_en [03:03] */
#define FX100_CONTROL1_FAR_END_FAULT_EN_MASK                       0x0008
#define FX100_CONTROL1_FAR_END_FAULT_EN_ALIGN                      0
#define FX100_CONTROL1_FAR_END_FAULT_EN_BITS                       1
#define FX100_CONTROL1_FAR_END_FAULT_EN_SHIFT                      3

/* FX100 :: Control1 :: autodet_en [02:02] */
#define FX100_CONTROL1_AUTODET_EN_MASK                             0x0004
#define FX100_CONTROL1_AUTODET_EN_ALIGN                            0
#define FX100_CONTROL1_AUTODET_EN_BITS                             1
#define FX100_CONTROL1_AUTODET_EN_SHIFT                            2

/* FX100 :: Control1 :: full_duplex [01:01] */
#define FX100_CONTROL1_FULL_DUPLEX_MASK                            0x0002
#define FX100_CONTROL1_FULL_DUPLEX_ALIGN                           0
#define FX100_CONTROL1_FULL_DUPLEX_BITS                            1
#define FX100_CONTROL1_FULL_DUPLEX_SHIFT                           1

/* FX100 :: Control1 :: enable [00:00] */
#define FX100_CONTROL1_ENABLE_MASK                                 0x0001
#define FX100_CONTROL1_ENABLE_ALIGN                                0
#define FX100_CONTROL1_ENABLE_BITS                                 1
#define FX100_CONTROL1_ENABLE_SHIFT                                0


/****************************************************************************
 * FX100 :: Control2
 ***************************************************************************/
/* FX100 :: Control2 :: reserved0 [15:12] */
#define FX100_CONTROL2_RESERVED0_MASK                              0xf000
#define FX100_CONTROL2_RESERVED0_ALIGN                             0
#define FX100_CONTROL2_RESERVED0_BITS                              4
#define FX100_CONTROL2_RESERVED0_SHIFT                             12

/* FX100 :: Control2 :: ping_pong_disable [11:11] */
#define FX100_CONTROL2_PING_PONG_DISABLE_MASK                      0x0800
#define FX100_CONTROL2_PING_PONG_DISABLE_ALIGN                     0
#define FX100_CONTROL2_PING_PONG_DISABLE_BITS                      1
#define FX100_CONTROL2_PING_PONG_DISABLE_SHIFT                     11

/* FX100 :: Control2 :: pll_clk125_sw_ref [10:10] */
#define FX100_CONTROL2_PLL_CLK125_SW_REF_MASK                      0x0400
#define FX100_CONTROL2_PLL_CLK125_SW_REF_ALIGN                     0
#define FX100_CONTROL2_PLL_CLK125_SW_REF_BITS                      1
#define FX100_CONTROL2_PLL_CLK125_SW_REF_SHIFT                     10

/* FX100 :: Control2 :: pll_clk125_sw_en [09:09] */
#define FX100_CONTROL2_PLL_CLK125_SW_EN_MASK                       0x0200
#define FX100_CONTROL2_PLL_CLK125_SW_EN_ALIGN                      0
#define FX100_CONTROL2_PLL_CLK125_SW_EN_BITS                       1
#define FX100_CONTROL2_PLL_CLK125_SW_EN_SHIFT                      9

/* FX100 :: Control2 :: clk_out_1000_sw_def [08:08] */
#define FX100_CONTROL2_CLK_OUT_1000_SW_DEF_MASK                    0x0100
#define FX100_CONTROL2_CLK_OUT_1000_SW_DEF_ALIGN                   0
#define FX100_CONTROL2_CLK_OUT_1000_SW_DEF_BITS                    1
#define FX100_CONTROL2_CLK_OUT_1000_SW_DEF_SHIFT                   8

/* FX100 :: Control2 :: clk_out_1000_sw_en [07:07] */
#define FX100_CONTROL2_CLK_OUT_1000_SW_EN_MASK                     0x0080
#define FX100_CONTROL2_CLK_OUT_1000_SW_EN_ALIGN                    0
#define FX100_CONTROL2_CLK_OUT_1000_SW_EN_BITS                     1
#define FX100_CONTROL2_CLK_OUT_1000_SW_EN_SHIFT                    7

/* FX100 :: Control2 :: mii_rxc_out_sw_ref [06:06] */
#define FX100_CONTROL2_MII_RXC_OUT_SW_REF_MASK                     0x0040
#define FX100_CONTROL2_MII_RXC_OUT_SW_REF_ALIGN                    0
#define FX100_CONTROL2_MII_RXC_OUT_SW_REF_BITS                     1
#define FX100_CONTROL2_MII_RXC_OUT_SW_REF_SHIFT                    6

/* FX100 :: Control2 :: mii_rxc_out_sw_en [05:05] */
#define FX100_CONTROL2_MII_RXC_OUT_SW_EN_MASK                      0x0020
#define FX100_CONTROL2_MII_RXC_OUT_SW_EN_ALIGN                     0
#define FX100_CONTROL2_MII_RXC_OUT_SW_EN_BITS                      1
#define FX100_CONTROL2_MII_RXC_OUT_SW_EN_SHIFT                     5

/* FX100 :: Control2 :: mii_rxc_out_sm_rst [04:04] */
#define FX100_CONTROL2_MII_RXC_OUT_SM_RST_MASK                     0x0010
#define FX100_CONTROL2_MII_RXC_OUT_SM_RST_ALIGN                    0
#define FX100_CONTROL2_MII_RXC_OUT_SM_RST_BITS                     1
#define FX100_CONTROL2_MII_RXC_OUT_SM_RST_SHIFT                    4

/* FX100 :: Control2 :: mode_chg_nrst [03:03] */
#define FX100_CONTROL2_MODE_CHG_NRST_MASK                          0x0008
#define FX100_CONTROL2_MODE_CHG_NRST_ALIGN                         0
#define FX100_CONTROL2_MODE_CHG_NRST_BITS                          1
#define FX100_CONTROL2_MODE_CHG_NRST_SHIFT                         3

/* FX100 :: Control2 :: reset_rxfifo [02:02] */
#define FX100_CONTROL2_RESET_RXFIFO_MASK                           0x0004
#define FX100_CONTROL2_RESET_RXFIFO_ALIGN                          0
#define FX100_CONTROL2_RESET_RXFIFO_BITS                           1
#define FX100_CONTROL2_RESET_RXFIFO_SHIFT                          2

/* FX100 :: Control2 :: bypass_rxfifo [01:01] */
#define FX100_CONTROL2_BYPASS_RXFIFO_MASK                          0x0002
#define FX100_CONTROL2_BYPASS_RXFIFO_ALIGN                         0
#define FX100_CONTROL2_BYPASS_RXFIFO_BITS                          1
#define FX100_CONTROL2_BYPASS_RXFIFO_SHIFT                         1

/* FX100 :: Control2 :: extend_pkt_size [00:00] */
#define FX100_CONTROL2_EXTEND_PKT_SIZE_MASK                        0x0001
#define FX100_CONTROL2_EXTEND_PKT_SIZE_ALIGN                       0
#define FX100_CONTROL2_EXTEND_PKT_SIZE_BITS                        1
#define FX100_CONTROL2_EXTEND_PKT_SIZE_SHIFT                       0


/****************************************************************************
 * FX100 :: Control3
 ***************************************************************************/
/* FX100 :: Control3 :: number_of_idle [15:08] */
#define FX100_CONTROL3_NUMBER_OF_IDLE_MASK                         0xff00
#define FX100_CONTROL3_NUMBER_OF_IDLE_ALIGN                        0
#define FX100_CONTROL3_NUMBER_OF_IDLE_BITS                         8
#define FX100_CONTROL3_NUMBER_OF_IDLE_SHIFT                        8

/* FX100 :: Control3 :: correlator_disable [07:07] */
#define FX100_CONTROL3_CORRELATOR_DISABLE_MASK                     0x0080
#define FX100_CONTROL3_CORRELATOR_DISABLE_ALIGN                    0
#define FX100_CONTROL3_CORRELATOR_DISABLE_BITS                     1
#define FX100_CONTROL3_CORRELATOR_DISABLE_SHIFT                    7

/* FX100 :: Control3 :: bypass_nrz [06:06] */
#define FX100_CONTROL3_BYPASS_NRZ_MASK                             0x0040
#define FX100_CONTROL3_BYPASS_NRZ_ALIGN                            0
#define FX100_CONTROL3_BYPASS_NRZ_BITS                             1
#define FX100_CONTROL3_BYPASS_NRZ_SHIFT                            6

/* FX100 :: Control3 :: bypass_encoder [05:05] */
#define FX100_CONTROL3_BYPASS_ENCODER_MASK                         0x0020
#define FX100_CONTROL3_BYPASS_ENCODER_ALIGN                        0
#define FX100_CONTROL3_BYPASS_ENCODER_BITS                         1
#define FX100_CONTROL3_BYPASS_ENCODER_SHIFT                        5

/* FX100 :: Control3 :: bypass_alignment [04:04] */
#define FX100_CONTROL3_BYPASS_ALIGNMENT_MASK                       0x0010
#define FX100_CONTROL3_BYPASS_ALIGNMENT_ALIGN                      0
#define FX100_CONTROL3_BYPASS_ALIGNMENT_BITS                       1
#define FX100_CONTROL3_BYPASS_ALIGNMENT_SHIFT                      4

/* FX100 :: Control3 :: force_link [03:03] */
#define FX100_CONTROL3_FORCE_LINK_MASK                             0x0008
#define FX100_CONTROL3_FORCE_LINK_ALIGN                            0
#define FX100_CONTROL3_FORCE_LINK_BITS                             1
#define FX100_CONTROL3_FORCE_LINK_SHIFT                            3

/* FX100 :: Control3 :: force_lock [02:02] */
#define FX100_CONTROL3_FORCE_LOCK_MASK                             0x0004
#define FX100_CONTROL3_FORCE_LOCK_ALIGN                            0
#define FX100_CONTROL3_FORCE_LOCK_BITS                             1
#define FX100_CONTROL3_FORCE_LOCK_SHIFT                            2

/* FX100 :: Control3 :: fast_unlock_timer [01:01] */
#define FX100_CONTROL3_FAST_UNLOCK_TIMER_MASK                      0x0002
#define FX100_CONTROL3_FAST_UNLOCK_TIMER_ALIGN                     0
#define FX100_CONTROL3_FAST_UNLOCK_TIMER_BITS                      1
#define FX100_CONTROL3_FAST_UNLOCK_TIMER_SHIFT                     1

/* FX100 :: Control3 :: fast_timers [00:00] */
#define FX100_CONTROL3_FAST_TIMERS_MASK                            0x0001
#define FX100_CONTROL3_FAST_TIMERS_ALIGN                           0
#define FX100_CONTROL3_FAST_TIMERS_BITS                            1
#define FX100_CONTROL3_FAST_TIMERS_SHIFT                           0


/****************************************************************************
 * FX100 :: Status1
 ***************************************************************************/
/* FX100 :: Status1 :: mode_change [15:15] */
#define FX100_STATUS1_MODE_CHANGE_MASK                             0x8000
#define FX100_STATUS1_MODE_CHANGE_ALIGN                            0
#define FX100_STATUS1_MODE_CHANGE_BITS                             1
#define FX100_STATUS1_MODE_CHANGE_SHIFT                            15

/* FX100 :: Status1 :: reserved0 [14:12] */
#define FX100_STATUS1_RESERVED0_MASK                               0x7000
#define FX100_STATUS1_RESERVED0_ALIGN                              0
#define FX100_STATUS1_RESERVED0_BITS                               3
#define FX100_STATUS1_RESERVED0_SHIFT                              12

/* FX100 :: Status1 :: fiber_pwrdwn_status_chg [11:11] */
#define FX100_STATUS1_FIBER_PWRDWN_STATUS_CHG_MASK                 0x0800
#define FX100_STATUS1_FIBER_PWRDWN_STATUS_CHG_ALIGN                0
#define FX100_STATUS1_FIBER_PWRDWN_STATUS_CHG_BITS                 1
#define FX100_STATUS1_FIBER_PWRDWN_STATUS_CHG_SHIFT                11

/* FX100 :: Status1 :: fiber_pwrdwn [10:10] */
#define FX100_STATUS1_FIBER_PWRDWN_MASK                            0x0400
#define FX100_STATUS1_FIBER_PWRDWN_ALIGN                           0
#define FX100_STATUS1_FIBER_PWRDWN_BITS                            1
#define FX100_STATUS1_FIBER_PWRDWN_SHIFT                           10

/* FX100 :: Status1 :: link_status_chg [09:09] */
#define FX100_STATUS1_LINK_STATUS_CHG_MASK                         0x0200
#define FX100_STATUS1_LINK_STATUS_CHG_ALIGN                        0
#define FX100_STATUS1_LINK_STATUS_CHG_BITS                         1
#define FX100_STATUS1_LINK_STATUS_CHG_SHIFT                        9

/* FX100 :: Status1 :: bad_esd_detected [08:08] */
#define FX100_STATUS1_BAD_ESD_DETECTED_MASK                        0x0100
#define FX100_STATUS1_BAD_ESD_DETECTED_ALIGN                       0
#define FX100_STATUS1_BAD_ESD_DETECTED_BITS                        1
#define FX100_STATUS1_BAD_ESD_DETECTED_SHIFT                       8

/* FX100 :: Status1 :: false_carrier_detected [07:07] */
#define FX100_STATUS1_FALSE_CARRIER_DETECTED_MASK                  0x0080
#define FX100_STATUS1_FALSE_CARRIER_DETECTED_ALIGN                 0
#define FX100_STATUS1_FALSE_CARRIER_DETECTED_BITS                  1
#define FX100_STATUS1_FALSE_CARRIER_DETECTED_SHIFT                 7

/* FX100 :: Status1 :: tx_err_detected [06:06] */
#define FX100_STATUS1_TX_ERR_DETECTED_MASK                         0x0040
#define FX100_STATUS1_TX_ERR_DETECTED_ALIGN                        0
#define FX100_STATUS1_TX_ERR_DETECTED_BITS                         1
#define FX100_STATUS1_TX_ERR_DETECTED_SHIFT                        6

/* FX100 :: Status1 :: rx_err_detected [05:05] */
#define FX100_STATUS1_RX_ERR_DETECTED_MASK                         0x0020
#define FX100_STATUS1_RX_ERR_DETECTED_ALIGN                        0
#define FX100_STATUS1_RX_ERR_DETECTED_BITS                         1
#define FX100_STATUS1_RX_ERR_DETECTED_SHIFT                        5

/* FX100 :: Status1 :: lock_timer_expired [04:04] */
#define FX100_STATUS1_LOCK_TIMER_EXPIRED_MASK                      0x0010
#define FX100_STATUS1_LOCK_TIMER_EXPIRED_ALIGN                     0
#define FX100_STATUS1_LOCK_TIMER_EXPIRED_BITS                      1
#define FX100_STATUS1_LOCK_TIMER_EXPIRED_SHIFT                     4

/* FX100 :: Status1 :: lost_lock [03:03] */
#define FX100_STATUS1_LOST_LOCK_MASK                               0x0008
#define FX100_STATUS1_LOST_LOCK_ALIGN                              0
#define FX100_STATUS1_LOST_LOCK_BITS                               1
#define FX100_STATUS1_LOST_LOCK_SHIFT                              3

/* FX100 :: Status1 :: faulting [02:02] */
#define FX100_STATUS1_FAULTING_MASK                                0x0004
#define FX100_STATUS1_FAULTING_ALIGN                               0
#define FX100_STATUS1_FAULTING_BITS                                1
#define FX100_STATUS1_FAULTING_SHIFT                               2

/* FX100 :: Status1 :: locked [01:01] */
#define FX100_STATUS1_LOCKED_MASK                                  0x0002
#define FX100_STATUS1_LOCKED_ALIGN                                 0
#define FX100_STATUS1_LOCKED_BITS                                  1
#define FX100_STATUS1_LOCKED_SHIFT                                 1

/* FX100 :: Status1 :: link [00:00] */
#define FX100_STATUS1_LINK_MASK                                    0x0001
#define FX100_STATUS1_LINK_ALIGN                                   0
#define FX100_STATUS1_LINK_BITS                                    1
#define FX100_STATUS1_LINK_SHIFT                                   0


/****************************************************************************
 * XGXS16G_USER_aerBlk
 ***************************************************************************/
/****************************************************************************
 * aerBlk :: aer
 ***************************************************************************/
/* aerBlk :: aer :: MMD_deviceType [15:10] */
#define AERBLK_AER_MMD_DEVICETYPE_MASK                             0xfc00
#define AERBLK_AER_MMD_DEVICETYPE_ALIGN                            0
#define AERBLK_AER_MMD_DEVICETYPE_BITS                             6
#define AERBLK_AER_MMD_DEVICETYPE_SHIFT                            10

/* aerBlk :: aer :: MMD_port [09:00] */
#define AERBLK_AER_MMD_PORT_MASK                                   0x03ff
#define AERBLK_AER_MMD_PORT_ALIGN                                  0
#define AERBLK_AER_MMD_PORT_BITS                                   10
#define AERBLK_AER_MMD_PORT_SHIFT                                  0


/****************************************************************************
 * XGXS16G_USER_Combo_IEEE0
 ***************************************************************************/
/****************************************************************************
 * Combo_IEEE0 :: MIICntl
 ***************************************************************************/
/* Combo_IEEE0 :: MIICntl :: rst_hw [15:15] */
#define COMBO_IEEE0_MIICNTL_RST_HW_MASK                            0x8000
#define COMBO_IEEE0_MIICNTL_RST_HW_ALIGN                           0
#define COMBO_IEEE0_MIICNTL_RST_HW_BITS                            1
#define COMBO_IEEE0_MIICNTL_RST_HW_SHIFT                           15

/* Combo_IEEE0 :: MIICntl :: gloopback [14:14] */
#define COMBO_IEEE0_MIICNTL_GLOOPBACK_MASK                         0x4000
#define COMBO_IEEE0_MIICNTL_GLOOPBACK_ALIGN                        0
#define COMBO_IEEE0_MIICNTL_GLOOPBACK_BITS                         1
#define COMBO_IEEE0_MIICNTL_GLOOPBACK_SHIFT                        14

/* Combo_IEEE0 :: MIICntl :: manual_speed0 [13:13] */
#define COMBO_IEEE0_MIICNTL_MANUAL_SPEED0_MASK                     0x2000
#define COMBO_IEEE0_MIICNTL_MANUAL_SPEED0_ALIGN                    0
#define COMBO_IEEE0_MIICNTL_MANUAL_SPEED0_BITS                     1
#define COMBO_IEEE0_MIICNTL_MANUAL_SPEED0_SHIFT                    13

/* Combo_IEEE0 :: MIICntl :: autoneg_enable [12:12] */
#define COMBO_IEEE0_MIICNTL_AUTONEG_ENABLE_MASK                    0x1000
#define COMBO_IEEE0_MIICNTL_AUTONEG_ENABLE_ALIGN                   0
#define COMBO_IEEE0_MIICNTL_AUTONEG_ENABLE_BITS                    1
#define COMBO_IEEE0_MIICNTL_AUTONEG_ENABLE_SHIFT                   12

/* Combo_IEEE0 :: MIICntl :: pwrdwn_sw [11:11] */
#define COMBO_IEEE0_MIICNTL_PWRDWN_SW_MASK                         0x0800
#define COMBO_IEEE0_MIICNTL_PWRDWN_SW_ALIGN                        0
#define COMBO_IEEE0_MIICNTL_PWRDWN_SW_BITS                         1
#define COMBO_IEEE0_MIICNTL_PWRDWN_SW_SHIFT                        11

/* Combo_IEEE0 :: MIICntl :: reserved0 [10:10] */
#define COMBO_IEEE0_MIICNTL_RESERVED0_MASK                         0x0400
#define COMBO_IEEE0_MIICNTL_RESERVED0_ALIGN                        0
#define COMBO_IEEE0_MIICNTL_RESERVED0_BITS                         1
#define COMBO_IEEE0_MIICNTL_RESERVED0_SHIFT                        10

/* Combo_IEEE0 :: MIICntl :: restart_autoneg [09:09] */
#define COMBO_IEEE0_MIICNTL_RESTART_AUTONEG_MASK                   0x0200
#define COMBO_IEEE0_MIICNTL_RESTART_AUTONEG_ALIGN                  0
#define COMBO_IEEE0_MIICNTL_RESTART_AUTONEG_BITS                   1
#define COMBO_IEEE0_MIICNTL_RESTART_AUTONEG_SHIFT                  9

/* Combo_IEEE0 :: MIICntl :: full_duplex [08:08] */
#define COMBO_IEEE0_MIICNTL_FULL_DUPLEX_MASK                       0x0100
#define COMBO_IEEE0_MIICNTL_FULL_DUPLEX_ALIGN                      0
#define COMBO_IEEE0_MIICNTL_FULL_DUPLEX_BITS                       1
#define COMBO_IEEE0_MIICNTL_FULL_DUPLEX_SHIFT                      8

/* Combo_IEEE0 :: MIICntl :: collision_test_en [07:07] */
#define COMBO_IEEE0_MIICNTL_COLLISION_TEST_EN_MASK                 0x0080
#define COMBO_IEEE0_MIICNTL_COLLISION_TEST_EN_ALIGN                0
#define COMBO_IEEE0_MIICNTL_COLLISION_TEST_EN_BITS                 1
#define COMBO_IEEE0_MIICNTL_COLLISION_TEST_EN_SHIFT                7

/* Combo_IEEE0 :: MIICntl :: manual_speed1 [06:06] */
#define COMBO_IEEE0_MIICNTL_MANUAL_SPEED1_MASK                     0x0040
#define COMBO_IEEE0_MIICNTL_MANUAL_SPEED1_ALIGN                    0
#define COMBO_IEEE0_MIICNTL_MANUAL_SPEED1_BITS                     1
#define COMBO_IEEE0_MIICNTL_MANUAL_SPEED1_SHIFT                    6

/* Combo_IEEE0 :: MIICntl :: reserved1 [05:00] */
#define COMBO_IEEE0_MIICNTL_RESERVED1_MASK                         0x003f
#define COMBO_IEEE0_MIICNTL_RESERVED1_ALIGN                        0
#define COMBO_IEEE0_MIICNTL_RESERVED1_BITS                         6
#define COMBO_IEEE0_MIICNTL_RESERVED1_SHIFT                        0


/****************************************************************************
 * Combo_IEEE0 :: MIIStat
 ***************************************************************************/
/* Combo_IEEE0 :: MIIStat :: s100BASE_T4_capable [15:15] */
#define COMBO_IEEE0_MIISTAT_S100BASE_T4_CAPABLE_MASK               0x8000
#define COMBO_IEEE0_MIISTAT_S100BASE_T4_CAPABLE_ALIGN              0
#define COMBO_IEEE0_MIISTAT_S100BASE_T4_CAPABLE_BITS               1
#define COMBO_IEEE0_MIISTAT_S100BASE_T4_CAPABLE_SHIFT              15

/* Combo_IEEE0 :: MIIStat :: s100BASE_X_FULL_Duplex_capable [14:14] */
#define COMBO_IEEE0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_MASK    0x4000
#define COMBO_IEEE0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_ALIGN   0
#define COMBO_IEEE0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_BITS    1
#define COMBO_IEEE0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_SHIFT   14

/* Combo_IEEE0 :: MIIStat :: s100BASE_X_HALF_Duplex_capable [13:13] */
#define COMBO_IEEE0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_MASK    0x2000
#define COMBO_IEEE0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_ALIGN   0
#define COMBO_IEEE0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_BITS    1
#define COMBO_IEEE0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_SHIFT   13

/* Combo_IEEE0 :: MIIStat :: s10BASE_T_FULL_Duplex_capable [12:12] */
#define COMBO_IEEE0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_MASK     0x1000
#define COMBO_IEEE0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_ALIGN    0
#define COMBO_IEEE0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_BITS     1
#define COMBO_IEEE0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_SHIFT    12

/* Combo_IEEE0 :: MIIStat :: s10BASE_T_HALF_Duplex_capable [11:11] */
#define COMBO_IEEE0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_MASK     0x0800
#define COMBO_IEEE0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_ALIGN    0
#define COMBO_IEEE0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_BITS     1
#define COMBO_IEEE0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_SHIFT    11

/* Combo_IEEE0 :: MIIStat :: s100BASE_T2_FULL_Duplex_capable [10:10] */
#define COMBO_IEEE0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_MASK   0x0400
#define COMBO_IEEE0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_ALIGN  0
#define COMBO_IEEE0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_BITS   1
#define COMBO_IEEE0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_SHIFT  10

/* Combo_IEEE0 :: MIIStat :: s100BASE_T2_HALF_Duplex_capable [09:09] */
#define COMBO_IEEE0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_MASK   0x0200
#define COMBO_IEEE0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_ALIGN  0
#define COMBO_IEEE0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_BITS   1
#define COMBO_IEEE0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_SHIFT  9

/* Combo_IEEE0 :: MIIStat :: extended_status [08:08] */
#define COMBO_IEEE0_MIISTAT_EXTENDED_STATUS_MASK                   0x0100
#define COMBO_IEEE0_MIISTAT_EXTENDED_STATUS_ALIGN                  0
#define COMBO_IEEE0_MIISTAT_EXTENDED_STATUS_BITS                   1
#define COMBO_IEEE0_MIISTAT_EXTENDED_STATUS_SHIFT                  8

/* Combo_IEEE0 :: MIIStat :: reserved0 [07:07] */
#define COMBO_IEEE0_MIISTAT_RESERVED0_MASK                         0x0080
#define COMBO_IEEE0_MIISTAT_RESERVED0_ALIGN                        0
#define COMBO_IEEE0_MIISTAT_RESERVED0_BITS                         1
#define COMBO_IEEE0_MIISTAT_RESERVED0_SHIFT                        7

/* Combo_IEEE0 :: MIIStat :: mf_preamble_supression [06:06] */
#define COMBO_IEEE0_MIISTAT_MF_PREAMBLE_SUPRESSION_MASK            0x0040
#define COMBO_IEEE0_MIISTAT_MF_PREAMBLE_SUPRESSION_ALIGN           0
#define COMBO_IEEE0_MIISTAT_MF_PREAMBLE_SUPRESSION_BITS            1
#define COMBO_IEEE0_MIISTAT_MF_PREAMBLE_SUPRESSION_SHIFT           6

/* Combo_IEEE0 :: MIIStat :: autoneg_complete [05:05] */
#define COMBO_IEEE0_MIISTAT_AUTONEG_COMPLETE_MASK                  0x0020
#define COMBO_IEEE0_MIISTAT_AUTONEG_COMPLETE_ALIGN                 0
#define COMBO_IEEE0_MIISTAT_AUTONEG_COMPLETE_BITS                  1
#define COMBO_IEEE0_MIISTAT_AUTONEG_COMPLETE_SHIFT                 5

/* Combo_IEEE0 :: MIIStat :: remote_fault [04:04] */
#define COMBO_IEEE0_MIISTAT_REMOTE_FAULT_MASK                      0x0010
#define COMBO_IEEE0_MIISTAT_REMOTE_FAULT_ALIGN                     0
#define COMBO_IEEE0_MIISTAT_REMOTE_FAULT_BITS                      1
#define COMBO_IEEE0_MIISTAT_REMOTE_FAULT_SHIFT                     4

/* Combo_IEEE0 :: MIIStat :: autoneg_ability [03:03] */
#define COMBO_IEEE0_MIISTAT_AUTONEG_ABILITY_MASK                   0x0008
#define COMBO_IEEE0_MIISTAT_AUTONEG_ABILITY_ALIGN                  0
#define COMBO_IEEE0_MIISTAT_AUTONEG_ABILITY_BITS                   1
#define COMBO_IEEE0_MIISTAT_AUTONEG_ABILITY_SHIFT                  3

/* Combo_IEEE0 :: MIIStat :: link_status [02:02] */
#define COMBO_IEEE0_MIISTAT_LINK_STATUS_MASK                       0x0004
#define COMBO_IEEE0_MIISTAT_LINK_STATUS_ALIGN                      0
#define COMBO_IEEE0_MIISTAT_LINK_STATUS_BITS                       1
#define COMBO_IEEE0_MIISTAT_LINK_STATUS_SHIFT                      2

/* Combo_IEEE0 :: MIIStat :: jabber_detect [01:01] */
#define COMBO_IEEE0_MIISTAT_JABBER_DETECT_MASK                     0x0002
#define COMBO_IEEE0_MIISTAT_JABBER_DETECT_ALIGN                    0
#define COMBO_IEEE0_MIISTAT_JABBER_DETECT_BITS                     1
#define COMBO_IEEE0_MIISTAT_JABBER_DETECT_SHIFT                    1

/* Combo_IEEE0 :: MIIStat :: extended_capability [00:00] */
#define COMBO_IEEE0_MIISTAT_EXTENDED_CAPABILITY_MASK               0x0001
#define COMBO_IEEE0_MIISTAT_EXTENDED_CAPABILITY_ALIGN              0
#define COMBO_IEEE0_MIISTAT_EXTENDED_CAPABILITY_BITS               1
#define COMBO_IEEE0_MIISTAT_EXTENDED_CAPABILITY_SHIFT              0


/****************************************************************************
 * Combo_IEEE0 :: Id1
 ***************************************************************************/
/* Combo_IEEE0 :: Id1 :: regid [15:00] */
#define COMBO_IEEE0_ID1_REGID_MASK                                 0xffff
#define COMBO_IEEE0_ID1_REGID_ALIGN                                0
#define COMBO_IEEE0_ID1_REGID_BITS                                 16
#define COMBO_IEEE0_ID1_REGID_SHIFT                                0


/****************************************************************************
 * Combo_IEEE0 :: Id2
 ***************************************************************************/
/* Combo_IEEE0 :: Id2 :: regid [15:00] */
#define COMBO_IEEE0_ID2_REGID_MASK                                 0xffff
#define COMBO_IEEE0_ID2_REGID_ALIGN                                0
#define COMBO_IEEE0_ID2_REGID_BITS                                 16
#define COMBO_IEEE0_ID2_REGID_SHIFT                                0


/****************************************************************************
 * Combo_IEEE0 :: AutoNegAdv
 ***************************************************************************/
/* Combo_IEEE0 :: AutoNegAdv :: next_page [15:15] */
#define COMBO_IEEE0_AUTONEGADV_NEXT_PAGE_MASK                      0x8000
#define COMBO_IEEE0_AUTONEGADV_NEXT_PAGE_ALIGN                     0
#define COMBO_IEEE0_AUTONEGADV_NEXT_PAGE_BITS                      1
#define COMBO_IEEE0_AUTONEGADV_NEXT_PAGE_SHIFT                     15

/* Combo_IEEE0 :: AutoNegAdv :: reserved0 [14:14] */
#define COMBO_IEEE0_AUTONEGADV_RESERVED0_MASK                      0x4000
#define COMBO_IEEE0_AUTONEGADV_RESERVED0_ALIGN                     0
#define COMBO_IEEE0_AUTONEGADV_RESERVED0_BITS                      1
#define COMBO_IEEE0_AUTONEGADV_RESERVED0_SHIFT                     14

/* Combo_IEEE0 :: AutoNegAdv :: remote_fault [13:12] */
#define COMBO_IEEE0_AUTONEGADV_REMOTE_FAULT_MASK                   0x3000
#define COMBO_IEEE0_AUTONEGADV_REMOTE_FAULT_ALIGN                  0
#define COMBO_IEEE0_AUTONEGADV_REMOTE_FAULT_BITS                   2
#define COMBO_IEEE0_AUTONEGADV_REMOTE_FAULT_SHIFT                  12

/* Combo_IEEE0 :: AutoNegAdv :: reserved1 [11:09] */
#define COMBO_IEEE0_AUTONEGADV_RESERVED1_MASK                      0x0e00
#define COMBO_IEEE0_AUTONEGADV_RESERVED1_ALIGN                     0
#define COMBO_IEEE0_AUTONEGADV_RESERVED1_BITS                      3
#define COMBO_IEEE0_AUTONEGADV_RESERVED1_SHIFT                     9

/* Combo_IEEE0 :: AutoNegAdv :: pause [08:07] */
#define COMBO_IEEE0_AUTONEGADV_PAUSE_MASK                          0x0180
#define COMBO_IEEE0_AUTONEGADV_PAUSE_ALIGN                         0
#define COMBO_IEEE0_AUTONEGADV_PAUSE_BITS                          2
#define COMBO_IEEE0_AUTONEGADV_PAUSE_SHIFT                         7

/* Combo_IEEE0 :: AutoNegAdv :: half_duplex [06:06] */
#define COMBO_IEEE0_AUTONEGADV_HALF_DUPLEX_MASK                    0x0040
#define COMBO_IEEE0_AUTONEGADV_HALF_DUPLEX_ALIGN                   0
#define COMBO_IEEE0_AUTONEGADV_HALF_DUPLEX_BITS                    1
#define COMBO_IEEE0_AUTONEGADV_HALF_DUPLEX_SHIFT                   6

/* Combo_IEEE0 :: AutoNegAdv :: full_duplex [05:05] */
#define COMBO_IEEE0_AUTONEGADV_FULL_DUPLEX_MASK                    0x0020
#define COMBO_IEEE0_AUTONEGADV_FULL_DUPLEX_ALIGN                   0
#define COMBO_IEEE0_AUTONEGADV_FULL_DUPLEX_BITS                    1
#define COMBO_IEEE0_AUTONEGADV_FULL_DUPLEX_SHIFT                   5

/* Combo_IEEE0 :: AutoNegAdv :: reserved2 [04:00] */
#define COMBO_IEEE0_AUTONEGADV_RESERVED2_MASK                      0x001f
#define COMBO_IEEE0_AUTONEGADV_RESERVED2_ALIGN                     0
#define COMBO_IEEE0_AUTONEGADV_RESERVED2_BITS                      5
#define COMBO_IEEE0_AUTONEGADV_RESERVED2_SHIFT                     0


/****************************************************************************
 * Combo_IEEE0 :: AutoNegLPAbil
 ***************************************************************************/
/* Combo_IEEE0 :: AutoNegLPAbil :: next_page [15:15] */
#define COMBO_IEEE0_AUTONEGLPABIL_NEXT_PAGE_MASK                   0x8000
#define COMBO_IEEE0_AUTONEGLPABIL_NEXT_PAGE_ALIGN                  0
#define COMBO_IEEE0_AUTONEGLPABIL_NEXT_PAGE_BITS                   1
#define COMBO_IEEE0_AUTONEGLPABIL_NEXT_PAGE_SHIFT                  15

/* Combo_IEEE0 :: AutoNegLPAbil :: acknowledge [14:14] */
#define COMBO_IEEE0_AUTONEGLPABIL_ACKNOWLEDGE_MASK                 0x4000
#define COMBO_IEEE0_AUTONEGLPABIL_ACKNOWLEDGE_ALIGN                0
#define COMBO_IEEE0_AUTONEGLPABIL_ACKNOWLEDGE_BITS                 1
#define COMBO_IEEE0_AUTONEGLPABIL_ACKNOWLEDGE_SHIFT                14

/* Combo_IEEE0 :: AutoNegLPAbil :: remote_fault [13:12] */
#define COMBO_IEEE0_AUTONEGLPABIL_REMOTE_FAULT_MASK                0x3000
#define COMBO_IEEE0_AUTONEGLPABIL_REMOTE_FAULT_ALIGN               0
#define COMBO_IEEE0_AUTONEGLPABIL_REMOTE_FAULT_BITS                2
#define COMBO_IEEE0_AUTONEGLPABIL_REMOTE_FAULT_SHIFT               12

/* Combo_IEEE0 :: AutoNegLPAbil :: reserved0 [11:09] */
#define COMBO_IEEE0_AUTONEGLPABIL_RESERVED0_MASK                   0x0e00
#define COMBO_IEEE0_AUTONEGLPABIL_RESERVED0_ALIGN                  0
#define COMBO_IEEE0_AUTONEGLPABIL_RESERVED0_BITS                   3
#define COMBO_IEEE0_AUTONEGLPABIL_RESERVED0_SHIFT                  9

/* Combo_IEEE0 :: AutoNegLPAbil :: pause [08:07] */
#define COMBO_IEEE0_AUTONEGLPABIL_PAUSE_MASK                       0x0180
#define COMBO_IEEE0_AUTONEGLPABIL_PAUSE_ALIGN                      0
#define COMBO_IEEE0_AUTONEGLPABIL_PAUSE_BITS                       2
#define COMBO_IEEE0_AUTONEGLPABIL_PAUSE_SHIFT                      7

/* Combo_IEEE0 :: AutoNegLPAbil :: half_duplex [06:06] */
#define COMBO_IEEE0_AUTONEGLPABIL_HALF_DUPLEX_MASK                 0x0040
#define COMBO_IEEE0_AUTONEGLPABIL_HALF_DUPLEX_ALIGN                0
#define COMBO_IEEE0_AUTONEGLPABIL_HALF_DUPLEX_BITS                 1
#define COMBO_IEEE0_AUTONEGLPABIL_HALF_DUPLEX_SHIFT                6

/* Combo_IEEE0 :: AutoNegLPAbil :: full_duplex [05:05] */
#define COMBO_IEEE0_AUTONEGLPABIL_FULL_DUPLEX_MASK                 0x0020
#define COMBO_IEEE0_AUTONEGLPABIL_FULL_DUPLEX_ALIGN                0
#define COMBO_IEEE0_AUTONEGLPABIL_FULL_DUPLEX_BITS                 1
#define COMBO_IEEE0_AUTONEGLPABIL_FULL_DUPLEX_SHIFT                5

/* Combo_IEEE0 :: AutoNegLPAbil :: reserved1 [04:01] */
#define COMBO_IEEE0_AUTONEGLPABIL_RESERVED1_MASK                   0x001e
#define COMBO_IEEE0_AUTONEGLPABIL_RESERVED1_ALIGN                  0
#define COMBO_IEEE0_AUTONEGLPABIL_RESERVED1_BITS                   4
#define COMBO_IEEE0_AUTONEGLPABIL_RESERVED1_SHIFT                  1

/* Combo_IEEE0 :: AutoNegLPAbil :: sgmii_mode [00:00] */
#define COMBO_IEEE0_AUTONEGLPABIL_SGMII_MODE_MASK                  0x0001
#define COMBO_IEEE0_AUTONEGLPABIL_SGMII_MODE_ALIGN                 0
#define COMBO_IEEE0_AUTONEGLPABIL_SGMII_MODE_BITS                  1
#define COMBO_IEEE0_AUTONEGLPABIL_SGMII_MODE_SHIFT                 0


/****************************************************************************
 * Combo_IEEE0 :: AutoNegExp
 ***************************************************************************/
/* Combo_IEEE0 :: AutoNegExp :: reserved0 [15:03] */
#define COMBO_IEEE0_AUTONEGEXP_RESERVED0_MASK                      0xfff8
#define COMBO_IEEE0_AUTONEGEXP_RESERVED0_ALIGN                     0
#define COMBO_IEEE0_AUTONEGEXP_RESERVED0_BITS                      13
#define COMBO_IEEE0_AUTONEGEXP_RESERVED0_SHIFT                     3

/* Combo_IEEE0 :: AutoNegExp :: next_page_ability [02:02] */
#define COMBO_IEEE0_AUTONEGEXP_NEXT_PAGE_ABILITY_MASK              0x0004
#define COMBO_IEEE0_AUTONEGEXP_NEXT_PAGE_ABILITY_ALIGN             0
#define COMBO_IEEE0_AUTONEGEXP_NEXT_PAGE_ABILITY_BITS              1
#define COMBO_IEEE0_AUTONEGEXP_NEXT_PAGE_ABILITY_SHIFT             2

/* Combo_IEEE0 :: AutoNegExp :: page_received [01:01] */
#define COMBO_IEEE0_AUTONEGEXP_PAGE_RECEIVED_MASK                  0x0002
#define COMBO_IEEE0_AUTONEGEXP_PAGE_RECEIVED_ALIGN                 0
#define COMBO_IEEE0_AUTONEGEXP_PAGE_RECEIVED_BITS                  1
#define COMBO_IEEE0_AUTONEGEXP_PAGE_RECEIVED_SHIFT                 1

/* Combo_IEEE0 :: AutoNegExp :: reserved1 [00:00] */
#define COMBO_IEEE0_AUTONEGEXP_RESERVED1_MASK                      0x0001
#define COMBO_IEEE0_AUTONEGEXP_RESERVED1_ALIGN                     0
#define COMBO_IEEE0_AUTONEGEXP_RESERVED1_BITS                      1
#define COMBO_IEEE0_AUTONEGEXP_RESERVED1_SHIFT                     0


/****************************************************************************
 * Combo_IEEE0 :: AutoNegNP
 ***************************************************************************/
/* Combo_IEEE0 :: AutoNegNP :: Next_Page [15:15] */
#define COMBO_IEEE0_AUTONEGNP_NEXT_PAGE_MASK                       0x8000
#define COMBO_IEEE0_AUTONEGNP_NEXT_PAGE_ALIGN                      0
#define COMBO_IEEE0_AUTONEGNP_NEXT_PAGE_BITS                       1
#define COMBO_IEEE0_AUTONEGNP_NEXT_PAGE_SHIFT                      15

/* Combo_IEEE0 :: AutoNegNP :: Ack [14:14] */
#define COMBO_IEEE0_AUTONEGNP_ACK_MASK                             0x4000
#define COMBO_IEEE0_AUTONEGNP_ACK_ALIGN                            0
#define COMBO_IEEE0_AUTONEGNP_ACK_BITS                             1
#define COMBO_IEEE0_AUTONEGNP_ACK_SHIFT                            14

/* Combo_IEEE0 :: AutoNegNP :: Message_Page [13:13] */
#define COMBO_IEEE0_AUTONEGNP_MESSAGE_PAGE_MASK                    0x2000
#define COMBO_IEEE0_AUTONEGNP_MESSAGE_PAGE_ALIGN                   0
#define COMBO_IEEE0_AUTONEGNP_MESSAGE_PAGE_BITS                    1
#define COMBO_IEEE0_AUTONEGNP_MESSAGE_PAGE_SHIFT                   13

/* Combo_IEEE0 :: AutoNegNP :: Ack2 [12:12] */
#define COMBO_IEEE0_AUTONEGNP_ACK2_MASK                            0x1000
#define COMBO_IEEE0_AUTONEGNP_ACK2_ALIGN                           0
#define COMBO_IEEE0_AUTONEGNP_ACK2_BITS                            1
#define COMBO_IEEE0_AUTONEGNP_ACK2_SHIFT                           12

/* Combo_IEEE0 :: AutoNegNP :: Toggle [11:11] */
#define COMBO_IEEE0_AUTONEGNP_TOGGLE_MASK                          0x0800
#define COMBO_IEEE0_AUTONEGNP_TOGGLE_ALIGN                         0
#define COMBO_IEEE0_AUTONEGNP_TOGGLE_BITS                          1
#define COMBO_IEEE0_AUTONEGNP_TOGGLE_SHIFT                         11

/* Combo_IEEE0 :: AutoNegNP :: Message [10:00] */
#define COMBO_IEEE0_AUTONEGNP_MESSAGE_MASK                         0x07ff
#define COMBO_IEEE0_AUTONEGNP_MESSAGE_ALIGN                        0
#define COMBO_IEEE0_AUTONEGNP_MESSAGE_BITS                         11
#define COMBO_IEEE0_AUTONEGNP_MESSAGE_SHIFT                        0


/****************************************************************************
 * Combo_IEEE0 :: AutoNegLPAbil2
 ***************************************************************************/
/* Combo_IEEE0 :: AutoNegLPAbil2 :: Next_Page [15:15] */
#define COMBO_IEEE0_AUTONEGLPABIL2_NEXT_PAGE_MASK                  0x8000
#define COMBO_IEEE0_AUTONEGLPABIL2_NEXT_PAGE_ALIGN                 0
#define COMBO_IEEE0_AUTONEGLPABIL2_NEXT_PAGE_BITS                  1
#define COMBO_IEEE0_AUTONEGLPABIL2_NEXT_PAGE_SHIFT                 15

/* Combo_IEEE0 :: AutoNegLPAbil2 :: Ack [14:14] */
#define COMBO_IEEE0_AUTONEGLPABIL2_ACK_MASK                        0x4000
#define COMBO_IEEE0_AUTONEGLPABIL2_ACK_ALIGN                       0
#define COMBO_IEEE0_AUTONEGLPABIL2_ACK_BITS                        1
#define COMBO_IEEE0_AUTONEGLPABIL2_ACK_SHIFT                       14

/* Combo_IEEE0 :: AutoNegLPAbil2 :: Message_Page [13:13] */
#define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_PAGE_MASK               0x2000
#define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_PAGE_ALIGN              0
#define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_PAGE_BITS               1
#define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_PAGE_SHIFT              13

/* Combo_IEEE0 :: AutoNegLPAbil2 :: Ack2 [12:12] */
#define COMBO_IEEE0_AUTONEGLPABIL2_ACK2_MASK                       0x1000
#define COMBO_IEEE0_AUTONEGLPABIL2_ACK2_ALIGN                      0
#define COMBO_IEEE0_AUTONEGLPABIL2_ACK2_BITS                       1
#define COMBO_IEEE0_AUTONEGLPABIL2_ACK2_SHIFT                      12

/* Combo_IEEE0 :: AutoNegLPAbil2 :: Toggle [11:11] */
#define COMBO_IEEE0_AUTONEGLPABIL2_TOGGLE_MASK                     0x0800
#define COMBO_IEEE0_AUTONEGLPABIL2_TOGGLE_ALIGN                    0
#define COMBO_IEEE0_AUTONEGLPABIL2_TOGGLE_BITS                     1
#define COMBO_IEEE0_AUTONEGLPABIL2_TOGGLE_SHIFT                    11

/* Combo_IEEE0 :: AutoNegLPAbil2 :: Message [10:00] */
#define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_MASK                    0x07ff
#define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_ALIGN                   0
#define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_BITS                    11
#define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_SHIFT                   0


/****************************************************************************
 * Combo_IEEE0 :: MIIextStat
 ***************************************************************************/
/* Combo_IEEE0 :: MIIextStat :: s1000BASE_X_FULL_Duplex_capable [15:15] */
#define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_MASK 0x8000
#define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_ALIGN 0
#define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_BITS 1
#define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_SHIFT 15

/* Combo_IEEE0 :: MIIextStat :: s1000BASE_X_HALF_Duplex_capable [14:14] */
#define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_MASK 0x4000
#define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_ALIGN 0
#define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_BITS 1
#define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_SHIFT 14

/* Combo_IEEE0 :: MIIextStat :: s1000BASE_T_FULL_Duplex_capable [13:13] */
#define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_MASK 0x2000
#define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_ALIGN 0
#define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_BITS 1
#define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_SHIFT 13

/* Combo_IEEE0 :: MIIextStat :: s1000BASE_T_HALF_Duplex_capable [12:12] */
#define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_MASK 0x1000
#define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_ALIGN 0
#define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_BITS 1
#define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_SHIFT 12

/* Combo_IEEE0 :: MIIextStat :: reserved0 [11:00] */
#define COMBO_IEEE0_MIIEXTSTAT_RESERVED0_MASK                      0x0fff
#define COMBO_IEEE0_MIIEXTSTAT_RESERVED0_ALIGN                     0
#define COMBO_IEEE0_MIIEXTSTAT_RESERVED0_BITS                      12
#define COMBO_IEEE0_MIIEXTSTAT_RESERVED0_SHIFT                     0


/****************************************************************************
 * Datatype Definitions.
 ***************************************************************************/
#endif /*  _PHY_XGXS16G_H_ */

/* End of File */
